Information and coding theory has applications in telecommunication, where error detection and correction techniques enable reliable delivery of data over unreliable communication channels. Many communication channels are subject to noise. BCH technique is one of the most reliable error control techniques and the most important advantage of BCH technique is both detection and correction can be performed. The technique aims at detecting and correcting of two bit errors in a code-word of length 15 bits. A seven bit message was specifically chosen so that ASCII characters can be easily transmitted.

1. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014
INTERNATIONAL JOURNAL OF ELECTRONICS AND
17 – 19, July 2014, Mysore, Karnataka, India
COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)
ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)
Volume 5, Issue 8, August (2014), pp. 86-96
© IAEME: http://www.iaeme.com/IJECET.asp
Journal Impact Factor (2014): 7.2836 (Calculated by GISI)
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IJECET
© I A E M E
ERROR CONTROL CODING USING BOSE-CHAUDHURI-HOCQUENGHEM
86
(BCH) CODES
Eshtaartha Basu1, Dhanush.P2, Kishor S3, Geethashree A4
1, 2, 3Electronics and Communication Engineering, VVCE, P.B. No.206, Vijayanagar, Mysore, India,
4Asst. Prof., Electronics and Communication Engineering, VVCE, P.B. No.206, Vijayanagar,
Mysore, India
ABSTRACT
Information and coding theory has applications in telecommunication, where error detection
and correction techniques enable reliable delivery of data over unreliable communication channels.
Many communication channels are subject to noise. BCH technique is one of the most reliable error
control techniques and the most important advantage of BCH technique is both detection and
correction can be performed. The technique aims at detecting and correcting of two bit errors in a
code-word of length 15 bits. A seven bit message was specifically chosen so that ASCII characters
can be easily transmitted.
Keywords: BCH, codeword, encoder, decoder, syndrome
1. INTRODUCTION
In telecommunication, a communication system is a collection of individual communication
networks, transmission systems, relay stations, tributary stations, and data terminal equipment,
usually capable of interconnection and interoperation to form an integrated whole. The components
of a communication system serve a common purpose, are technically compatible, use common
procedures, respond to controls, and operate in union. Telecommunication is a method of
communication (e.g., for sports broadcasting, mass media, journalism, etc.). A communication
subsystem is a functional unit or operational assembly that is smaller than the larger assembly under
consideration.

2. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014
17 – 19, July 2014, Mysore, Karnataka, India
Fig. 1: Basic structure of communication system
The basic structure of a communication system is shown in Fig.1. A basic communication
system consists of an information source which generates the message. The generated message will
be in binary form. The transmitter will usually consist of an encoder which converts the digital
message into a form suitable for transmission. The encoded message is then fed into the
communication channel. The message usually gets corrupted due to the induced noise. The decoder
present in the receiver will detect and correct errors followed by decoding to retrieve the original
message.
The information can of course be anything representable in symbols. For our purposes, this
information should be representable as a string of binary digits. The purpose of the communication
system is to convey the information from one point to another with no degradation.
The noisy channel adds noise to the information without our consent, corrupting the
information to a degree related to the character and strength of the noise. The detailed behaviour of
communication systems in the presence of noise is a lengthy study in itself.
The most important concern mostly is the encoder and decoder blocks. These blocks
implement the coding systems spoken by Shannon, adding some extra bits in the encoder, and
removing them again in the decoder. The decoder detects errors, corrects errors, or a combination of
both. A good design will have the information on the input and output identical. Not surprisingly,
there are numerous coding systems. Each has a suitable area of service.
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1.1 Information and Coding Theory
A code is a rule for converting a piece of information (for example, a letter, word, phrase, or
gesture) into another - usually shortened or covert - form or representation, not necessarily of the
same type. In communication and information processing, encoding is the process by which
information from a source is converted into symbols to be communicated. Decoding is the reverse
process, converting these code symbols back into information understandable by a receiver.
One reason for coding is to enable communication in places where ordinary plain language,
spoken or written, is difficult or impossible.
1.2 Galois Field
In algebra, a finite field or Galois field is a field that contains a finite number of elements,
called its size.
Finite fields only exist for which the size is a prime power pk (where p is a prime number and
k is a positive integer). For each prime power, there is a finite field with this size, and all fields of a
given size are isomorphic. The characteristic of a field of size pk is p (this means that adding p copies
of any element always results in zero). In a finite field of size q, the polynomial Tq − T is the product
of q different linear factors, and, therefore, has all the elements of the field as roots. The
multiplicative group of the non-zero elements of a finite field is a cyclic group, and thus, the non-zero
elements can be expressed as the powers of a single (but generally not unique) element called a
primitive element.

3. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014
17 – 19, July 2014, Mysore, Karnataka, India
Finite fields are important in number theory, algebraic geometry, Galois Theory,
cryptography, and coding theory. The finite fields are classified by size; there is exactly one finite
field to isomorphism of size pk for each prime p and positive integer k. Each finite field of size q is
the splitting field of the polynomial xq - x, and thus the fixed field of the Frobenius endomorphism
which takes x to xq.
Finite fields appear in the following chain of class inclusions: Commutative rings Integral
domains integrally closed domains unique factorization domains principal ideal domains
Euclidean domains fields finite fields.
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2. BCH CODES
The BCH codes form a class of cyclic error-correcting codes that are constructed using finite
fields. BCH codes were invented in 1959 by French mathematician Alexis Hocquenghem, and
independently in 1960 by Raj Bose and D. K. Ray-Chaudhuri. The acronym BCH comprises the
initials of these inventors' names.
One of the key features of BCH codes is that during code design, there is a precise control
over the number of symbol errors correctable by the code. In particular, it is possible to design binary
BCH codes that can correct multiple bit errors. Another advantage of BCH codes is the ease with
which they can be decoded, namely, via an algebraic method known as syndrome decoding. This
simplifies the design of the decoder for these codes, using small low-power electronic hardware.
BCH codes are used in applications such as satellite communication, compact disc players,
DVDs, disk drives, solid-state drives and two-dimensional bar codes.
2.1 Description of BCH Cyclic Codes
BCH codes are a generalization of Hamming codes, and they can be designed to be able to
correct any error pattern of size t or less [1, 2, 4]. In this sense the generalization of the Hamming
codes extends the design of codes for t = 1 (Hamming codes) to codes for any desired higher value of
t (BCH codes). The design method is based on taking an LCM of appropriate minimal polynomials.
For any positive integer m 3 and t 2m−1, there exists a binary BCH code CBCH(n, k) with the
following properties:
Code length : n = 2m − 1
Number of parity bits : n − k mt
Minimum Hamming distance : dmin 2t + 1
Error-correction capability : t errors
These codes are able to correct any error pattern of size t or less, in a code vector of length
‘n’, n = 2m − 1. The generator polynomial of a BCH code is described in terms of its roots, taken
from the Galois field GF(2m). If is a primitive element in GF(2m), the generator polynomial g(X) of
a BCH code for correcting t errors in a code vector of length n = 2m − 1 is the minimum-degree
polynomial over GF(2) that has , 2, . . . , 2t as its roots given by Eq. (1).
g(i) = 0, i = 1, 2, . . . , 2t (1)
It also true that g(X) has i and conjugate as its roots. On the other hand, if i(X) is the
minimal polynomial of i then the LCM of 1(X), 2(X), . . . ,2t(X) is the generator polynomial
g(X) given by Eq. (2).
g(X) = LCM{ 1(X), 2(X), . . . , 2t(X)} (2)

4. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014
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However, and due to repetition of conjugate roots, it can be shown that the generator
polynomial g(X) can be formed with only the odd index minimal polynomials given by Eq. (3).
g(X) = LCM{ 1(X), 3(X), . . . , 2t−1(X)} (3)
Since the degree of each minimal polynomial is m or less, the degree of g(X) is at most mt.
As BCH codes are cyclic codes, this means that the value of n − k can be at most mt. The
Hamming codes are a particular class of BCH codes, for which the generator polynomial is g(X) =
1(X). A BCH code for t = 1 is then a Hamming code. Since is a primitive element of GF(2m), then
1(X) is a polynomial of degree m. [1][2]
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3. DESIGN AND ARCHITECTURE
BCH codes are a generalization of Hamming codes, and they can be designed to be able to
correct any error pattern of size ‘t’ or less.
3.1 Design specifications
In our system design of (15, 7) BCH code,
m=4
Code word length= 15,
Information length = 7,
Parity bits length = 8,
Block length = n = 2m –1 = 24 –1 = 15,
Number of parity bits = (n – k) mt; n–k = 15–7 = 8; mt = 4*2 = 8,
Therefore (n – k) = mt
Minimum distance = dmin 2t +1; dmin 4+1=5
These codes are able to correct any error pattern of size 2 or less, in a code vector of length ‘n’, n
= 2m − 1. The generator polynomial of a BCH code is described in terms of its roots, taken from the
Galois field GF (2m).
3.2 Overview of design
Fig.2 represents an overview of our design. The message is represented by 7 bits.
Specifically, the 7 bits are chosen, so that ASCII characters can be easily represented. The seven bit
message is fed into the BCH Encoder. The Encoder converts the seven bit message into a codeword
of length fifteen bits. The first seven bits are the message bits and the last eight bits are the redundant
bits.
The fifteen bit codeword is transmitted through the channel. The Error Introduction Module
will randomly flip any two or one bit which can be treated as virtual noise. Now, the codeword with
one or two bit error is fed into the BCH Decoder module.
Fig. 2: Overview of our design

5. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014
17 – 19, July 2014, Mysore, Karnataka, India
The Decoder module will calculate syndrome for the received codeword and then determine
the position of error bits using the same. Here error is corrected by flipping the error bits. Finally,
error free original message is retrieved back as the output of decoder.
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3.3 Encoder Design
The 7 bit information is represented by {u0, u1, u2, u3, u4, u5, u6}, then polynomial notation
can be used to show the information such as equation. Here, the bit position ‘n’ from 0 to 7
corresponds to the power of x such as Xn. The polynomial notation of information is given by
Eq. (4).
U(X) = u0 + u1.x1 + u2.x2+ u3.x3+ u4.x4+ u5.x5+ u6.x6 (4)
The 8-bit parity bits {r0, r1, r2, r3, r4, r5, r6, r7} can be represented by Eq. (5)
R(X) = r0 + r1.x1 + r2.x2+ r3.x3+ r4.x4+ r5.x5+ r6.x6+ r7.x7 (5)
r0, r1, …, r7 bits are 8 bits parity bits. These parity coefficients are 0 to 7th power of x. and
Information coefficients are 8 to 14th power of x. Then 15 bits Encoded information can be
represented by Eq. (6).
SB(X) = r0 + r1.x1 + r2.x2+ r3.x3+ r4.x4+ r5.x5+ r6.x6 + r7.x7+ u0.x8 + u1.x9 + u2.x10+ u3.x11
+ u4.x12+ u5.x13+ u6.x14 (6)
In BCH code, R(x) is remainder of U(x)*x8 divided by G(x). U(X).x8 is given by Eq. (7)
U(X).x8 = u0.x8 + u1.x9 + u2.x10+ u3.x11+ u4.x12+u5.x13+ u6.x14 (7)
G(x) = 1+x4+x6+x7+x8 (8)
Here, G(x) is called as the generator polynomial given by Eq. (8).
U(x)*x8 means the coefficients u0……….u6 are shift to higher bit by 8 bits. The order of G(x)
is 8. The remainder R(x) will be order of 7 or less. Here, calculation uses Galois field rule.
The remainder calculation is done using x8= 1+x4+x6+x7 iteratively and polynomial with
order more than 8 can be reduced to less than 7 given by Eq. (9). The result of polynomial is the
remainder polynomial.
x8 = 1+x4+x6+x7 (9)
However, during this computation, addition and/or subtraction between coefficients shall be
replaced by ex-or computation because of Galois field.
Fig. 3 shows the encoder circuit example. SIN input port receives information bits from u6,
u5……down to u0. During this input sequence, the switch is connected to A terminal in order to pass
those u6……..u0 signal to the output SB port and to the shift registers. Since the U(x)*x8 mod G(x)
is calculated, Eq. (10) is used to reduce the power of the polynomial of Eq. (7). Therefore,
x8 = 1+x4+x6+x7 (10)
The above equation means that if the coefficients of x8 = 1, coefficients of 0, 4, 6, 7th will be
exored with ‘1’. Consequently, after inputting all u6………to u0 to the registers, remainder will be

6. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014
17 – 19, July 2014, Mysore, Karnataka, India
calculated. Then after, the switch is connected to B terminal, remainder r7…….. r0 will be shifted out
to SB terminal. The detail operation is shown in Fig. 4.
Fig. 3: Circuit of encoder
In Fig. 5, a case of register values are shown as example.
The one corresponds to information bits = {0, 0, 0, 0, 0, 0, 1}.
Fig. 4: Timing diagram of encoder operation
Consider Fig. 4. The Information bits = {0, 0, 0, 0, 0, 0, 1}, u0 =1 and the value of r7, r0,
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r4and r6 is equal to one from Eq. (11).
x8= 1+x4+x6+x7 (11)
i.e., r7=r6=r4=r0=1.
Since this operation happens in cycle 7 (last cycle of switch A period), the values are just
shift out at the cycles from 8 to 15 as shown in Fig. 5.
Fig. 5: Encoder operation when information bits are {0, 0, 0, 0, 0, 0, 1}

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3.4 Error introduction module
This module will be integrated to encoder. Its main objective is to flip any two or one bit in
each code word, which is of length fifteen bits.
Fig. 6 shows example for code word input to error introduction module and output code word
with error.
Fig. 6: Error introduction module
3.5 Decoder Design
This section gives a brief idea about decoder design.
3.5.1 Syndrome calculation
The generator polynomial given by Eq. (12) is used in BCH(15,7) encoding.
G(x) = 1+x4+x6+x7+x8 (12)
SB(X) = u0.x8 + u1.x9 + u2.x10+ u3.x11+ u4.x12+u5.x13+ u6.x14 + r0 + r1.x1 + r2.x2+ r3.x3+r4.x4+ r5.x5+
r6.x6+ r7.x7 (13)
SB(x) given by Eq. (13) can be divided by G(x) and if remainder is 0, it can be judge that no
error exists in a code. Actually, BCH(15,7) can correct 2 bit errors in 15 bits codes. The generator
polynomial G(x) is given by Eq. (14).
G1(x) = 1+x+x4
G2(x) = 1+x+x2+x3+x4
G(x) = G1(x).G2(x)
G(x) = (1+x+x4).(1+x+x2+x3+x4)
G(x) = 1+x4+x6+x7+x8 (14)
Then, SB(x) can be divided by either G1(x) or G2(x). If no error in a code, both remainder of
G1(x) and G2(x) are both 0s.
SB(x) is transmitted. Then R(x) is received. If no error happened during transmission, R(x)
can be divided by both G1(x) and G2(x). Here we define Syndrome S1(x) = remainder of R(x) divided
by G1(x), S2(x) = remainder of R(x) divided by G2(x). Since both G1(x) and G2(x) is 4th order
polynomial, syndromes are power of 3 or less polynomials given by Eq. (15) and Eq. (16).
S1(x) = s10 + s11·x1 + s12·x2+ s13·x3 (15)
S2(x) = s20 + s21·x1 + s22·x2+ s23·x3 (16)

8. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014
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According to the coefficients (S10, S11, S12, S13) and
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S20, S21, S22, S23), error status can be
obtained. Since those coefficients are only 8 bits, then totally only 256 cases exists. Fig. 7 shows the
relation between 8 coefficient bits and error status.
The first cell (in Fig. 7) corresponds to syndrome = 0. This cell indicates no errors in code.
BLUE cells are corresponds to 1 bit error. Totally 15 cells are blue cells. The number in the blue cell
indicated the position of the error. Since the error is bit error, error can be recovered by flip the value
at the error position. The RED cell corresponds to 2 bit error. There are 15*14/2=105 cells. Each cell
indicates two error position values. Other 135 empty cells are more than 3 bit errors. The error
cannot be recovered.
In decoding, the two key functions are syndrome computation and Table access.
Fig. 7: Relation between 8 syndrome bits and error status
Fig. 8 can be used as Error position Indicator.
Fig. 8: Error position indicator
In Fig. 9, two linear feedback shift register circuits are shown in order to compute two
syndrome S1(x) and S2(x). In the figure, flip flops of linear feedback shift register is named t10-13, and
final computation results will appear in registers s10-13. Fig. 10 shows the operational timing diagram
of the circuit. In first 11 cycles, the switch is connected to a port, and then feedback operation
happens. Since first 11 cycles corresponds to 14th to 4th order of the xn and the power is larger than
order of syndromes, feedback operation is required. In last 4 cycles, the switch is connected to B port
and simple exor operation and shift operation are performed.
START signal is asserted to indicate the beginning and t10-13 flip flop outputs are forced to ‘0’
by AND gates for initializing. As you can see from Fig. 10, at the cycle of 14, syndrome values
appear in s10-13 flip flops. By accessing the Fig. 7 using the 8 syndrome bits and error status can be
found.

9. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014
17 – 19, July 2014, Mysore, Karnataka, India
Fig. 9: Syndrome computation circuit example
Fig. 10: Timing diagram of Syndrome computation
In Fig. 11, syndrome are computed from input YELLOW cell of
(1,0,0,0,0,0,0,1,1,1,0,1,0,0,0). In this case, the input does not include errors. Then the computed
syndromes in RED cells are all 0s.
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After de-assertion of RESET signal, ENCODER generates START and SBWE signals. Every
15 cycle is one BCH(15, 7) packet data. DECODER received SBWE signal and perform error
correction to generate RBEC signal which includes both information and parity. TOTBITS signal is
total received bits and ERRBITS is the number of error bits received. [3]

10. Proceedings of the 2nd International Conference on Current Trends in Engineering and Management ICCTEM -2014
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Fig. 11: Syndrome computation example (no error case)
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4. DESIGN VERIFICATION
This section provides a brief idea as to how the theoretical design was tested before practical
implementation.
4.1 C Modelling
The entire design was first tested using C language. A C model was developed to mimic the
operations of encoder, error introduction module and decoder. All the three modules were executed
together to verify their performance and synchronization.
4.2 C modelling results
The input message is seven bits wide. The encoder takes in the message and produces 15 bit
code-word. The user has to input the error bit locations. Error will be introduced in the code-word
correspondingly. At the decoder, Syndrome-1 and Syndrome-2 will be calculated to detect the
position of error. The errors will then be suitably corrected by flipping the error bit locations.
In Fig. 12, input message has seven bits. It will be encoded to obtain codeword of fifteen bits.
Fig. 12: Output of C Model
Using error introduction module fifth and ninth bits are flipped. The codeword word with
error is fed to decoder, which will calculate the syndromes according to error infused. Based on the
syndrome values error positions will be identified and rectified.

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5. CONCLUSION
A string of ASCII characters were successfully transmitted and received over the noisy
channel. One or two bits of the code-word were randomly flipped during its transmission over the
channel. The performance of the error control system was appreciable in detection and correction of
maximum two bits errors in each codeword of length 15. C model was developed to mimic the
operations of encoder, error introduction module and decoder to verify their performance and
synchronization.
REFERENCES
[1] S. Lin, and D.J. Costello Jr. - “Error Control Coding”, Prentice-Hall, New Jersey, 1983.
[2] Claude E. Shannon and Warren Weaver, “The Mathematical Theory of Communication”,
Chicago: University of Illinois Press, 1963.
[3] LSI Design Contest 2010, Okinawa - http://www.lsi-contest.com/index_e.html
[4] Vera Pless, “Introduction to the Theory of Error Correcting Codes”, 2nd ed., New York:
John Wiley Sons, 1989.