This project involves Hardware Implementation of TIAOXIN-346, a design submitted in CAESAR in relation to Authenticated Encryption Scheme. This design includes AES for Encryption and Decryption purpose. Presently working on Side Channel Attacks to test the design's security. Complete documentation is on the profile.
This presentation consists of Authenticated Encryption Decryption Scheme Project Idea, implementation and complete information. This Presentation was given at VLSI DESIGN CONFERENCE 2016 in Kolkata.
Security Hash Algorithm (SHA) was developed in 1993 by the National Institute of Standards and Technology (NIST) and National Security Agency (NSA).
It was designed as the algorithm to be used for secure hashing in the US Digital Signature Standard.
• Hashing function is one of the most commonly used encryption methods. A hash is a special mathematical function that performs one-way encryption.
• SHA-l is a revised version of SHA designed by NIST and was published as a Federal Information Processing Standard (FIPS).
• Like MD5, SHA-l processes input data in 512-bit blocks.
• SHA-l generates a 160-bit message digest. Whereas MD5 generated message digest of 128 bits.
• The procedure is used to send a non secret but signed message from sender to receiver. In such a case following steps are followed:
1. Sender feeds a plaintext message into SHA-l algorithm and obtains a 160-bit SHA-l hash.
2. Sender then signs the hash with his RSA private key and sends both the plaintext message and the signed hash to the receiver.
3. After receiving the message, the receiver computes the SHA-l hash himself and also applies the sender's public key to the signed hash to obtain the original hash H.
Simulated Analysis and Enhancement of Blowfish Algorithmiosrjce
This paper represents or analyzes the security of system based on Blowfish. Blowfish mainly focuses
on the encrypt and decrypt techniques and algorithms apply for cryptanalysis. It describe the algorithms for
encryption as well as decryption algorithms and also give the sufficient description of key generation, key
expansion, function and working principle of Blowfish cipher with proper explanations. Taking the current era,
Most of the famous systems which offer security for a network or web or to a data are vulnerability to attacks and
they are broken at some point of time by effective cryptanalysis methods, irrespective of its complex algorithmic
design. In the general, today’s cryptography world is bounded to an interpretive of following any one or multi
encryption scheme and that too for a single iteration on a single file only. This is evident in the maximum of the
encryption-decryption cases. It also describes the comparisons between older blowfish and enhances blowfish. It
also shows enhance Blowfish algorithm for encryption and decryption of data. It is also give the proper simulated
analysis of encryption and decryption time for different file formats using a windows application. It describe
feature of application and its process and efficiency as well as calculation of time and throughput.
This presentation consists of Authenticated Encryption Decryption Scheme Project Idea, implementation and complete information. This Presentation was given at VLSI DESIGN CONFERENCE 2016 in Kolkata.
Security Hash Algorithm (SHA) was developed in 1993 by the National Institute of Standards and Technology (NIST) and National Security Agency (NSA).
It was designed as the algorithm to be used for secure hashing in the US Digital Signature Standard.
• Hashing function is one of the most commonly used encryption methods. A hash is a special mathematical function that performs one-way encryption.
• SHA-l is a revised version of SHA designed by NIST and was published as a Federal Information Processing Standard (FIPS).
• Like MD5, SHA-l processes input data in 512-bit blocks.
• SHA-l generates a 160-bit message digest. Whereas MD5 generated message digest of 128 bits.
• The procedure is used to send a non secret but signed message from sender to receiver. In such a case following steps are followed:
1. Sender feeds a plaintext message into SHA-l algorithm and obtains a 160-bit SHA-l hash.
2. Sender then signs the hash with his RSA private key and sends both the plaintext message and the signed hash to the receiver.
3. After receiving the message, the receiver computes the SHA-l hash himself and also applies the sender's public key to the signed hash to obtain the original hash H.
Simulated Analysis and Enhancement of Blowfish Algorithmiosrjce
This paper represents or analyzes the security of system based on Blowfish. Blowfish mainly focuses
on the encrypt and decrypt techniques and algorithms apply for cryptanalysis. It describe the algorithms for
encryption as well as decryption algorithms and also give the sufficient description of key generation, key
expansion, function and working principle of Blowfish cipher with proper explanations. Taking the current era,
Most of the famous systems which offer security for a network or web or to a data are vulnerability to attacks and
they are broken at some point of time by effective cryptanalysis methods, irrespective of its complex algorithmic
design. In the general, today’s cryptography world is bounded to an interpretive of following any one or multi
encryption scheme and that too for a single iteration on a single file only. This is evident in the maximum of the
encryption-decryption cases. It also describes the comparisons between older blowfish and enhances blowfish. It
also shows enhance Blowfish algorithm for encryption and decryption of data. It is also give the proper simulated
analysis of encryption and decryption time for different file formats using a windows application. It describe
feature of application and its process and efficiency as well as calculation of time and throughput.
Design And Implementation Of Tiny Encryption AlgorithmIJERA Editor
Over the recent years, several smart applications like RFID‟s, sensor networks, including industrial systems, critical infrastructures, private and public spaces as well as portable and wearable applications in which highly constrained devices are interconnected, typically communicating wirelessly with one another, working in concert to accomplish some task. Advanced safety and security mechanisms can be very important in all of these areas. Light weight cryptography enables secure and efficient communication between networked smart objects. This proposed system focuses on the FPGA implementation of light weight cryptographic algorithm Tiny Encryption Algorithm TEA to adapt with many real time constraints such as memory, data loss and low cost. The proposed scheme uses Linear Feedback Shift Register to generate the random key making it more secure for sensitive information transfer in many real-time applications. In this study,operation of this cryptosystem is analyzed by implementing the cryptographic algorithm TEA with the key generation unit in FPGA Spartan 3E. We have also compared the results with the IDEA.
Shai Halevi discusses new ways to protect cloud data and security. Presented at "New Techniques for Protecting Cloud Data and Security" organized by the New York Technology Council.
Error control coding using bose chaudhuri hocquenghem bch codesIAEME Publication
Information and coding theory has applications in telecommunication, where error detection
and correction techniques enable reliable delivery of data over unreliable communication channels.
Many communication channels are subject to noise. BCH technique is one of the most reliable error
control techniques and the most important advantage of BCH technique is both detection and
correction can be performed. The technique aims at detecting and correcting of two bit errors in a
code-word of length 15 bits. A seven bit message was specifically chosen so that ASCII characters
can be easily transmitted.
Cloud computing is an ever-growing field in today‘s era.With the accumulation of data and the
advancement of technology,a large amount of data is generated everyday.Storage, availability and security of
the data form major concerns in the field of cloud computing.This paper focuses on homomorphic encryption,
which is largely used for security of data in the cloud.Homomorphic encryption is defined as the technique of
encryption in which specific operations can be carried out on the encrypted data.The data is stored on a remote
server.The task here is operating on the encrypted data.There are two types of homomorphic encryption, Fully
homomorphic encryption and patially homomorphic encryption.Fully homomorphic encryption allow arbitrary
computation on the ciphertext in a ring, while the partially homomorphic encryption is the one in which
addition or multiplication operations can be carried out on the normal ciphertext.Homomorphic encryption
plays a vital role in cloud computing as the encrypted data of companies is stored in a public cloud, thus taking
advantage of the cloud provider‘s services.Various algorithms and methods of homomorphic encryption that
have been proposed are discussed in this paper
Discrete Logarithmic Problem- Basis of Elliptic Curve CryptosystemsNIT Sikkim
ECC was developed in 1985 independently by Neal Koblitz and Victor Miller. Both men saw the application of the elliptic curve discrete log problem (ECDLP) as a replacement for the conventional discrete log problem (DLP) which is used in DSA, and the integer factorization problem found in RSA. For both problems, sub-exponential solutions have been generated; the
same which cannot be said for ECDLP . In addition to offering increased security for a smaller key size, operations of adding and doubling can be optimized successfully on a mobile
platform . ECC offers a viable replacement to the most common public-key cryptography algorithms on mobile devices.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
Design And Implementation Of Tiny Encryption AlgorithmIJERA Editor
Over the recent years, several smart applications like RFID‟s, sensor networks, including industrial systems, critical infrastructures, private and public spaces as well as portable and wearable applications in which highly constrained devices are interconnected, typically communicating wirelessly with one another, working in concert to accomplish some task. Advanced safety and security mechanisms can be very important in all of these areas. Light weight cryptography enables secure and efficient communication between networked smart objects. This proposed system focuses on the FPGA implementation of light weight cryptographic algorithm Tiny Encryption Algorithm TEA to adapt with many real time constraints such as memory, data loss and low cost. The proposed scheme uses Linear Feedback Shift Register to generate the random key making it more secure for sensitive information transfer in many real-time applications. In this study,operation of this cryptosystem is analyzed by implementing the cryptographic algorithm TEA with the key generation unit in FPGA Spartan 3E. We have also compared the results with the IDEA.
Shai Halevi discusses new ways to protect cloud data and security. Presented at "New Techniques for Protecting Cloud Data and Security" organized by the New York Technology Council.
Error control coding using bose chaudhuri hocquenghem bch codesIAEME Publication
Information and coding theory has applications in telecommunication, where error detection
and correction techniques enable reliable delivery of data over unreliable communication channels.
Many communication channels are subject to noise. BCH technique is one of the most reliable error
control techniques and the most important advantage of BCH technique is both detection and
correction can be performed. The technique aims at detecting and correcting of two bit errors in a
code-word of length 15 bits. A seven bit message was specifically chosen so that ASCII characters
can be easily transmitted.
Cloud computing is an ever-growing field in today‘s era.With the accumulation of data and the
advancement of technology,a large amount of data is generated everyday.Storage, availability and security of
the data form major concerns in the field of cloud computing.This paper focuses on homomorphic encryption,
which is largely used for security of data in the cloud.Homomorphic encryption is defined as the technique of
encryption in which specific operations can be carried out on the encrypted data.The data is stored on a remote
server.The task here is operating on the encrypted data.There are two types of homomorphic encryption, Fully
homomorphic encryption and patially homomorphic encryption.Fully homomorphic encryption allow arbitrary
computation on the ciphertext in a ring, while the partially homomorphic encryption is the one in which
addition or multiplication operations can be carried out on the normal ciphertext.Homomorphic encryption
plays a vital role in cloud computing as the encrypted data of companies is stored in a public cloud, thus taking
advantage of the cloud provider‘s services.Various algorithms and methods of homomorphic encryption that
have been proposed are discussed in this paper
Discrete Logarithmic Problem- Basis of Elliptic Curve CryptosystemsNIT Sikkim
ECC was developed in 1985 independently by Neal Koblitz and Victor Miller. Both men saw the application of the elliptic curve discrete log problem (ECDLP) as a replacement for the conventional discrete log problem (DLP) which is used in DSA, and the integer factorization problem found in RSA. For both problems, sub-exponential solutions have been generated; the
same which cannot be said for ECDLP . In addition to offering increased security for a smaller key size, operations of adding and doubling can be optimized successfully on a mobile
platform . ECC offers a viable replacement to the most common public-key cryptography algorithms on mobile devices.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
Dan Towner of ACCU Bristol & Bath, presenting at the Bristol IT MegaMeet 2013
This talk aims to demystify the clever parts of compilers that nobody ever told you about, explaining their inner secrets in simple terms. Come along to find out what induction variables do, what software pipelining is, how vectorisation works, how code scheduling is done, and how the debugger makes sense of it all.
See the video of the presentation here: http://www.youtube.com/watch?v=aeyf6wfxbL4
VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based o...IJECEIAES
This paper presents the electronic synthesis, VHDL design and implementation on FPGA of turbo decoders for Difference Set Codes (DSC) decoded by the majority logic (ML). The VHDL design is based on the decoding Equations that we have simplified, in order to reduce the complexity and is implemented on parallel process to increase the data rate. A co-simulation using the Dsp-Builder tool on a platform designed on Matlab/Simulink, allows the measurement of the performance in terms of BER (Bit Error Rate) as well as the decoder validation. These decoders can be a good choice for future digital transmission chains. For example, for the Turbo decoder based on the product code DSC (21.11)² with a quantization of 5 bits and for one complete iteration, the results show the possibility of integration of our entire turbo decoder on a single chip, with lower latency at 0.23 microseconds and data rate greater than 500 Mb/s.
A Cryptographic Hardware Revolution in Communication Systems using Verilog HDLidescitation
Advanced Encryption Standard (AES), is an
advancement of Federal Information Processing Standard
(FIPS) which is an initiated Process Standard of NIST. The
AES specifies the Rijndael algorithm, in which a symmetric
block cipher that processes fixed 128 bit data blocks using
cipher keys with different lengths of 128, 192 and 256 bits.
The earliest Rijndael algorithm had the advantage of
combining both data block sizes of 128, 192 and 256 bits with
any key lengths. AES can be programmed in pure hardware
Verilog HDL, Which includes Multiplexer to enhance more
secure to Cipher text. The results indicate that the hardware
implementation proposed in this project is Decrementing
Utilization of resource and power consumption of 113 mW
than other implementation. Using FPGA lead to reliability on
source modulations. This project presents the AES algorithm
with regard to FPGA and Verilog HDL. The software used for
Simulation is ModelSim-Altera 6.3g_p1 (Quartus II 8.1).
Synthesis and implementation of the code is carried out on
Xilinx ISE 13.4 (XC6VCX240T) device is used for hardware
evaluation.
Design and implementation of log domain decoder IJECEIAES
Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs a high data rate with very low BER.
We propose a simple and efficient searchable symmetric encryption scheme based on a Bitmap index that evaluates Boolean queries. Our scheme provides a practical solution in settings where communications and computations are very constrained as it offers a suitable trade-off between privacy and performance.
IP Core Design of Hight Lightweight Cipher and its Implementation csandit
In the present era of e-world where security has got a larger weightage, cryptography has its
role to play. Nowadays, the devices available in the market are of resource constrained type.
Hence we need lightweight ciphers for the efficient encryption of data thereby increasing the
performance. In this project a detailed study of HIGHT cryptographic algorithm is done which
outperforms standard algorithms. HIGHT is an ISO Standard block cipher which has 64-bit
block length and 128-bit key length. HIGHT was designed to be proper for the implementation
in the low resource environment such as WSN, WBN, RFID tag or tiny ubiquitous devices. It is
implemented on Spartan 6 FPGA evaluation kit and performance metrics are found out. A
HIGHT cryptocore is being designed, characterized and implemented which will be a reference
platform for hardware design engineers to model devices which require lightweight
characteristics.
IP CORE DESIGN OF HIGHT LIGHTWEIGHT CIPHER AND ITS IMPLEMENTATIONcscpconf
In the present era of e-world where security has got a larger weightage, cryptography has its
role to play. Nowadays, the devices available in the market are of resource constrained type.
Hence we need lightweight ciphers for the efficient encryption of data thereby increasing the
performance. In this project a detailed study of HIGHT cryptographic algorithm is done which outperforms standard algorithms. HIGHT is an ISO Standard block cipher which has 64-bit block length and 128-bit key length. HIGHT was designed to be proper for the implementation in the low resource environment such as WSN, WBN, RFID tag or tiny ubiquitous devices. It is implemented on Spartan 6 FPGA evaluation kit and performance metrics are found out. A HIGHT cryptocore is being designed, characterized and implemented which will be a reference platform for hardware design engineers to model devices which require lightweight characteristics.
Please download, and use Slideshow mode to view the slides, as that's where the magic of animation moves the telemetry frame elements around to illustrate the inner workings.
JPL / NASA Deep Space Network Telemetry
Similar to Authenticated Encryption Decryption Scheme (20)
Initially worked on a prototype for value estimations and later employed the prototype design on an E-Rickshaw. PWM based controller is used for charging Panels and allowing simultaneous charge discharge of batteries
AES and DES are two different crypto algorithms having different features. This projects consists of integrating these algorithms to develop a new structure. Here, read and write of text files is employed. Thus, the text files listed should exist in the same folder as the project is in. Implementation is carried in VHDL on Modelsim.
This design consists of two communication protocols integrated in SoC and are UART & SPI. -Single bit input is provided for user to select either UART or SPI. In UART protocol TRANSMITTER passes the 32 bit data serially with parity bit to RECEIVER. In SPI protocol, RECEIVER passes the data to another RECEIVER which finally returns data back to TRANSMITTER and the TRANSMITTER passes data to TOP MODULE.
8 bit Microprocessor with Single Vectored InterruptHardik Manocha
SoC consists of instruction memory, main memory and microprocessor unit. Instructions are fetched using PC and as per the instruction, main memory and register memory are accessed. 8 bit data bus is built. Working on developing programs to look for microprocessor operation.
Project consists of individual modules of encryption and decryption units. Standard T-DES algorithm is implemented. Presently working on to integrate DES with AES to develop stronger crypto algorithm and test the same against Side Channel Attacks and compare different algorithms.
This design involves the implementation AES 128. Inside top module, enc, dec and key_generation modules are available. Both enc and dec are controlled via respective resets. When enc executes, key_generation runs and further fills the key memory. dec unit on its execution extracts key from the same memory. Working on to test the design with Side Channel Attacks.
Advanced Encryption Standard (AES) with Dynamic Substitution BoxHardik Manocha
AES algorithm has been stated as secure against any attack but increasing fast computing is making hackers to develop the cracks for AES as well. Therefore to further increase the security of AES, i tried to replace Standard static and fixed Substitution Box with a dynamic S Box. Dynamicity is brought with the help of Input key. Static S box is altered using the input key and the new generated s box is used for encryption. Reverse steps goes for Decryption. Presently, working on to test this design against Side Channel attacks and would publish the results here.
Minor Project- AES Implementation in VerilogHardik Manocha
This presentation described about the Minor project I worked on for partial fulfillment of Bachelors Degree in G B Pant Engineering College. Presentation consisted of Advanced Encryption Standard (AES) and its implementation in Verilog. Different steps of the algorithm are presented.
This presentation consists of the Seminar, provided by me in the partial fulfillment of my Bachelors Degree in G B Pant Engineering College. Seminar included information about Encryption, Decryption, Cryptosystems and Authenticity in crytosystem.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...Amil Baba Dawood bangali
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Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
COLLEGE BUS MANAGEMENT SYSTEM PROJECT REPORT.pdfKamal Acharya
The College Bus Management system is completely developed by Visual Basic .NET Version. The application is connect with most secured database language MS SQL Server. The application is develop by using best combination of front-end and back-end languages. The application is totally design like flat user interface. This flat user interface is more attractive user interface in 2017. The application is gives more important to the system functionality. The application is to manage the student’s details, driver’s details, bus details, bus route details, bus fees details and more. The application has only one unit for admin. The admin can manage the entire application. The admin can login into the application by using username and password of the admin. The application is develop for big and small colleges. It is more user friendly for non-computer person. Even they can easily learn how to manage the application within hours. The application is more secure by the admin. The system will give an effective output for the VB.Net and SQL Server given as input to the system. The compiled java program given as input to the system, after scanning the program will generate different reports. The application generates the report for users. The admin can view and download the report of the data. The application deliver the excel format reports. Because, excel formatted reports is very easy to understand the income and expense of the college bus. This application is mainly develop for windows operating system users. In 2017, 73% of people enterprises are using windows operating system. So the application will easily install for all the windows operating system users. The application-developed size is very low. The application consumes very low space in disk. Therefore, the user can allocate very minimum local disk space for this application.
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
1. VLSI DESIGN CONFERENCE 2016
Domain- Analog/Digital Design
Challenge D3- Efficient Accelerator for Authenticated Encryption
Title: HarSam
Authors: Samnit Dua and Hardik Manocha
Passcode: 26X-C4E3D5E4H7
Confirmation No: 26
Introduction:
Our Team has selected one of the CAESAR Candidate’s paper to be implemented in the Design Contest
for VLSI Design Conference 2016, named TIAOXIN-346. As stated in the paper
(http://competitions.cr.yp.to/round1/tiaoxinv1.pdf ), implementation has been done on software
displaying Speed analysis for the design. No Hardware implementation has been listed in the paper.
Our Team, thus decided to design the Hardware for TIAOXIN-346, emphasizing on the FPGA
implementation using VerilogHDL and try to achieve the same speed as stated in the paper, on the
FPGA. Further, our team worked on the memory feature of the design as well.
Complete analysis of our design is listed on the pages to come with comparison to the analysis listed in
the paper.
We have worked on the 256 number of bits of the Text that has to be encrypted and decrypted.
2. Specification:
TIAOXIN-346 is a nonce based authenticated encryption scheme, which operates on 256 bits of the
Message and Associated data, along with 128 bits Key and Nonce (public message number)
For ENCRYPTION/AUTHENTICTION stage Tiaoxin- 346 (K; IV; M; AD) = (C; Tag)
Inputs-
Key, K (128 bits)
Nonce, IV (128 bits)
Plain Text, M (256 bits)
Associated Data, AD (256 bits)
Outputs-
Cipher Text, C (256 bits)
Authentication Tag, Tag (128 bits)
For DECRYPTION stage
Inputs-
Key, K (128 bits)
Nonce, IV (128 bits)
Cipher Text, M (256 bits)
Associated Data, AD (256 bits)
Authentication Tag, Tag (128 bits)
Outputs-
Plain Text, M (256 bits), if Authentication Tag generated matches with the input
Authentication Tag.
3. Notations:
Z0 - a constant word defined as Z0 =428a2f98d728ae227137449123ef65cd
Z1 - a constant word defined as Z1 =b5c0fbcfec4d3b2fe9b5dba58189dbbc
Ts - a state composed of s words. For instance, T3 has 3 words, T6 has 6 words. To index state words we
use the language C notation, hence Ts = (Ts[0]; Ts[1]; : : : ; Ts[s-1]), where Ts[i]; i = 0; : : : ; s-1 are words,
and Ts[0] is the first word.
Operations:
X ^ Y {bitwise addition (XOR) of the words X and Y
X&Y {bitwise conjunction (AND) of the words X and Y
AES(X; SK) {one keyed round of AES applied to the word X, where SK is the sub key, i.e.:
AES(X; SK) = Mix Columns (Shift Rows (Sub Bytes(X))) ^ SK
Sub Bytes; Shift Rows; Mix Columns are the same operations as in AES.
Thus, AES(X; SK) is the AES-NI instruction aesenc.
R (Ts; M) {a round transformation of a state with s words. The inputs of R are state Ts and word M,
while the output is a new state Tnew i.e.
R: Ts X M->Tnew s :
Tnew s [0] = AES (Ts [s - 1]; Ts [0]) ^M
Tnew s [1] = AES (Ts [0]; Z0)
Tnew s [2] = Ts [1]
: : :
Tnew s [s - 1] = Ts[s - 2]
States of TIAOXIN-346:
Both the Encryption and Decryption parts of TIAOXIN-346 operate upon three states- T3, T4 and
T6. T3 consists of 3 words; T4 consists of 4 words while T6 consists of 6 words.
Update Operation:
T3, T4 and T6 are updated using UPDATE function. UPDATE function uses the R(T;M) operation,
as defined above.
Update: T3 X T4 X T5 XM0 XM1 XM2 -> T3 X T4 X T6
T3new = R(T3;M0); T3 = T3new
4. T4 new = R(T4;M1); T4 = T4new
T6 new = R(T6;M2); T6 = T6new
T3 Update T4 Update T6 Update
Circled A stands for one AES round. The AES rounds applied to T3[2]; T4[3]; T6[5] are keyless, while the
AES rounds applied to T3[0]; T4[0]; T6[0] use Z0 as a sub key.
Definition of TIAOXIN-346
Tiaoxin – 346 processes the associated data AD and the message Min blocks where each block is
composed of 2 words (32 bytes, 256 bits)
The associated data AD is of 32 bytes. The length of the AD is encoded as 16-byte big endian word and
stored in AD Length, i.e. AD Length = |AD|.
The message M is of 32 bytes. The length of the M is encoded as 16-byte big endian word and stored in
M Length, i.e. M Length = |M|.
Tiaoxin - 346 is a stream cipher based design and as such it works in four phases: Initialization,
Processing associated data, Encryption, and Finalization. These phases are executed in the order
specified above.
INITIALIZATION:
In the initialization, the key K and the public message number (nonce) IV are loaded into the three states
T3; T4; T6 and the states go through 15 rounds.
T3 [0] = K; T3 [1] = K; T3 [2] = IV;
T4 [0] = K; T4 [1] = K; T4 [2] = IV; T4 [3] = Z0;
T6 [0] = K; T6 [1] = K; T6 [2] = IV; T6 [3] = Z1; T6 [4] = 0; T6 [5] = 0;
for i = 1 to 15
5. Update (T3; T4; T6; Z0; Z1; Z0);
end for
PROCESSING ASSOCIATED DATA
Assume the associated data is composed of two words, i.e. AD= AD0 || AD1. The Processing associated
data is defined as:
Update (T3; T4; T6; AD0; AD1; AD0 ^ AD1);
ENCRYPTION:
Assume the Message M is composed of two words, i.e. M= M0 || M1. In the encryption, a block M is
processed in one round, and a block of cipher text C = C0 || C1 (concatenation) is output. The Processing
associated data is defined as:
Update (T3; T4; T6; M0; M1; M0 ^ M1);
C0=T3 [0] ^ T3 [2] ^ T4 [1] ^ (T6 [3] & T4 [3]);
C1= T6 [0] ^ T4 [2] ^ T3 [1] ^ (T6 [5] & T3 [2]);
TAG PRODUCTION:
After all message blocks have been processed, the words holding the lengths of the associated data and
message are processed, then the states go through 20 more rounds, and the tag Tag is produced as an
XOR of all words of all states. This final phase is defined as:
Update (T3; T4; T6; AD Length; M Length; AD Length ^ M Length);
for i = 1 to 20
Update (T3; T4; T6; Z1; Z0; Z1);
end for
Tag= T3 [0] ^ T3 [1] ^ T3 [2] ^ T4 [0] ^ T4 [1] ^ T4 [2] ^ T4 [3] ^ T6 [0] ^
T6 [1] ^ T6 [2] ^ T6 [3] ^ T6 [4] ^ T6 [5];
6. DECRYPTION and VERIFICATION:
In the decryption-verification process, the order of the phases is the same: Initialization, Processing
associated data, Decryption, and Finalization. Initialization, Processing associated data and Finalization
are the same as during the encryption. Decryption is defined as:
Update (T3; T4; T6; 0; 0; 0);
M0= C0 ^ T3 [0] ^ T3 [2] ^ T4 [1] ^ (T6 [3] & T4 [3]);
M1= C ^ T6 [0] ^ T4 [2] ^ T3 [1] ^ (T6 [5] & T3 [2]) ^ M0;
T3 [0] = T3 [0] ^ M0;
T4 [0] = T4 [0] ^ M1;
T6 [0] = T6 [0] ^ M0 ^ M1;
VERILOG IMPLEMENTATION:
The VerilogHDL is an IEEE standard hardware description language. It is widely used in the design of
digital integrated circuits. Basically Verilog is verification through simulation, for timing analysis, for test
analysis and for logic synthesis. Verilog HDL allows designers to design at various levels of abstraction
like register transfer level, gate level and switch level. Verilog is used as an input for synthesis programs
which will generate a gate-level description for the circuit. Xilinx ISE 13.2 is a software tool developed by
Xilinx for synthesis and analysis of HDL designs.
VerilogHDL code is written in Xilinx ISE 13.2.
SIMULATION:
Our VerilogHDL code is simulated using ISIM available with Xilinx 13.2.
Test Vectors/Data for ENCRYPTION:
Inputs
Key, K = 91cc70a38f1cf31c3a3a39c748e8ee3a
7. Nonce, IV = b7ddefbdfad7df7b7dbee3e5f5f5fbe6
Message, M= b7ddf2398e1471e39e6387474738e91d1dc74fbdfad7df7b7dbee3e5f5f5fbe6
Associate Data, AD= 91cc70a38f1cf31c3a3a39c748edbeef7defd6befbdbedf71f2fafafdf30ee3a
Outputs
C= d4a1b9fb02fa511cdf7f8cfbb90e22438702502bada2b70436ca6fc14c5d6224
Tag= bf979c14211c4930064abc4f50c2d0d0
Simulation Result for ENCRYPTION:
Test Vectors/Data for DECRYPTION:
Inputs
Key, K = 91cc70a38f1cf31c3a3a39c748e8ee3a
Nonce, IV = b7ddefbdfad7df7b7dbee3e5f5f5fbe6
Associate Data, AD= 91cc70a38f1cf31c3a3a39c748edbeef7defd6befbdbedf71f2fafafdf30ee3a
12. Device and the family used for our design implementation is SPARTAN 3E (xc3s500e-5vq100).
SUMMARY- ENCRYPTION
This summary shows Synthesize report for Enhanced Pentium M architecture.
Summary for Haswell architecture
13. SUMMARY- DECRYPTION
Detailed Synthesize Report for Decryption is available in the main folder, named “reports ->
synthesize reports -> detailed_synthesize_report_dec.txt”.
FPGA IMPLEMENTATION:
Code written by our team is altered in order to test our design over FPGA.
Encryption code changes:
1) Inputs K, IV, AD, M are created constant in the code.
2) Rest of the Inputs is similar.
3) Inputs K,IV, AD, M are created as parameters with the values listed in this paper.
4) Outputs defined for FPGA code are only 8 bits. All these bits are used to display
Cipher Data and Tag on LEDs.
5) Only certain bits of C and Tag are displayed on LEDs, in order to have maximum
similarity with the actual code.
14. SUMMARY- ENCRYPTION for FPGA
Detailed Synthesize report is available in main folder as “synthesize
report_fpga_implementation -> detailed_synthesize_report_enc_fpga.txt”.
Decryption Code changes:
1) Only inputs are clk and rst.
2) Inputs K, IV, C, Tag, and AD are created as parameters with the values generated
from Encryption module.
3) Output is only single LED, which describes the match between Input Tag and
generated Tag, and thus describes what would be the output.
SUMMARY- DECRYPTION for FPGA
15. COMPARISON:
This section would describe the comparison among our design and the one described in the
paper (http://competitions.cr.yp.to/round1/tiaoxinv1.pdf ). This comparison is done for ENCRYPTION,
as the performance listed in the TIAOXIN-346 is only for ENCRYPTION.
Features Our Design TIAOXIN-346
Software Yes Yes
Hardware (SPARTAN 3E) Yes No
SPEED (Enhanced Pentium M
micro architecture)
(256 bits Data)
7.562ns N A
SPEED (Haswell micro
architecture)
(256 bits Data)
7.782ns N A
SPEED (Sandy Bridge micro
architecture)
(256 bits Data)
N A 1.45ns
16. CONCLUSION:
As the problem statement for the Design Contest demanded, that teams participating should
implement Hardware for a CAESAR Entry, therefore, Our Team was able to achieve Hardware
Implementation for TIAOXIN-346. In the paper, entitled “TIAOXIN-346”, no Hardware
Implementation has been listed. Only Software Implementation has been described.
Although, in our design, we were not able to achieve similar SPEED performance as compared
to TIAOXIN-346. Our design is 5 times slower than TIAOXIN-346 but we have successfully
verified our design over FPGA.
Our Team is still working on to bring the listed SPEED Features in TIAOXIN-346, to be available
with our design, so that we add one more feature of HARDWARE IMPLEMENATION to TIAOXIN-
346. For this, our team has built another design which makes use of “Function Calls and LOOPS
Structures” instead of “multiple times Module Instantiations”. We have successfully
SIMULATED this design, but due to lack of system resources, we were not able to determine the
SPEED features of that design as Synthesize Process is taking whole lot of time and still not
completing and thereby that design is not Hardware Implemented as well. We are pretty sure
that Design with Functions and LOOP Structure would match the SPEED features of TIAOXIN-
346, as Functions and LOOP Structures take only 2-3 clock ticks rather than complete clock
cycles.