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Nice, simple, passionate, smart worker, pursuing B.Tech in ECE, from G B PANT GOVT ENGG COLLEGE, New DELHI. My areas of INTEREST surround VLSI( both FRONT-END AND BACK-END), DIGITAL IMAGE PROCESSING, DIGITAL SIGNAL PROCESSING (MATLAB), ROBOTICS and Embedded Systems. Currently learning IMAGE and Signal PROCESSING in order to integrate these domains with Verilog to implement on FPGA. Also started learning VERIFICATION by SYSTEM VERILOG + UVM. My works: http://www.slideshare.net/HardikManocha1/vlsi-design-conference-2016-kolkata-authenticated-encryption-decryption