The document outlines the Digital System Design learning module focused on Hardware Description Languages (HDL), with prerequisites including Boolean algebra and function minimization techniques. It covers various HDLs such as Verilog and VHDL, their development history, versions, and essential EDA tools for circuit design and simulation. Additionally, it includes practical steps for HDL design flow, coding basics, and examples for academic exercises and quizzes.

1. Digital System Design
Learning Module 2.1: Introduction to HDL

2. What I Expect as Pre- Requisite
• Boolean Algebra
• Truth Table& Boolean Functions
• POS & SOP
• Function Minimization & K Map
Method
Section 2.3 and 2.4 of Text Book, Only 4 Pages 40-45
Section 2.5 Example 2.1 – 2.3
Section 3.2-3.3
Section2.6 Example 2.4 – 2.5
Example 3.1-3.6

3. Quiz 1- CLO2
• Analysis of Boolean functions and truth tables to change their
implementation methods and minimizations
• Date : ??

4. Need of Electronic Design Automation
Scale the complexity using pen and paper
 Can you try to Draw the Diagram of 8 bit Full Adder which is used in 8051?
- How About Trying for 16 bit addition circuit?

5. A Sample Diagram of 4 Bit ALU

6. Examples from Sequential Circuits

7. Electronic Design Automation
How can one draw, analyze the
schematic of a system having 1
Million transistors?
Electronic Design Automation – Computer based tools / software / simulators to
describe, analyze, test electronic circuits for chip developments

8. Difference between HDL and Software
• Writing a task in C to execute in a controller
Vs
• Writing a Verilog code
• C Executes statement HDL executes concurrent behavior of hardware
• C compiler generates machine language that fits some hardware whereas
HDL generates hardware its self
• Embedded code ≠ embedded hardware (a Kind of)

9. Versions of HDL
• Verilog
• Developed by Gateway Design System Corporation (Now Cadence) 1985
• Initially a proprietary version of tool
• Open Verilog International (OVI) 1990
• C like approach; engineers like it
• VHDL
• Developed by State Agencies later adopted as IEEE standard
• Its different in approach ; more like Ada ( integrated software development )

10. Versions of Verilog
• Verilog – 95
• IEEE Standard 1364-1995, commonly referred to as Verilog-95
• Verilog – 2001
• An extension / improvement of previous version
• These extensions became IEEE Standard 1364-2001 known as Verilog-2001
• Verilog-2001 is a significant upgrade from Verilog-95
• It adds explicit support for (2's complement) signed nets and variables. Previously, code authors
had to perform signed operations using awkward bit-level manipulations
• Verilog-2001 is the version of Verilog supported by the majority of commercial EDA software
packages.
• Verilog – 2005
• Verilog 2005 (IEEE Standard 1364-2005)
• A separate part of the Verilog standard, Verilog-AMS, attempts to integrate analog and mixed
signal modeling with traditional Verilog.
• System Verilog
• A Superset of Verilog-2005, with many new features and capabilities to aid design verification
and design modeling. As of 2009, the SystemVerilog and Verilog language standards were
merged into SystemVerilog 2009 (IEEE Standard 1800-2009). The current version is IEEE standard
1800-2017

11. EDA tools for HDL
• Icarus Verilog: fully open-source compiler that includes both a Verilog
synthesizer and simulator.
• GHDL: This is a fully open-source VHDL compiler and simulator
• Vivado: This is a software tool from Xilinx which can be used to
design, simulate and build FPGAs.
• ModelSim: This is a commercially produced simulation tool from
Siemens.
• HDL Coder For Matlab
• Xcelium (Cadence)

12. Tools for verilog
"designflow"
1-think about a design you want to implement,
e.g. an adder
2- implement the design in VHDL/Verilog
3- implement a testbench in VHDL/Verilog
4- use the testbench for simulating your design
(from step 2)
5- if this works and the simulation is successful,
try to synthesize the design
6- do all the other stuff, like map, place and route
7- build a .bit file
8- use your JTAG to program your FPGA
step 1) the most important is Libre /openOffice Calc, paper and a
pencil and if you have large FSMs maybe Qfsm
step 2) you need a good editor, grab one you like and everything
is fine. there are a few specialized for VHDL, the best is sigasi (you
have to google this one, spam prevention). For this task you can
already use one of the big vendors IDEs,
step 3) -> step 2)
step 4) here are a few possibilities: Xilinx ISim, (Altera) Modelsim,
(Lattice) Aldec, ghdl in combination with GTKWave. I think there
are more Simulators, but this should be enough for beginning. All
these tools are Simulators only, although they bring a full IDE
(except of ghdl).
step 5) do yourself a favour and use the tool provided by the
manufacturer of your FPGA. if you are experienced enough you
could try Icarus Verilog, too.
step 6 and 7) no other chance than using the vendortools
step 8) so many tools do that, even the tools provided by the
FPGA vendors.

13. Hardware Descriptive Language (HDL)-
section 3.9
• A textual representation of a digital circuits.
C= A+B
Gate Level- Model
Look up table – Data Flow Model Behavioral - Model

14. HDL Design Levels
• Design Entry – Writing a code using any of three models described
earlier
• Syntax Verification – A Kind of Compiler
• Logic Simulation – Test the Circuit
• Logic Synthesis – Code to component Conversion (EDA internal data)
• Timing Verification

15. Let’s Go for First Verilog Program
Keywords- case sensitive, pre-defined
• module
• Endmodule
• Ports & Connection
• output
• input
• wire
• Primitives ~ Library functions
• and
• not
• or etc.

16. Delays in Verilog
• Every Physical Circuit Observe the Delays so required to be described
in code
`timescale 1ns/100ps
Unit of Time Precision of time scale
Time Unit can be marked in small boxes
Precision
1ns 2ns 3ns

17. Introducing the propagation delay

18. Timing Effects
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
0
0 0
1

19. How to Test
• What if code is mistakenly written as ??
and G1(w1, A, B)
not G2( E, c)
nor G3( D, w1, e)
- Will there be any syntax error
- Test by giving input and verify truth table
- This leads to develop a test bench

20. First Test Bench
Block of statements- a kind of group of statements forming a task
Start Simulation in time window by setting t=0
Stop simulation after 200 unit of time

22. Describing circuit from Boolean Function
Write the Boolean Expression for D and E
Use symbols to represent logical Operators
Sample Function
Continuous Assignment Operation ?
Contrary to procedural statement.

23. Primitives ~ objects/function/classes
• Verilog HDL has two types of primitives
• System Defined Primitive e.g and, or, not etc
• Just use these words within syntax regulations, system knows how to translate
• User Defined Primitives (UDPs)
• User can define its own primitives as objects/ functions / classes are defined in other
languages
• It helps to model available hardware/ ICs based their truth table
• Method adopted is look up table (LUT)
• Developed using keywords “primitive” “endprimitive”
• Let’s see an example

25. How to Use UDP in module

26. Practice Tasks ~ Home Work
• End Problem 3.33-3.36
• End Problem 3.38
A Quiz will be conducted in regarding above suggested End Problems