1. Following are the steps for writing and simulating VHDL code in Xilinx ISE environment.
1) Create New project from File Menu.
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2. 2) Give the file name
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4. 4) Press ‘Next’ two times in the follow-up windows and then ‘Finish’ at last.
5) Select New Source by clicking on project in sources window as shown below:
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5. 6) Select VHDL Module and name the file. Then click Next
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6. 7) Give port declarations as we do in entity. Then click Next. And then Finish.
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7. 8) VHDL Code is presented on the screen. Now we just have to write the code in architecture.
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9. 9) Select New Source by clicking on project in sources and then select Test Bench Waveform and name the file. Then Click Next two times
and then Finish.
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10. 10) A new window appears as shown below. For combinational circuits select combinatorial clock.
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11. 11) Set the input waveforms by clicking on the waveform at different time intervals.
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13. 13) Under Processes window simulate the file.
14) The output simulations is observed at last.
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