Verilog hdl


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Verilog hdl

  1. 1. What is HDL?hardware description language describes the hardware of digital systems in textual form.One can design any hardware at any levelSimulation of designs before fabricationWith the advent of VLSI, it is not possible to verify a complex design with millions of gates on a breadboard, HDLs came into existence to verify the functionality of these circuits.
  2. 2. Most Commonly used HDLsVerilog Verilog HDL is commonly used in the US industry. Major digital design companies in Pakistan use Verilog HDL as their primary choice. most commonly used in the design, verification, and implementation of digital logic chipsVHDL (VHSIC (Very High Speed Integrated Circuits) hardware description language) VHDL is more popular in Europe. commonly used as a design-entry language for field- programmable gate arrays. Field-Programmable Gate Array is a type of logic chip that can be programmed.
  3. 3. Verilog SimulatorThere are many logic simulators used for VerilogHDL. Most common are:XilinxVeriwellModel SimFor Beginners Veriwell is good choice and is very userfriendly.Xilinx and ModelSim are widely used.
  4. 4. Levels of AbstractionThere are four different levels of abstraction in verilog:Behavioral /AlgorithmicData flowGate levelSwitch level.We will cover Gate level, Data flow and BehavioralLevel modeling
  5. 5. Getting started…A verilog program for a particular application consistsof two blocksDesign Block (Module)Testing Block (Stimulus)
  6. 6. Design BlockDesign Methodologies:Two types of design methodologies Top Down Design Bottom Up Design inputs Design outputs Block
  7. 7. In Top Down design methodology, we define the top levelblock and identify the sub-blocks necessary to build the toplevel block. We further divide the sub-block until we cometo the leaf cells, which are the cells which cannot bedivided.
  8. 8. In a Bottom Up design methodology, we first identify thebuilding blocks , we build bigger blocks using these buildingblocks. These cells are then used for high level block untilwe build the top level block in the design
  9. 9. EXAMPLEFOUR BIT ADDER (Ripple carry adder)
  10. 10. Module RepresentationVerilog provides the concept of moduleA module is a Basic Building block in Verilog Basic Building block in Verilog It can be a single element or collection of lower design blocksA verilog code starts with moduleSyntax:module <module-name>(inputs, outputs);//Define inputs and outputs Every verilog program starts with the ………… keyword module and ends with the keyword ………… endmodule ………… endmodule
  11. 11. Input Output DefinitionOnce the module is defined at the start the inputs and outputs are to be defined explicitly. e.g.input a , b //means there are 2 inputs of one bit eachIf input or output is more than 1 bit i.e. two or more bits, then the definition will be: input [3:0] A, B; //4 bit inputs A3-A0 and B3-B0 output [3:0] C;
  12. 12. Levels of Abstraction
  13. 13. Gate Level ModelingIn gate level modeling a circuit can be defined by use oflogic gates.These gates predefined in verilog library.The basic gates and their syntax is as follows: and gate_name(output, inputs); or gate_name(output, inputs); not gate_name (output, inputs); xor gate_name(output, inputs); nor gate_name(output, inputs); nand gate_name(output, inputs); xnor gate_name(output, inputs);
  14. 14. Data Flow ModelingContinuous assignment statement is used.Keyword assign is used followed by =Most common operator types are Operator Types Operator Symbol Operation Number of performed Operands Arithmetic * Multiply Two / Divide Two + Add Two - Subract two Bitwise Logical ~ Bitwise negation One & Bitwise and Two | Bitwise or Two ^ Bitwise xor Two ^~ or ~^ Bitwise xnor two Shift >> Shift right Two << Shift left Two Concatenation {} Concatenation Any number Conditional ?: Conditional three
  15. 15. Examples1. assign x = a + b;2. assign y = ~ x ; // y=x’3. assign y = a & b; // y= ab4. assign w = a ^ b; //y= a b5. assign y = x >> 1; //shift right x by 16. assign y = {b, c}; //concatenate b with c e.g. b = 3’b101, c =3’b 111 y = 101111assign {cout , sum} = a + b + cin; //concatenate sum and cout7. assign y = s ? b : a // 2×1 multiplexer when s = 1 , y = b when s = 0 , y = a assign y = s1 ? ( s0 ? d : c ) : ( s0 ? b : a ); // 4×1 MUX
  16. 16. Module InstantiationModule instantiation is a process of connecting one module to another.For example in a test bench or stimulus the top level design has to be instantiated
  17. 17. Testing Block (Stimulus)In order to test your circuit a test bench code is to be written which is commonly called Stimulus.The design block has to be instantiated/calledIt displays the output of the design based on the inputs.
  18. 18. Example 2- Input AND GateThe Design and Stimulus blocks will be asfollows:
  19. 19. Design Block 1)Gate Level Modeling module practice (y, a, b); //module definition input a, b; // inputs(by default it takes 1 bit input output y; // one bit output and gate_1(y, a, b) ; endmodule
  20. 20. 2) Data Flow Modeling module practice (y, a, b); //module definition input a, b; // by default it takes 1 bit input output y; // one bit output assign y = a & b; endmodule
  21. 21. Stimulus Blockmodule stimulus; #5 $stop; // stop the simulationreg a, b; #5 $finish; // terminate the simulationwire y; end//Instantiate the practice module initialpractice p0(y, a, b); begininitial $display("|%b| and |%b| = ", a, b);begin $monitor ($time, "|%b |" , y); a=0; b=0; end#5 a=1; b=1; //initial #5 a=0; b=1; //$vw_dumpvars; // display the simulation in the form of timing diagram#5 a=1; b=0; endmodule#5 a=1; b=1;
  22. 22. Example #2:4 bit ripple carry adder
  23. 23. Full Adder
  24. 24. Bottom Level module//Define a full adder //full adder logic configurationmodule fulladder (sum, c_out, a, b, xor ( s1,a,b); c_in); and (c1,a,b);//I/O Port declaration xor (sum,s1,c_in); and (c2,s1,c_in);output sum, c_out;input a, b, c_in; or (c_out,c2,c1);//Internal nets endmodulewire s1, c1, c2;
  25. 25. TOP LEVEL MODULE //Define a 4 bit 4 addermodule toplevel_fa(sum,c_out,a,b,c_in); //I/O port declarationoutput [3:0] sum;output c_out;input [3:0] a, b;input c_in; //internal netswire c1,c2,c3; //Instantiate four 1-bit full adderfulladder fa0(sum[0],c1,a[0],b[0],c_in);fulladder fa1(sum[1],c2,a[1],b[1],c1);fulladder fa2(sum[2],c3,a[2],b[2],c2);fulladder fa3(sum[3],c_out,a[3],b[3],c3);endmodule
  26. 26. Test Bench (stimulus) //define stimulus toplevel modulemodule stimulus;reg [3:0]a,b; //set up variablesreg c_in;wire [3:0] sum;wire c_out;//Instantiate the toplevelmodule(ripple carry adder) call it tltoplevel_fa tl(sum,c_out,a,b,c_in);
  27. 27. //stimulate inputsinitialbegin a = 4b0000; b = 4b0010; c_in = 1b0; #1 $display (“ a = %b, b = %b, c_in = %b, sum = %b", a, b, c_in, sum); a = 4d1; b = 4d2; c_in = 1b1; #2$display (“ a = %b, b = %b, c_in = %b, sum = %b", a, b, c_in, sum); a = 4hf; b = 4ha; c_in = 1b0; #2$display (“ a = %b, b = %b, c_in = %b, sum = %b", a, b, c_in,sum);endendmodule
  28. 28. Verilog KeywordsVerilog uses about 100 predefined keywords. All the keywords are represented in colored font (either green, blue or red). if it is not shown in a colored font it means there must be some typing error.All the verilog statements are terminated with a semicolon(;) except for the statements (keywords) like initial, begin, always, if, for, while etc…Verilog is case sensitive i.e. the keywords are written in lower case.
  29. 29. Continued…… Most common keywords are module, endmodule input, output wire, reg $display, $print, $monitor always, for, while, if initial, begin and, or, not, xor, xnor, nard, nor posedge , negedge, clock, reset, case $vw_dumpvars, $stop, $finish Single line comment is given by // ( two consecutive slash) and multi-line comment is given by /*……… */ for e.g // This is the first session of verilog /* this is the first session of verilog*/