Altera Corporation, profile picture
Uploaded byAltera Corporation
2,473 views

Nios II Embedded Processor: Embedded World 2010

The document discusses the Nios II processor from Altera. It comes in three versions - FAST optimized for speed, STANDARD with balanced speed and size, and ECONOMY optimized for size. Software code is binary compatible across versions. The processor is configurable with features like caches and custom instructions. It integrates easily into systems using the SOPC Builder tool and works with development tools and operating systems.

Embed presentation

The Nios II Processor Learning Zone @ Embedded World 2010 © 2010 Altera Corporation—Public
Nios II Versions 32-bit RISC Nios II Processor comes in three ISA compatible versions: − FAST: Optimized for Speed − STANDARD: Balanced for Speed & Size − ECONOMY: Optimized for Size Software code is binary compatible across all versions - No software changes required © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Nios II Processor Features Configurable: − Core features – caches, interrupts, custom instructions, etc. − User Defined Peripheral Set Automated processor configuration and system integration Powerful software tools − Eclipse IDE, C/C++ Development Tools, Trace Debug, Flash Programmer, etc. Third party support for RTOS, middleware and debug tools © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Nios II Processor Configuration Nios II Processor Core reset Instruction General Master Instruction and Program Instruction and clock Purpose Port Data Trace Controller Data Trace Registers Instruction JTAG interface Hardware- & Cache to Software Assisted Address Debugger Debug Module Generation Status & Control Registers Tightly Tightly High Speed Trace Trace Coupled Coupled Connection Trace port Trace port I-Memory Memory Memory I-Memory to Trace Pod Breakpoints Breakpoints Exception Tightly Tightly HW Controller MMU HW Coupled Coupled D-Memory D-Memory Interrupt MPU irq[31..0] Controller Data Master Port Data Custom Cache Custom Instruction Arithmetic I/O Signals Logic Logic Unit © 2010 Altera Corporation—Public = Configurable = Optional & Configurable ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. = Fixed = Debug Options
Nios II Processor Benchmark Data Cyclone® III / IV FPGAs Stratix® IV FPGAs Clock Clock Speed DMIPS LEs Speed DMIPS ALUTs (MHz) (MHz) Nios II /f 175 195 1,800 290 340 1,020 Nios II /s 145 90 1,300 250 150 850 Nios II /e 215 30 650 340 48 520 Note: Cyclone devices range from 5K LEs to >100KLEs © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
3 Ways to Increase Performance Custom Hardware Multi-Processor Instructions Accelerators System FPGA FPGA FPGA Nios II Nios Nios II Nios Nios II Nios External External Nios II PCIe Nios PCIe Custom Custom Hardware Hardware CPU or CPU or Instructions Instructions Accelerator Accelerator DSP DSP Nios II Nios Accelerate CPU Add external Add more processing co-processing processors performance with hardware to (internal &/or application- accelerate data external) to increase specific hardware functions processing power © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Accelerating Software in FPGA Custom Add Custom instruction: CUST A,B,C Logic − Ideal for complex bit/word operations A + - Add hardware accelerator << C - Out >> − Processor & accelerator can run concurrently B & − More work per clock − Lower fMAX, power, cost Nios II Embedded Processor − Ideal for block operations Control 2,500 Nios II Iterations/Second DMA DMA Custom Accelerator Instruction 2,000 1,500 530 Times 27 Times Faster 1,000 Faster Arbiter Arbiter 500 0 Software Custom Accelerator Program Data Data Memory Memory Memory Only Instruction © 2010 Altera Corporation—Public * Accelerator running 64Kb CRC at 100 MHz ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Altera C2H – the SW Accelerator Solution Generates and integrates a custom hardware accelerator from an ANSI C function. C2H C2H CPU Accelerator Accelerator Arbiter Arbiter Arbiter Arbiter Program Data Data Memory Memory Memory © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Hardware Development Flow Hardware HW Simulation Configure & Integrate Hardware Configuration FPGA © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Creating Systems With SOPC Builder © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
SOPC Builder IP Cores Over 50 IP cores and components available Interface protocols − Ethernet, RapidIO®, PCI, SPI, UART, USB, etc. Processors − Nios II, Cortex M1, Coldfire V1, etc. Memories and memory controllers − DMA, flash controllers, SDRAM controllers Peripherals − Display, microcontroller peripherals, etc. Video and imaging processing − Alpha blender mixer, Deinterlacer, etc. Plus many more © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Embedded Development Flow Hardware Configure & Integrate Hardware System .ptf Configuration Information .sopc Software FPGA Compile & Debug © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Nios II Embedded Design Suite Integrated Software Nios II Software Development Build Tools Manage, Build, Debug Embedded Design Suite HAL API Peripheral Drivers GNU Tools and Runtime Debugger, Software Library © 2010 Altera Corporation—Public C/C++Compiler ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Nios II Operating System / Middleware Support LINUX embOS µCLinux ERIKA & RT-Druid Open Source Open Source www.niosforum.org www.niosforum.org © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Partner Software Development Tools Optimizing C Compiler © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Other Processor Options ARM Cortex-M1 Freescale ColdFire V1 Evatronix X86 Octera PPC 405 Leon 3 Many legacy cores – 8051, 6502, etc © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Why your next embedded project might use a Nios II processor… If standard microcontrollers I/O I/O I/O or processors don’t offer enough… FPGA − Functionality CUSTOM LOGIC − System Integration Nios II DSP I/O − Power/performance ratio − Product flexibility − Obsolescence protection …then the Nios II processor is for you! Innovate with Nios II & FPGA! © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Thank You www.altera.com © 2010 Altera Corporation—Public
Back-up © 2010 Altera Corporation—Public
First Step in System Design © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
What is SOPC Builder? IP delivery and system generation tool: − GUI based − IP configuration − System configuration − Automated IP integration © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Traditional System Design Processor Ethernet (Bus Master) Interrupt (Bus Master) 32-Bit Controller 32-Bit Address Address Address High Data Data Decoder High Arbiter Engineering Engineering Overhead! Overhead! Width-Match Width-Match Width-Match Width-Match Width-Match UART Memory Timer PCI DDR2 8-Bit 32-Bit 16-Bit 64-Bit 64-Bit Clock 1 Clock 2 Clock 1 © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
SOPC Builder Integration Processor Ethernet (Bus Master) (Bus Master) 32-Bit 32-Bit Integration is Integration is Fast, Easy and Fast, Easy and Error Free! Error Free! Automatically Generated System Interconnect Fabric Address Address Interrupt Interrupt Burst Burst Wait-state Wait-state Multi-clock Multi-clock Decoder Decoder Controller Controller Transfers Transfers Generation Generation Domain Domain Arbiter Arbiter Arbiter Arbiter Arbiter Arbiter Arbiter Arbiter Arbiter Arbiter Width-Match Width-Match Width-Match Width-Match Width-Match Width-Match Width-Match Width-Match Width-Match Width-Match UART Memory Timer PCI DDR2 8-Bit 32-Bit 16-Bit 64-Bit 64-Bit Clock 1 Clock 2 Clock 1 © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
SOPC Builder © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Component Selection Pool of “SOPC Builder Ready” Pool of “SOPC Builder Ready” Components Components −− Communications Communications −− DSP DSP −− Bus Interfaces Bus Interfaces −− Bridges Bridges −− Memory Controllers Memory Controllers Nios & Nios II®®Processors Nios & Nios II Processors Over 60 Third Party IP Support Third Party IP Support Cores Available Today © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Component Configuration Select Component from Select Component from SOPC library SOPC library Wizard based configuration Wizard based configuration for individual component for individual component properties properties Component added to list of Component added to list of active components active components Add, remove or modify Add, remove or modify component properties at component properties at any time any time © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
SOPC Builder Nios II Processor Options Select best fit processor core Configure caches Configure debug option Integrate custom instructions Edit and Regenerate at Any Time! © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
System Configuration Connection Patch Panel Connection Patch Panel −− One click to connect One click to connect component component Each master can connect Each master can connect to one or many slaves to one or many slaves Configure connections to Configure connections to optimize throughput optimize throughput Set Arbitration priorities Set Arbitration priorities © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
System Component Configuration Configure how each Component Configure how each Component fits into the System fits into the System −− Interrupt Request (IRQ) Level Interrupt Request (IRQ) Level −− Base Address Base Address −− Clock Source Clock Source Auto-assign option Auto-assign option Error checking Error checking Edit values at any time Edit values at any time Lock critical settings Lock critical settings Click on ‘Generate’ button Click on ‘Generate’ button to create system © 2010 Altera Corporation—Public to create system ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Developing Software for the Nios II Processor © 2010 Altera Corporation—Public
Nios II IDE Debug Perspective Re-start Debugger Re-Run Program Basic Debug • Run Controls • Stack View • Active Debug Sessions Double-click to add breakpoints Memory View • Variables • Registers • Signals © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Processor - FPGA Interfaces = master = slave Processor FPGA or DSP Avalon GPIO, Switch Fabric RS232, I/O etc. I/F IP IP CPU / DSP CPU Co-Proc Specific IP IP I/F SRAM SDRAM etc. Memory IP IP Automatically Generated © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Processor - FPGA Interfaces = master = slave Processor FPGA or DSP Avalon Switch Fabric IP CPU / DSP Industry Interface Standard PCIe PCI e Hard IP I/F High IP Performance IP Automatically Generated © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Processor - FPGA Interfaces = master = slave Processor FPGA Avalon Switch Fabric IP Industry Interface Standard PCIe CPU PCIe Hard IP I/F High IP Performance IP Automatically Generated © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Co-processing Solution Example USB PCIe I/O Hub Processor DSP Graphics (Intel Atom) (Optional) Hard Disk PCIe RapidIO DVI Isolation and RJ-45 Industrial Motor Control Ethernet Power Stage Isolation PWM and RJ-45 Sensor Camera ADC/DAC OPTO I/O © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Nios II Embedded Evaluation Kit, Cyclone III Edition Embedded software evaluation platform Development board based on Cyclone III FPGA with touch-screen LCD Software applications and tutorials − Web server − Picture viewer − Graphics acceleration − and more Development software: Nios II EDS, SOPC Builder, Quartus II Web Edition Low Cost: $449 © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
NEW Altera Embedded Systems Development Kit, Cyclone III Edition Complete platform for proto-typing embedded systems (3C120) List price: $1995 IP Licensing purchased separately Embedded IP Suite (IPS-EMBEDDED) $995 − Nios® II processor, DDR/DDR2 Memory controllers, Triple Speed Ethernet and software stack © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

More Related Content

PDF
GIGABYTE GA-K8NXP-SLI AMD Socket 939 Processor Motherboard
bybettlebrox
 
PDF
ADVANCED DVB-C,DVB-S STB DEMOD
byaniruddh Tyagi
 
PDF
Fortigate 200 b-quickstart
byJuan Carlos Escamilla
 
PDF
Dektec dtu-215
byTELE-audiovision eng
 
PDF
Mini Robot Fighter
byminirobot
 
PDF
Benefits of Using FPGAs for Embedded Processing: Embedded World 2010
byAltera Corporation
 
PDF
Raise your Uptime - How to monitor heterogeneous server environments with Linux
byWerner Fischer
 
PDF
2011 intelligent operator_panels
byadvantech2012
 
GIGABYTE GA-K8NXP-SLI AMD Socket 939 Processor Motherboard
bybettlebrox
 
ADVANCED DVB-C,DVB-S STB DEMOD
byaniruddh Tyagi
 
Fortigate 200 b-quickstart
byJuan Carlos Escamilla
 
Dektec dtu-215
byTELE-audiovision eng
 
Mini Robot Fighter
byminirobot
 
Benefits of Using FPGAs for Embedded Processing: Embedded World 2010
byAltera Corporation
 
Raise your Uptime - How to monitor heterogeneous server environments with Linux
byWerner Fischer
 
2011 intelligent operator_panels
byadvantech2012
 

Similar to Nios II Embedded Processor: Embedded World 2010

PDF
PA Develops an LTE PHY for Catapult
bygrahambell
 
PPTX
EASA Part-66 Module 5.6 : Basic Computer Structure
bysoulstalker
 
PPT
Tms320F2812 Digital I/0
byPantech ProLabs India Pvt Ltd
 
PPT
Architecture of tms320 f2812
byPantech ProLabs India Pvt Ltd
 
PPTX
Arm 7 nxp
byPantech ProLabs India Pvt Ltd
 
PDF
Lect.10.arm soc.4 neon
bysean chen
 
PDF
Adv. FPGA Motor Control--EBV & Univ. of Koln: Embedded World 2010
byAltera Corporation
 
PPT
Dcs presentation 13005437501565-phpapp01
byinfoasim2
 
PDF
8051 tutorial
bymariomarion102030
 
PDF
Mpc5121 econfs
byDino, llc
 
PDF
DFX Architecture for High-performance Multi-core Microprocessors
byIshwar Parulkar
 
PDF
Slyy027
byAshutosh Bedarkar
 
PDF
Thesis Donato Slides EN
byMarco Santambrogio
 
PPT
Modeling System Behaviors: A Better Paradigm on Prototyping
byDVClub
 
PDF
CWCAS X-ISCKER Poster
byJose Pinilla
 
PDF
Sears Point Racetrack
byDino, llc
 
PDF
Drra brief
byBengt Edlund
 
PDF
Drra brief
byBengt Edlund
 
PDF
Session 40 Frederik Jonsson
byTransportforum (VTI)
 
PDF
C:\Documents And Settings\Fredlin\Desktop\Ic Design\Synthesis200301
byguest77988fe
 
PA Develops an LTE PHY for Catapult
bygrahambell
 
EASA Part-66 Module 5.6 : Basic Computer Structure
bysoulstalker
 
Tms320F2812 Digital I/0
byPantech ProLabs India Pvt Ltd
 
Architecture of tms320 f2812
byPantech ProLabs India Pvt Ltd
 
Arm 7 nxp
byPantech ProLabs India Pvt Ltd
 
Lect.10.arm soc.4 neon
bysean chen
 
Adv. FPGA Motor Control--EBV & Univ. of Koln: Embedded World 2010
byAltera Corporation
 
Dcs presentation 13005437501565-phpapp01
byinfoasim2
 
8051 tutorial
bymariomarion102030
 
Mpc5121 econfs
byDino, llc
 
DFX Architecture for High-performance Multi-core Microprocessors
byIshwar Parulkar
 
Slyy027
byAshutosh Bedarkar
 
Thesis Donato Slides EN
byMarco Santambrogio
 
Modeling System Behaviors: A Better Paradigm on Prototyping
byDVClub
 
CWCAS X-ISCKER Poster
byJose Pinilla
 
Sears Point Racetrack
byDino, llc
 
Drra brief
byBengt Edlund
 
Drra brief
byBengt Edlund
 
Session 40 Frederik Jonsson
byTransportforum (VTI)
 
C:\Documents And Settings\Fredlin\Desktop\Ic Design\Synthesis200301
byguest77988fe
 

More from Altera Corporation

PDF
Creating Your Own PCI Express System Using FPGAs: Embedded World 2010
byAltera Corporation
 
PPTX
Overview of Nios II Embedded Processor
byAltera Corporation
 
PPT
Upgrade Your Broadcast System to PCIe Gen2
byAltera Corporation
 
PPT
Altera Cyclone IV FPGA Customer Presentation
byAltera Corporation
 
PDF
AMC & VPX Form Factor Boards With High Speed SERDES: Embedded World 2010
byAltera Corporation
 
PPT
Stratix V FPGA Intro Presentation
byAltera Corporation
 
PDF
IXXAT--Industrial Ethernet Challenges/Solutions: Embedded World 2010
byAltera Corporation
 
PPTX
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case Study
byAltera Corporation
 
PDF
Industrial Safety: Embedded World 2010
byAltera Corporation
 
PPTX
Altera’s Role In Accelerating the Internet of Things
byAltera Corporation
 
Creating Your Own PCI Express System Using FPGAs: Embedded World 2010
byAltera Corporation
 
Overview of Nios II Embedded Processor
byAltera Corporation
 
Upgrade Your Broadcast System to PCIe Gen2
byAltera Corporation
 
Altera Cyclone IV FPGA Customer Presentation
byAltera Corporation
 
AMC & VPX Form Factor Boards With High Speed SERDES: Embedded World 2010
byAltera Corporation
 
Stratix V FPGA Intro Presentation
byAltera Corporation
 
IXXAT--Industrial Ethernet Challenges/Solutions: Embedded World 2010
byAltera Corporation
 
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case Study
byAltera Corporation
 
Industrial Safety: Embedded World 2010
byAltera Corporation
 
Altera’s Role In Accelerating the Internet of Things
byAltera Corporation
 

Recently uploaded

PDF
How the EU Ecolabel's Record Growth Creates ESG Opportunities for CRE
byWastify AI
 
PDF
One String, Many Prompts: AI Code Generation
byGeoffrey Goetz
 
PPTX
Webinar: EVerest for Production: Accelerating EV Charger Development w/ Indus...
byDanBrown980551
 
PDF
Kubernetes Cloud Native Indonesia Meetup - January 2026
byPrasta Maha
 
PPTX
Apache Kafka 101 for Techies in IT dep.pptx
byamulyareddyk97
 
PPTX
API Gateway Architecture - Technical Report 2026
byPowersoft2026
 
PDF
Ethical AI applied to publishing: Presenting wâsikan kisewâtisiwin, an AI too...
byBookNet Canada
 
PDF
Talaria: A Sound-Driven Music Search Engine for Discovery Beyond Metadata
byShuen-Huei Guan
 
PDF
Teaching Robots how to Read 1/2: AI Center & Classic Document Understanding (...
byanabulhac
 
PDF
Transcript: What ONIX can do: Leveraging metadata to support the discoverabil...
byBookNet Canada
 
PPT
Database Management Systems: Basics, History, Data Models, etc.
byParithi Thamizh
 
PPTX
Achieve enterprise automation with SAP BTP solutions and SAP Signavio
bydarrellkiwi
 
PDF
What Is AI LXP and Why Enterprises Are Adopting It.pdf
byneuralminds4
 
PDF
Deploying Windows Clients & Managing Identities
byVICTOR MAESTRE RAMIREZ
 
PPTX
AI in Marine Insurance Future of Smarter Risk, Faster Claims & Safer Shipping...
byAutomationEdge Technologies
 
DOCX
Best Web to Learn About Buying Verified Skrill Accounts (Los Angeles).docx
byhttps://topsellerit.com/product/buy-verified-binance-accounts/
 
PDF
Lightweight, Travel-Ready Freedom for Adults and Seniors
byTopmate
 
PDF
TopMate ES11 3-Wheel Electric Scooter: Comfortable, Stable Mobility for Every...
byTopmate
 
PPTX
Spacewalk 2026 - Presented at the IMAX in Raleigh, NC
byAll Things Open
 
PPTX
The Abomination of AI – keynote at ICoSCI 2026
byAlan Dix
 
How the EU Ecolabel's Record Growth Creates ESG Opportunities for CRE
byWastify AI
 
One String, Many Prompts: AI Code Generation
byGeoffrey Goetz
 
Webinar: EVerest for Production: Accelerating EV Charger Development w/ Indus...
byDanBrown980551
 
Kubernetes Cloud Native Indonesia Meetup - January 2026
byPrasta Maha
 
Apache Kafka 101 for Techies in IT dep.pptx
byamulyareddyk97
 
API Gateway Architecture - Technical Report 2026
byPowersoft2026
 
Ethical AI applied to publishing: Presenting wâsikan kisewâtisiwin, an AI too...
byBookNet Canada
 
Talaria: A Sound-Driven Music Search Engine for Discovery Beyond Metadata
byShuen-Huei Guan
 
Teaching Robots how to Read 1/2: AI Center & Classic Document Understanding (...
byanabulhac
 
Transcript: What ONIX can do: Leveraging metadata to support the discoverabil...
byBookNet Canada
 
Database Management Systems: Basics, History, Data Models, etc.
byParithi Thamizh
 
Achieve enterprise automation with SAP BTP solutions and SAP Signavio
bydarrellkiwi
 
What Is AI LXP and Why Enterprises Are Adopting It.pdf
byneuralminds4
 
Deploying Windows Clients & Managing Identities
byVICTOR MAESTRE RAMIREZ
 
AI in Marine Insurance Future of Smarter Risk, Faster Claims & Safer Shipping...
byAutomationEdge Technologies
 
Best Web to Learn About Buying Verified Skrill Accounts (Los Angeles).docx
byhttps://topsellerit.com/product/buy-verified-binance-accounts/
 
Lightweight, Travel-Ready Freedom for Adults and Seniors
byTopmate
 
TopMate ES11 3-Wheel Electric Scooter: Comfortable, Stable Mobility for Every...
byTopmate
 
Spacewalk 2026 - Presented at the IMAX in Raleigh, NC
byAll Things Open
 
The Abomination of AI – keynote at ICoSCI 2026
byAlan Dix
 

Nios II Embedded Processor: Embedded World 2010

  • 1.
    The Nios IIProcessor Learning Zone @ Embedded World 2010 © 2010 Altera Corporation—Public
  • 2.
    Nios II Versions 32-bit RISC Nios II Processor comes in three ISA compatible versions: − FAST: Optimized for Speed − STANDARD: Balanced for Speed & Size − ECONOMY: Optimized for Size Software code is binary compatible across all versions - No software changes required © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 3.
    Nios II ProcessorFeatures Configurable: − Core features – caches, interrupts, custom instructions, etc. − User Defined Peripheral Set Automated processor configuration and system integration Powerful software tools − Eclipse IDE, C/C++ Development Tools, Trace Debug, Flash Programmer, etc. Third party support for RTOS, middleware and debug tools © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 4.
    Nios II ProcessorConfiguration Nios II Processor Core reset Instruction General Master Instruction and Program Instruction and clock Purpose Port Data Trace Controller Data Trace Registers Instruction JTAG interface Hardware- & Cache to Software Assisted Address Debugger Debug Module Generation Status & Control Registers Tightly Tightly High Speed Trace Trace Coupled Coupled Connection Trace port Trace port I-Memory Memory Memory I-Memory to Trace Pod Breakpoints Breakpoints Exception Tightly Tightly HW Controller MMU HW Coupled Coupled D-Memory D-Memory Interrupt MPU irq[31..0] Controller Data Master Port Data Custom Cache Custom Instruction Arithmetic I/O Signals Logic Logic Unit © 2010 Altera Corporation—Public = Configurable = Optional & Configurable ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. = Fixed = Debug Options
  • 5.
    Nios II ProcessorBenchmark Data Cyclone® III / IV FPGAs Stratix® IV FPGAs Clock Clock Speed DMIPS LEs Speed DMIPS ALUTs (MHz) (MHz) Nios II /f 175 195 1,800 290 340 1,020 Nios II /s 145 90 1,300 250 150 850 Nios II /e 215 30 650 340 48 520 Note: Cyclone devices range from 5K LEs to >100KLEs © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 6.
    3 Ways toIncrease Performance Custom Hardware Multi-Processor Instructions Accelerators System FPGA FPGA FPGA Nios II Nios Nios II Nios Nios II Nios External External Nios II PCIe Nios PCIe Custom Custom Hardware Hardware CPU or CPU or Instructions Instructions Accelerator Accelerator DSP DSP Nios II Nios Accelerate CPU Add external Add more processing co-processing processors performance with hardware to (internal &/or application- accelerate data external) to increase specific hardware functions processing power © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 7.
    Accelerating Software inFPGA Custom Add Custom instruction: CUST A,B,C Logic − Ideal for complex bit/word operations A + - Add hardware accelerator << C - Out >> − Processor & accelerator can run concurrently B & − More work per clock − Lower fMAX, power, cost Nios II Embedded Processor − Ideal for block operations Control 2,500 Nios II Iterations/Second DMA DMA Custom Accelerator Instruction 2,000 1,500 530 Times 27 Times Faster 1,000 Faster Arbiter Arbiter 500 0 Software Custom Accelerator Program Data Data Memory Memory Memory Only Instruction © 2010 Altera Corporation—Public * Accelerator running 64Kb CRC at 100 MHz ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 8.
    Altera C2H –the SW Accelerator Solution Generates and integrates a custom hardware accelerator from an ANSI C function. C2H C2H CPU Accelerator Accelerator Arbiter Arbiter Arbiter Arbiter Program Data Data Memory Memory Memory © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 9.
    Hardware Development Flow Hardware HW Simulation Configure & Integrate Hardware Configuration FPGA © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 10.
    Creating Systems WithSOPC Builder © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 11.
    SOPC Builder IPCores Over 50 IP cores and components available Interface protocols − Ethernet, RapidIO®, PCI, SPI, UART, USB, etc. Processors − Nios II, Cortex M1, Coldfire V1, etc. Memories and memory controllers − DMA, flash controllers, SDRAM controllers Peripherals − Display, microcontroller peripherals, etc. Video and imaging processing − Alpha blender mixer, Deinterlacer, etc. Plus many more © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 12.
    Embedded Development Flow Hardware Configure & Integrate Hardware System .ptf Configuration Information .sopc Software FPGA Compile & Debug © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 13.
    Nios II EmbeddedDesign Suite Integrated Software Nios II Software Development Build Tools Manage, Build, Debug Embedded Design Suite HAL API Peripheral Drivers GNU Tools and Runtime Debugger, Software Library © 2010 Altera Corporation—Public C/C++Compiler ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 14.
    Nios II OperatingSystem / Middleware Support LINUX embOS µCLinux ERIKA & RT-Druid Open Source Open Source www.niosforum.org www.niosforum.org © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 15.
    Partner Software DevelopmentTools Optimizing C Compiler © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 16.
    Other Processor Options ARM Cortex-M1 Freescale ColdFire V1 Evatronix X86 Octera PPC 405 Leon 3 Many legacy cores – 8051, 6502, etc © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 17.
    Why your nextembedded project might use a Nios II processor… If standard microcontrollers I/O I/O I/O or processors don’t offer enough… FPGA − Functionality CUSTOM LOGIC − System Integration Nios II DSP I/O − Power/performance ratio − Product flexibility − Obsolescence protection …then the Nios II processor is for you! Innovate with Nios II & FPGA! © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 18.
    Thank You www.altera.com © 2010 Altera Corporation—Public
  • 19.
    Back-up © 2010 AlteraCorporation—Public
  • 20.
    First Step inSystem Design © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 21.
    What is SOPCBuilder? IP delivery and system generation tool: − GUI based − IP configuration − System configuration − Automated IP integration © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 22.
    Traditional System Design Processor Ethernet (Bus Master) Interrupt (Bus Master) 32-Bit Controller 32-Bit Address Address Address High Data Data Decoder High Arbiter Engineering Engineering Overhead! Overhead! Width-Match Width-Match Width-Match Width-Match Width-Match UART Memory Timer PCI DDR2 8-Bit 32-Bit 16-Bit 64-Bit 64-Bit Clock 1 Clock 2 Clock 1 © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 23.
    SOPC Builder Integration Processor Ethernet (Bus Master) (Bus Master) 32-Bit 32-Bit Integration is Integration is Fast, Easy and Fast, Easy and Error Free! Error Free! Automatically Generated System Interconnect Fabric Address Address Interrupt Interrupt Burst Burst Wait-state Wait-state Multi-clock Multi-clock Decoder Decoder Controller Controller Transfers Transfers Generation Generation Domain Domain Arbiter Arbiter Arbiter Arbiter Arbiter Arbiter Arbiter Arbiter Arbiter Arbiter Width-Match Width-Match Width-Match Width-Match Width-Match Width-Match Width-Match Width-Match Width-Match Width-Match UART Memory Timer PCI DDR2 8-Bit 32-Bit 16-Bit 64-Bit 64-Bit Clock 1 Clock 2 Clock 1 © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 24.
    SOPC Builder © 2010Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 25.
    Component Selection Pool of “SOPC Builder Ready” Pool of “SOPC Builder Ready” Components Components −− Communications Communications −− DSP DSP −− Bus Interfaces Bus Interfaces −− Bridges Bridges −− Memory Controllers Memory Controllers Nios & Nios II®®Processors Nios & Nios II Processors Over 60 Third Party IP Support Third Party IP Support Cores Available Today © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 26.
    Component Configuration Select Component from Select Component from SOPC library SOPC library Wizard based configuration Wizard based configuration for individual component for individual component properties properties Component added to list of Component added to list of active components active components Add, remove or modify Add, remove or modify component properties at component properties at any time any time © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 27.
    SOPC Builder NiosII Processor Options Select best fit processor core Configure caches Configure debug option Integrate custom instructions Edit and Regenerate at Any Time! © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 28.
    System Configuration Connection Patch Panel Connection Patch Panel −− One click to connect One click to connect component component Each master can connect Each master can connect to one or many slaves to one or many slaves Configure connections to Configure connections to optimize throughput optimize throughput Set Arbitration priorities Set Arbitration priorities © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 29.
    System Component Configuration Configure how each Component Configure how each Component fits into the System fits into the System −− Interrupt Request (IRQ) Level Interrupt Request (IRQ) Level −− Base Address Base Address −− Clock Source Clock Source Auto-assign option Auto-assign option Error checking Error checking Edit values at any time Edit values at any time Lock critical settings Lock critical settings Click on ‘Generate’ button Click on ‘Generate’ button to create system © 2010 Altera Corporation—Public to create system ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 30.
    Developing Software forthe Nios II Processor © 2010 Altera Corporation—Public
  • 31.
    Nios II IDEDebug Perspective Re-start Debugger Re-Run Program Basic Debug • Run Controls • Stack View • Active Debug Sessions Double-click to add breakpoints Memory View • Variables • Registers • Signals © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 32.
    Processor - FPGAInterfaces = master = slave Processor FPGA or DSP Avalon GPIO, Switch Fabric RS232, I/O etc. I/F IP IP CPU / DSP CPU Co-Proc Specific IP IP I/F SRAM SDRAM etc. Memory IP IP Automatically Generated © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 33.
    Processor - FPGAInterfaces = master = slave Processor FPGA or DSP Avalon Switch Fabric IP CPU / DSP Industry Interface Standard PCIe PCI e Hard IP I/F High IP Performance IP Automatically Generated © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 34.
    Processor - FPGAInterfaces = master = slave Processor FPGA Avalon Switch Fabric IP Industry Interface Standard PCIe CPU PCIe Hard IP I/F High IP Performance IP Automatically Generated © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 35.
    Co-processing Solution Example USB PCIe I/O Hub Processor DSP Graphics (Intel Atom) (Optional) Hard Disk PCIe RapidIO DVI Isolation and RJ-45 Industrial Motor Control Ethernet Power Stage Isolation PWM and RJ-45 Sensor Camera ADC/DAC OPTO I/O © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 36.
    Nios II EmbeddedEvaluation Kit, Cyclone III Edition Embedded software evaluation platform Development board based on Cyclone III FPGA with touch-screen LCD Software applications and tutorials − Web server − Picture viewer − Graphics acceleration − and more Development software: Nios II EDS, SOPC Builder, Quartus II Web Edition Low Cost: $449 © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
  • 37.
    NEW Altera EmbeddedSystems Development Kit, Cyclone III Edition Complete platform for proto-typing embedded systems (3C120) List price: $1995 IP Licensing purchased separately Embedded IP Suite (IPS-EMBEDDED) $995 − Nios® II processor, DDR/DDR2 Memory controllers, Triple Speed Ethernet and software stack © 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.