This document discusses system organization and input/output device interfaces. It covers several topics: 1. Single bus architecture with memory-mapped I/O and interface circuits to connect devices to the bus. 2. Program-controlled I/O using polling and interrupts to handle asynchronous devices. 3. Direct memory access (DMA) for high-speed transfer of blocks of data between memory and I/O devices. 4. Details of interrupt handling including priorities, nesting, and vectored interrupts.

1. CHAPTER 5.
SYSTEM ORGANIZATION
By Mr.M.A.Chimanna
1

2. ACCESSING I/O DEVICES
2

3. SINGLE BUS
3
Processor Memory
I/O device 1 I/O device n
Bus
Figure 4.1. A single-bus structure.

4. MEMORY-MAPPED I/O
 When I/O devices and the memory share the
same address space, the arrangement is called
memory-mapped I/O.
 Any machine instruction that can access
memory can be used to transfer data to or from
an I/O device.
Move DATAIN, R0
Move R0, DATAOUT
 Some processors have special In and Out
instructions to perform I/O transfer.
4

5. INTERFACE
5
I/O
Bus
Address lines
Data lines
Control lines
Figure 4.2. I/O interface for an input device.
interf acedecoder
Address Data and
status registers
Control
circuits
Input dev ice

6. PROGRAM-CONTROLLED I/O
 I/O devices operate at speeds that are very much
different from that of the processor.
 Keyboard, for example, is very slow.
 It needs to make sure that only after a character is
available in the input buffer of the keyboard
interface; also, this character must be read only
once.
6

7. THREE MAJOR MECHANISMS
 Program-controlled I/O – processor polls the device.
 Interrupt
 Direct Memory Access (DMA)
7

8. INTERRUPTS
8

9. OVERVIEW
 In program-controlled I/O, the program enters a
wait loop in which it repeatedly tests the device
status. During the period, the processor is not
performing any useful computation.
 However, in many situations other tasks can be
performed while waiting for an I/O device to
become ready.
 Let the device alert the processor.
9

10. ENABLING AND DISABLING INTERRUPTS
 Since the interrupt request can come at any time, it
may alter the sequence of events from that
envisaged by the programmer.
 Interrupts must be controlled.
10

11. ENABLING AND DISABLING INTERRUPTS
 The interrupt request signal will be active until it
learns that the processor has responded to its
request. This must be handled to avoid successive
interruptions.
 Let the interrupt be disabled/enabled in the
interrupt-service routine.
 Let the processor automatically disable interrupts
before starting the execution of the interrupt-service
routine.
11

12. HANDLING MULTIPLE DEVICES
 How can the processor recognize the device requesting an
interrupt?
 Given that different devices are likely to require different
interrupt-service routines, how can the processor obtain the
starting address of the appropriate routine in each case?
 (Vectored interrupts)
 Should a device be allowed to interrupt the processor while
another interrupt is being serviced?
 (Interrupt nesting)
 How should two or more simultaneous interrupt requests
be handled?
 (Daisy-chain)
12

13. VECTORED INTERRUPTS
 A device requesting an interrupt can identify itself
by sending a special code to the processor over the
bus.
 Interrupt vector
 Avoid bus collision
13

14. INTERRUPT NESTING
 Simple solution: only accept one interrupt at a time, then disable
all others.
 Problem: some interrupts cannot be held too long.
 Priority structure
14
Priority arbitration
Dev ice 1 Dev ice 2 Dev icep
circuit
Processor
Figure 4.7. Implementation of interrupt priority using individual
INTA1
INTR1 I NTRp
INTAp
interrupt-request and acknowledge lines.

15. SIMULTANEOUS REQUESTS
15
Figure 4.8. Interrupt priority schemes.
(b) Arrangement of priority groups
Dev ice Dev ice
circuit
Priority arbitration
Processor
Dev ice Dev ice
(a) Daisy chain
Processor
Dev ice 2
I NTR
INTA
I NTR1
INTR p
INTA1
INTAp
Dev icenDev ice 1

16. CONTROLLING DEVICE REQUESTS
 Some I/O devices may not be allowed to issue
interrupt requests to the processor.
 At device end, an interrupt-enable bit in a control
register determines whether the device is allowed
to generate an interrupt request.
 At processor end, either an interrupt enable bit in
the PS register or a priority structure determines
whether a given interrupt request will be accepted.
16

17. EXCEPTIONS
 Recovery from errors
 Debugging
 Trace
 Breakpoint
 Privilege exception
17

18. USE OF INTERRUPTS IN OPERATING SYSTEMS
 The OS and the application program pass control
back and forth using software interrupts.
 Supervisor mode / user mode
 Multitasking (time-slicing)
 Process – running, runnable, blocked
 Program state
18

19. PROCESSOR EXAMPLES
19

20. Condition
CodesInterrupt
Priority
Superv isor
Trace
T S X N Z V C
012348101315
Figure 4.14.Processor status register in the 68000 processor.
20

21. Main program
MOVE.L #LINE,PNTR Initialize buffer pointer.
CLR EOL Clearend-of-lineindicator.
ORI.B #4,CONTROL Set bit KEN.
MOVE #$100,SR Setprocessorpriority to1.
...
Interrupt-serviceroutine
READ MOVEM.L A0/D0, (A7) SaveregistersA0, D0 onstack.
MOVEA.L PNTR,A0 Load addresspointer.
MOVE.B DATAIN,D0 Get input character.
MOVE.B D0,(A0)+ Store it in memorybuffer.
MOVE.L A0,PNTR Updatepointer.
CMPI.B #$0D,D0 Check if CarriageReturn.
BNE RTRN
MOVE #1,EOL Indicateend of line.
ANDI.B #$FB,CONTROL Clearbit KEN.
RTRN MOVEM.L (A7)+,A0/D0 RestoreregistersD0, A0.
RTE
Figure 4.15. A 68000 interrupt-service routine to read an input line from a keyboard based on Figure 4.9.
–
21

22. DIRECT MEMORY ACCESS
22

23. DMA
 Think about the overhead in both polling and
interrupting mechanisms when a large block of
data need to be transferred between the
processor and the I/O device.
 A special control unit may be provided to allow
transfer of a block of data directly between an
external device and the main memory, without
continuous intervention by the processor –
direct memory access (DMA).
 The DMA controller provides the memory
address and all the bus signals needed for data
transfer, increment the memory address for
successive words, and keep track of the
number of transfers. 23

24. DMA PROCEDURE
 Processor sends the starting address, the
number of data, and the direction of transfer to
DMA controller.
 Processor suspends the application program
requesting DMA, starts DMA transfer, and starts
another program.
 After the DMA transfer is done, DMA controller
sends an interrupt signal to the processor.
 The processor puts the suspended program in
the Runnable state.
24

25. DMA REGISTER
25
Done
IE
IRQ
Status and control
Starting address
Word count
WR/
31 30 1 0
Figure 4.18.Registers in a DMA interface.

26. SYSTEM
26
Figure 4.19.Use of DMA controllers in a computer system.
memory
Processor
Key board
Sy stem bus
Main
Interface
Network
Disk/DMA
controller Printer
DMA
controller
DiskDisk

27. MEMORY ACCESS
 Memory access by the processor and the DMA
controller are interwoven.
 DMA device has higher priority.
 Among all DMA requests, top priority is given to
high-speed peripherals.
 Cycle stealing
 Block (burst) mode
 Data buffer
 Conflicts
27

28. BUS ARBITRATION
 The device that is allowed to initiate data transfers
on the bus at any given time is called the bus
master.
 Bus arbitration is the process by which the next
device to become the bus master is selected and
bus mastership is transferred to it.
 Need to establish a priority system.
 Two approaches: centralized and distributed
28

29. CENTRALIZED ARBITRATION
29
Processor
DMA
controller
1
DMA
controller
2BG1 BG2
BR
BBSY
Figure 4.20. A simple arrangement for bus arbitration using a daisy chain.

30. CENTRALIZED ARBITRATION
30
BBSY
BG1
BG2
Bus
master
BR
Processor DMA controller 2 Processor
Figure 4.21.Sequence of signals during transfer of bus mastership
for the devices in Figure 4.20.
Time

31. DISTRIBUTED ARBITRATION
31
Figure 4.22. A distributed arbitration scheme.
Interf ace circuit
f or dev ice A
0 1 0 1 0 1 1 1
O.C.
Vcc
Start-Arbitration
ARB0
ARB1
ARB2
ARB3

32. BUSES
32

33. OVERVIEW
 The primary function of a bus is to provide a
communications path for the transfer of data.
 A bus protocol is the set of rules that govern the
behavior of various devices connected to the
bus as to when to place information on the bus,
assert control signals, etc.
 Three types of bus lines: data, address, control
 The bus control signals also carry timing
information.
 Bus master (initiator) / slave (target)
33

34. SYNCHRONOUS BUS TIMING
34
Figure 4.23. Timing of an input transfer on a synchronous bus.
Bus cy cle
Data
Bus clock
command
Address and
t0 t1 t2
Time

35. SYNCHRONOUS BUS DETAILED TIMING
35
Figure 4.24.A detailed timing diagram for the input transfer of Figure 4.23.
Data
command
Address and
t0 t1
t2
command
Address and
Data
Seen by master
Seen by slave
tAM
tAS
tDS
tDM

36. MULTIPLE-CYCLE TRANSFERS
36
Figure 4.25.An input transfer using multiple clock cycles.
Clock
Address
Command
Data
Slave-ready

37. ASYNCHRONOUS BUS – HANDSHAKING
PROTOCOL FOR INPUT OPERATION
37
Figure 4.26. Handshake control of data transfer during an input operation.
Slav e-ready
Data
Master-ready
and command
Address
Bus cy cle
t1 t2 t3 t4 t5t0
Time

38. ASYNCHRONOUS BUS – HANDSHAKING
PROTOCOL FOR OUTPUT OPERATION
38
Figure 4.27. Handshake control of data transfer during an output operation.
Bus cy cle
Data
Master-ready
Slav e-ready
and command
Address
t1 t2 t3 t4 t5t0
Time

39. DISCUSSION
 Trade-offs
 Simplicity of the device interface
 Ability to accommodate device interfaces that
introduce different amounts of delay
 Total time required for a bus transfer
 Ability to detect errors resulting from addressing a
nonexistent device or from an interface malfunction
 Asynchronous bus is simpler to design.
 Synchronous bus is faster.
39

40. INTERFACE CIRCUITS
40

41. FUNCTION OF I/O INTERFACE
 Provide a storage buffer for at least one word of
data;
 Contain status flags that can be accessed by
the processor to determine whether the buffer
is full or empty;
 Contain address-decoding circuitry to
determine when it is being addressed by the
processor;
 Generate the appropriate timing signals
required by the bus control scheme;
 Perform any format conversion that may be
necessary to transfer data between the bus and
the I/O device. 41

42. PARALLEL PORT
 A parallel port transfers data in the form of a
number of bits, typically 8 or 16, simultaneously to
or from the device.
 For faster communications
42

43. PARALLEL PORT – INPUT INTERFACE
(KEYBOARD TO PROCESSOR CONNECTION)
43
Valid
Data
Key board
switches
Encoder
and
debouncing
circuit
SIN
Input
interface
Data
Address
R /
Master-ready
Slave-ready
W
DATAIN
Processor
Figure 4.28. Keyboard to processor connection.

44. 44

45. PARALLEL PORT – INPUT INTERFACE
(KEYBOARD TO PROCESSOR CONNECTION)
45

46. PARALLEL PORT – OUTPUT INTERFACE
(PRINTER TO PROCESSOR CONNECTION)
46
CPU SOUT
Output
interface
Data
Address
R /
Master-eady
Slave-ready
Valid
W
DataDATAOUT
Figure 4.31.Printer to processor connection.
PrinterProcessor
Idle

47. 47

48. DATAIN
1
SIN
Ready
A31
A1
A0
Address
decoder
D7
D0
R/ W
Figure 4.33. Combined input/output interface circuit.
A2
DATAOUT
Input
status
Bus
PA7
PA0
CA
PB7
PB0
CB1
CB2
SOUT
D1
RS1
RS0
My-address
Handshake
control
Master-
Ready
Slave-
48

49. 49

50. RECALL THE TIMING PROTOCOL
50
Figure 4.25.An input transfer using multiple clock cycles.
Address
Command
Data
Slave-ready

51. Handshake
control
DATAOUT
Printer
data
Idle
Valid
Read Load
SOUT
ready
A31
A1
A0
Address
decoder
D7 Q7
D0 Q0
D7
D0
Figure 4.35. A parallel point interface for the bus of Figure 4.25,
with a state-diagram for the timing logic.
status data
D1 Q1D0
Timing
Logic
Clock
My-address
R/W
Slave-
Idle Respond
My-address
Go
Go=1
51

52. SERIAL PORT
 A serial port is used to connect the processor to I/O
devices that require transmission of data one bit at
a time.
 The key feature of an interface circuit for a serial
port is that it is capable of communicating in bit-
serial fashion on the device side and in a bit-parallel
fashion on the bus side.
 Capable of longer distance communication than
parallel transmission.
52

53. 53

54. STANDARD I/O INTERFACES
54

55. OVERVIEW
 The needs for standardized interface signals and
protocols.
 Motherboard
 Bridge: circuit to connect two buses
 Expansion bus
 ISA, PCI, SCSI, USB,…
55

56. memory
Processor
Bridge
Processor bus
PCI bus
Main
memory
Additional
controller
CD-ROM
controller
Disk
Disk 1 Disk 2 ROM
CD-
SCSI
controller
USB
controller
Video
Keyboard Game
disk
IDE
SCSI bus
Figure 4.38. An example of a computer system using different interface standards.
ISA
interface
Ethernet
interface
56