CETPA INFOTECH PVT LTD is one of the IT education and training service provider brands of India that is preferably working in 3 most important domains. It includes IT Training services, software and embedded product development and consulting services.
http://www.cetpainfotech.com
CETPA INFOTECH PVT LTD is one of the IT education and training service provider brands of India that is preferably working in 3 most important domains. It includes IT Training services, software and embedded product development and consulting services.
Template driven code generation tool, fore real time and safety critical systems.
API message formating and serialisation.
Template driven source code generator for any language : Ada, C, C#, Java, ...
CETPA INFOTECH PVT LTD is one of the IT education and training service provider brands of India that is preferably working in 3 most important domains. It includes IT Training services, software and embedded product development and consulting services.
http://www.cetpainfotech.com
CETPA INFOTECH PVT LTD is one of the IT education and training service provider brands of India that is preferably working in 3 most important domains. It includes IT Training services, software and embedded product development and consulting services.
Template driven code generation tool, fore real time and safety critical systems.
API message formating and serialisation.
Template driven source code generator for any language : Ada, C, C#, Java, ...
Template driven code generation tool, fore real time and safety critical systems.
API message formating and serialisation.
Template driven source code generator for any language : Ada, C, C#, Java, ...
Program, Language, & Programming Language
Object Oriented Programming vs Procedure Oriented Programming
About C
Why still Learn C?
Basic Terms
C Stuff
C Syntax
C Program
In this short survey we consider example of most promising practical approach to improve coding gain under Factor graph in high performance regime (when we have enougth iteration budget [complexity and power comsumption for asic] to waiting recovery of variable nodes) Multi-Edge Type LDPC codes.
Those slides describe digital design using Verilog HDL,
starting with Design methodologies for any digital circuit then difference between s/w (C/C++) and H/w (Verilog) and the most important constructs that let us start hardware design using Verilog HDL.
Template driven code generation tool, fore real time and safety critical systems.
API message formating and serialisation.
Template driven source code generator for any language : Ada, C, C#, Java, ...
Program, Language, & Programming Language
Object Oriented Programming vs Procedure Oriented Programming
About C
Why still Learn C?
Basic Terms
C Stuff
C Syntax
C Program
In this short survey we consider example of most promising practical approach to improve coding gain under Factor graph in high performance regime (when we have enougth iteration budget [complexity and power comsumption for asic] to waiting recovery of variable nodes) Multi-Edge Type LDPC codes.
Those slides describe digital design using Verilog HDL,
starting with Design methodologies for any digital circuit then difference between s/w (C/C++) and H/w (Verilog) and the most important constructs that let us start hardware design using Verilog HDL.
DOUBLE PRECISION FLOATING POINT CORE IN VERILOGIJCI JOURNAL
A floating-point unit (FPU) is a math coprocessor, a part of a computer system specially designed to carry
out operations on floating point numbers. The term floating point refers to the fact that the radix point can
"float"; that is, it can placed anywhere with respect to the significant digits of the number. Double
precision floating point, also known as double, is a commonly used format on PCs due to its wider range
over single precision in spite of its performance and bandwidth cost. This paper aims at developing the
verilog version of the double precision floating point core designed to meet the IEEE 754 standard .This
standard defines a double as sign bit, exponent and mantissa. The aim is to build an efficient FPU that
performs basic functions with reduced complexity of the logic used and also reduces the memory
requirement as far as possible.
Design and Implementation of Area Efficiency AES Algoritham with FPGA and ASIC,paperpublications3
Abstract: A public domain encryption standard is subject to continuous, vigilant, expert cryptanalysis. AES is a symmetric encryption algorithm processing data in block of 128 bits. Under the influence of a key, a 128-bit block is encrypted by transforming it in a unique way into a new block of the same size. To implement AES Rijndael algorithm on FPGA using Verilog and synthesis using Xilinx, Plain text of 128 bit data is considered for encryption using Rijndael algorithm utilizing key. This encryption method is versatile used for military applications. The same key is used for decryption to recover the original 128 bit plain text. For high speed applications, the Non LUT based implementation of AES S-box and inverse S-box is preferred. Development of physical design of AES-128 bit is done using cadence SoC encounter. Performance evaluation of the physical design with respect to area, power, and time has been done. The core consumes 10.11 mW of power for the core area of 330100.742 μm2.
Keywords: Encryption, Decryption Rijndael algorithm, FPGA implementation, Physical Design.
Design and Implementation of Area Efficiency AES Algoritham with FPGA and ASICpaperpublications3
Abstract: A public domain encryption standard is subject to continuous, vigilant, expert cryptanalysis. AES is a symmetric encryption algorithm processing data in block of 128 bits. Under the influence of a key, a 128-bit block is encrypted by transforming it in a unique way into a new block of the same size. To implement AES Rijndael algorithm on FPGA using Verilog and synthesis using Xilinx, Plain text of 128 bit data is considered for encryption using Rijndael algorithm utilizing key. This encryption method is versatile used for military applications. The same key is used for decryption to recover the original 128 bit plain text. For high speed applications, the Non LUT based implementation of AES S-box and inverse S-box is preferred. Development of physical design of AES-128 bit is done using cadence SoC encounter. Performance evaluation of the physical design with respect to area, power, and time has been done. The core consumes 10.11 mW of power for the core area of 330100.742 μm2.
VHDL is defined by IEEE. This standard is known by all the VHDL tool developers. So
there is only one language to learn. This language is used by all the circuit designers around the world. The life time for this language is assured, since it is an IEEE standards. Any investment or learning is assured for lifetime. Abundance of models available from different sources can be used with ease. Some tools might support Foreign Language Interface, by which you can add your model in C language to the VHDL code. It is a modern language, powerful and general. Other advantages include readability of the code and portability. The code developed is portable to any technology at any time. Time to market is short (leads to leadership in the market). Any error found during the simulation phase is less expensive than by discovering the errors after making the circuit board (Investment is saved). The great advantage is that the Project Managers can modify the specification without leading to disaster (only the necessary portion of the code need to be changed). It can deliver designs 100% error free at short duration. New Concepts in
hardware design (for example, in image processing, DSP, etc.,) can be modeled in VHDL and its efficiency or viability can be proven without doing the hardware. A large number of ASICs fail to work when plugged into a system even if they meet their specifications first time. VHDL addresses this issue in two ways: A VHDL specification can be executed in order to achieve a high level of confidence in its correctness before commencing design, and may simulate one to two orders of magnitude faster than a gate level description. A VHDL specification for a part can form the basis for a simulation model to verify the operation of the part in the wider system context (e.g. printed circuit board simulation). This depends on how accurately the specification handles aspects such as timing and initialization.
Yaser Khalifa introduces you to VHDL (VHSIC Hardware Description Language), a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.
This is a classroom presentation for the basic concepts of HDL, using Verilog as the programming language. Module 2 deals with simulation and synthesis in Verilog.
This is a classroom presentation for the basic concepts of HDL, using Verilog as the programming language. Module 3 deals with programmable logic devices.
This is a slideshow depicting the importance of guru in the spiritual life. And in addition, about the practice of Gaayathree manthra and its specialties.
This is a slide-show containing the names of all the literary works written by Adi Shankaracharya. The last slide contains the summary of his greatest contributions.
An introduction to the practice of Ashtangayoga, with some prerequisites and attitudinal changes, concluding with some valid health tips and lifestyle changes.
Preparation to yogic breathing as well as some popular methods of yogic breathing (pranayama) are mentioned here, along with some additional health tips.
These slides are with less text and more pictures, with each slide sequentially related to the next one in an intuitive way, and hence the viewer should follow his/her intuitive skills in order to comprehend the flow. The truth is one, ultimately.
TECHNICAL TRAINING MANUAL GENERAL FAMILIARIZATION COURSEDuvanRamosGarzon1
AIRCRAFT GENERAL
The Single Aisle is the most advanced family aircraft in service today, with fly-by-wire flight controls.
The A318, A319, A320 and A321 are twin-engine subsonic medium range aircraft.
The family offers a choice of engines
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
Democratizing Fuzzing at Scale by Abhishek Aryaabh.arya
Presented at NUS: Fuzzing and Software Security Summer School 2024
This keynote talks about the democratization of fuzzing at scale, highlighting the collaboration between open source communities, academia, and industry to advance the field of fuzzing. It delves into the history of fuzzing, the development of scalable fuzzing platforms, and the empowerment of community-driven research. The talk will further discuss recent advancements leveraging AI/ML and offer insights into the future evolution of the fuzzing landscape.
Forklift Classes Overview by Intella PartsIntella Parts
Discover the different forklift classes and their specific applications. Learn how to choose the right forklift for your needs to ensure safety, efficiency, and compliance in your operations.
For more technical information, visit our website https://intellaparts.com
Quality defects in TMT Bars, Possible causes and Potential Solutions.PrashantGoswami42
Maintaining high-quality standards in the production of TMT bars is crucial for ensuring structural integrity in construction. Addressing common defects through careful monitoring, standardized processes, and advanced technology can significantly improve the quality of TMT bars. Continuous training and adherence to quality control measures will also play a pivotal role in minimizing these defects.
Automobile Management System Project Report.pdfKamal Acharya
The proposed project is developed to manage the automobile in the automobile dealer company. The main module in this project is login, automobile management, customer management, sales, complaints and reports. The first module is the login. The automobile showroom owner should login to the project for usage. The username and password are verified and if it is correct, next form opens. If the username and password are not correct, it shows the error message.
When a customer search for a automobile, if the automobile is available, they will be taken to a page that shows the details of the automobile including automobile name, automobile ID, quantity, price etc. “Automobile Management System” is useful for maintaining automobiles, customers effectively and hence helps for establishing good relation between customer and automobile organization. It contains various customized modules for effectively maintaining automobiles and stock information accurately and safely.
When the automobile is sold to the customer, stock will be reduced automatically. When a new purchase is made, stock will be increased automatically. While selecting automobiles for sale, the proposed software will automatically check for total number of available stock of that particular item, if the total stock of that particular item is less than 5, software will notify the user to purchase the particular item.
Also when the user tries to sale items which are not in stock, the system will prompt the user that the stock is not enough. Customers of this system can search for a automobile; can purchase a automobile easily by selecting fast. On the other hand the stock of automobiles can be maintained perfectly by the automobile shop manager overcoming the drawbacks of existing system.
NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...Amil Baba Dawood bangali
Contact with Dawood Bhai Just call on +92322-6382012 and we'll help you. We'll solve all your problems within 12 to 24 hours and with 101% guarantee and with astrology systematic. If you want to take any personal or professional advice then also you can call us on +92322-6382012 , ONLINE LOVE PROBLEM & Other all types of Daily Life Problem's.Then CALL or WHATSAPP us on +92322-6382012 and Get all these problems solutions here by Amil Baba DAWOOD BANGALI
#vashikaranspecialist #astrologer #palmistry #amliyaat #taweez #manpasandshadi #horoscope #spiritual #lovelife #lovespell #marriagespell#aamilbabainpakistan #amilbabainkarachi #powerfullblackmagicspell #kalajadumantarspecialist #realamilbaba #AmilbabainPakistan #astrologerincanada #astrologerindubai #lovespellsmaster #kalajaduspecialist #lovespellsthatwork #aamilbabainlahore#blackmagicformarriage #aamilbaba #kalajadu #kalailam #taweez #wazifaexpert #jadumantar #vashikaranspecialist #astrologer #palmistry #amliyaat #taweez #manpasandshadi #horoscope #spiritual #lovelife #lovespell #marriagespell#aamilbabainpakistan #amilbabainkarachi #powerfullblackmagicspell #kalajadumantarspecialist #realamilbaba #AmilbabainPakistan #astrologerincanada #astrologerindubai #lovespellsmaster #kalajaduspecialist #lovespellsthatwork #aamilbabainlahore #blackmagicforlove #blackmagicformarriage #aamilbaba #kalajadu #kalailam #taweez #wazifaexpert #jadumantar #vashikaranspecialist #astrologer #palmistry #amliyaat #taweez #manpasandshadi #horoscope #spiritual #lovelife #lovespell #marriagespell#aamilbabainpakistan #amilbabainkarachi #powerfullblackmagicspell #kalajadumantarspecialist #realamilbaba #AmilbabainPakistan #astrologerincanada #astrologerindubai #lovespellsmaster #kalajaduspecialist #lovespellsthatwork #aamilbabainlahore #Amilbabainuk #amilbabainspain #amilbabaindubai #Amilbabainnorway #amilbabainkrachi #amilbabainlahore #amilbabaingujranwalan #amilbabainislamabad
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
5. 21/01/2019 Aravinda K., Dept. of E&C, NHCE 5
CO1
Identify the necessity of HDL for the automation
of VLSI design
CO2
Select Verilog for EDA, and describe its structure
and syntax
CO3
Apply the concepts of HDL on programmable
devices, such as CPLD and FPGA
CO4
Translate the design on state machine into
HDL program
CO5
Write optimized HDL codes for simple and
complex systems
CO6
Employ the FPGA hardware for the implementation
of the HDL codes
COURSE OUTCOMES
6. Term Year Number of gates Examples
SSI 1961 Upto 20 logic gates Flip-flops, Decoders,
Registers
MSI 1966 20 till 200 gates Multiplexers, Adders,
Counters
LSI 1971 200 till 10,000 8-bit Microprocessors, RAM,
ROM
VLSI 1980 10,000 till 1,00,000 Microcontrollers, 16 & 32-bit
Microprocessors, DRAM
ULSI 1990 Above 1,00,000 gates 64-bit Microprocessors,
DSPs, SoC
21/01/2019 6Aravinda K., Dept. of E&C, NHCE
MODULE-1: INTRODUCTION TO VERILOG
7. 21/01/2019 Aravinda K., Dept. of E&C, NHCE 7
DESIGN ENTRY
Schematic capture: Lower level of
abstraction (gates, flip-flops, standard
MSI building blocks)
HDL: Higher level of abstraction -
(behavioral: flow-chart, algorithm)
(structural: specific components or
implementations)
SYNTHESIS
Process of conversion of higher-level
abstraction of the design into actual
components at the gate & flip-flop levels.
The output of the synthesis tool is the
netlist, which is a list of gates and a list of
their interconnections.
As the synthesis tool converts the
design descriptions into hardware, it is
also called as “design compiler” or
“silicon compiler”.
11. 21/01/2019 11Aravinda K., Dept. of E&C, NHCE
After the post-synthesis simulation, the design can
be implemented in several different target
technologies (device lengths).
The target could be a completely custom IC, or could
be implemented using the standard parts that are
available from the vendor.
The standard parts are at the lowest level of
sophistication and density, with the usage of old-
fashioned printed circuit board.
The fully-custom ASIC is at the highest level of
density and performance.
The other devices such as CPLD and FPGA come in
between, as programmable solutions.
13. 21/01/2019 13Aravinda K., Dept. of E&C, NHCE
The current two most common target technologies
are FPGAs and ASICs.
The design is mapped into the specific target
technology (channel length), and placed into specific
parts in the target ASIC or FPGA.
During routing, the selected components are
connected to each other, using the available paths.
In case of an ASIC, the routed design is utilized for
generating a photo-mask, which will be utilized for
manufacturing the IC.
In case of an FPGA, the routed design is translated
into a bit file, for the programming of the selected cells
inside the FPGA.
16. 21/01/2019 16Aravinda K., Dept. of E&C, NHCE
HARDWARE DESCRIPTION LANGUAGES
HDL is a textual method of documenting the circuits, and
feeding them into the simulators in the textual form, as opposed
to the graphic form.
HDLs lead to a top-down design methodology (specified and
tested at a high level), and HDLs are designed to be technology
independent.
HDLs can describe a digital system at three different levels –
behavioral (functional description), data flow (logic equations)
and structural (in terms of subcomponents).
17. 21/01/2019 17Aravinda K., Dept. of E&C, NHCE
VHDL Verilog
Government developed
(Designed and sponsored by US
department of defense), and
became IEEE standard in 1987
Commercially developed
(Designed by Gateway design
system corporation), became
IEEE standard in 1995
Strongly typecast, based on
“Ada” language, and is case-
insensitive
Mildly typecast, based on “C”
language, and is case-sensitive
Structured, and is for large and
complex systems (Difficult to
learn, but more powerful)
Simpler, with less syntax and
fewer constructs (Easier to
learn, and less powerful)
Two popular HDLs are Verilog & VHDL. Verilog was a proprietary
language in 1984, and was later owned and opened up by
Cadence, in order to create a vendor-independent language
specification, and to prevent the industry from shifting to VHDL.
18. 21/01/2019 18Aravinda K., Dept. of E&C, NHCE
In addition, there are system design languages, such as
System C and System Verilog, which describe large digital
systems at a block level behavior.
These languages are primarily used for verification and
validation. They help in reducing the design cycle time for large
systems; the design problems become evident in the early
stages, instead of becoming obvious during system integration.
When different blocks of a large system are designed by
different teams, during the initial design process, one team can
make use of the system level description of a block that is being
designed by the other team.
In addition to the system design languages, there are tools
that have emerged, which can convert the models written in
non-HDL, directly into hardware.
19. 21/01/2019 19Aravinda K., Dept. of E&C, NHCE
UNLIKE THE OTHER PROGRAMMING LANGUAGES,
THE CONSTRUCTS OF HDL ARE TAILORED
FOR THE PURPOSE OF SIMULATION AND SYNTHESIS.
21. 21/01/2019 21Aravinda K., Dept. of E&C, NHCE
Verilog Description of Combinational Circuits
The combinational circuits are always working
simultaneously, and hence they are modeled in Verilog
by concurrent statements or continuous assignments.
Concurrent statements are always ready to execute,
and hence, it is possible to simulate the execution of
the several parts of the circuit at the same time.
The Verilog simulator continuously monitors the
right side of each concurrent statement, and whenever
a signal changes, the expression on the right side gets
immediately re-evaluated.
22. 21/01/2019 22Aravinda K., Dept. of E&C, NHCE
#5 indicates a delay of 5 ns, representing the propagation delay
of each logic gate. If it is not included, then the computation will
be instantaneous.
When the statements get executed, the variable “C” gets
computed after 5 ns, and the variable “E” gets computed after
another 5 ns, thus the total delay becoming as 10 ns.
The order of the concurrent statements is not important. The
output for the following will be the same as the previous one:
23. 21/01/2019 23Aravinda K., Dept. of E&C, NHCE
In this example, when the gate delays have different values, the
outputs also update at different times, even though the
statements execute simultaneously.
If A changes at a time-stamp of 5 ns, then D, E and F change at
7 ns, 6 ns and 8 ns respectively.
24. 21/01/2019 24Aravinda K., Dept. of E&C, NHCE
“Delta delay” is an infinitesimally small delay, which is used to
indicate the sequentiality between dependant concurrent
statements. VHDL simulators display the delta delay, whereas
Verilog simulators do not.
The general form of the signal assignment statement is:
The brackets indicate that the delay is optional.
25. 21/01/2019 25Aravinda K., Dept. of E&C, NHCE
Statement Result
assign #10 CLK= ~CLK; Waveform with name “CLK” is produced
assign #10 Clk= ~Clk; Waveform with name “Clk” is produced
assign CLK= ~CLK; The waveform will never advance
A Verilog identifier or a signal name can contain letters,
numbers, underscore character and dollar sign.
A Verilog identifier must start with a letter or an underscore
character.
A Verilog identifier cannot start with a number or dollar sign.
The dollar sign is reserved as the first character for the
system tasks.
26. 21/01/2019 26Aravinda K., Dept. of E&C, NHCE
Valid identifiers Invalid identifiers
adder 4bit_adder
Mux_input $100
_error_code always
_$500 _#123
Every Verilog statement must be terminated with a
semicolon.
Anything following a double slash is treated as a comment to
the end of the line.
Comments for more than one line start with “/*” and end
with “*/”.
Words such as “and”, “or” and “always”, are reserved words.
27. 21/01/2019 27Aravinda K., Dept. of E&C, NHCE
When the signal is of type wire (or net), it generally has
a value of 0 or 1.
The net values in Verilog are represented as -
<number of bits>’<base><value>.
Hence, 1’b0 means “1 position binary 0”. The decimal and
hexadecimal values are represented with “d” and “h”.
A one-dimensional array of bit signals is referred to as a vector.
A 4 bit-wire can be named as vector B, and can be declared as,
wire B[3:0];.
The vector B has an index range 0 through 3, and its elements
are designated as B[0], B[1], B[2] and B[3].
The statement B=4’b1100 assigns 1 to B[3], 1 to B[2], 0 to B[1]
and 0 to B[0].
28. 21/01/2019 28Aravinda K., Dept. of E&C, NHCE
“&&” is the logical AND operator
“&” is the bitwise AND operator
29. 21/01/2019 29Aravinda K., Dept. of E&C, NHCE
Verilog Modules
A Module is a basic building block that declares input and output
signals, and specifies the internal operation of the module.
All the I/O signals have to be listed in the module statement.
Since “C” is an internal signal, it has to be declared as wire.
31. 21/01/2019 31Aravinda K., Dept. of E&C, NHCE
The interface ports can be of type input, output or inout. VHDL is
very strict in compilation, wheras Verilog produces an output even
when the variable is declared as input. However, a variable has to
be declared as inout, if that variable is used by other modules.
32. 21/01/2019 32Aravinda K., Dept. of E&C, NHCE
module FullAdder (X, Y, Cin, Cout, Sum);
output Cout, Sum;
input X, Y, Cin;
assign #10 Sum = X ^ Y ^ Cin;
assign #10 Cout = ( X && Y) || ( X && Cin) || ( Y && Cin);
endmodule
33. 21/01/2019 33Aravinda K., Dept. of E&C, NHCE
In the structural description,
the 4-bit adder is declared as a
module, and the full adder
module is instantiated inside the
4-bit adder module.
Here, each instance of Full
adder has a port map, which
corresponds one-to-one with the
signals in the component port
(FullAdder module).
This method, in which the
order of the signals in the
portmap is same as the order of
the signals in the ports of the
module, is called as “positional
association”.
If the ports are mapped by
name, then it is called as “named
association”.
34. 21/01/2019 34Aravinda K., Dept. of E&C, NHCE
Verilog Assignments
Continuous Procedural
Blocking Non-blockingExplicit Implicit
Keyword: assign Keywords: initial, always
36. 21/01/2019 36Aravinda K., Dept. of E&C, NHCE
Procedural Assignments
Combinational logic constantly reacts to input changes,
whereas synchronous sequential logic responds to changes that
are dependent on the clock.
Therefore, the procedural assignments are used to model the
sequential logic, such as registers and finite state machines.
Unlike the continuous assignments, with procedural
assignments, the execution of statements happens with a
sequence of operations.
The two types of procedural assignment blocks in Verilog are
“initial” and “always”; the LHS of the assignment statements,
inside these blocks, have to be declared as of data type “reg”.
37. 21/01/2019 37Aravinda K., Dept. of E&C, NHCE
initial always
Executes only once Executes in a loop
Executes without waiting Executes after an event
Useful in simulation & verification Useful for synthesis
39. 21/01/2019 39Aravinda K., Dept. of E&C, NHCE
In this example, assuming
the initial values as:
A=1’b1, B=1’b0, C=1’b1,
D=1’b0,
the outputs after completion
of the execution are:
A=1’b0, B=1’b0, C=1’b0,
D=1’b1.
We should be very careful while using “always” to represent
combinational logic. If any input signals are accidentally omitted
from the sensitivity list, there will be mismatches between
simulation and synthesis outcomes.
The statement “always @(*)” avoids such accidental errors.
41. 21/01/2019 41Aravinda K., Dept. of E&C, NHCE
input and inout ports have to be of type “wire”; output ports can
be of either “wire” or “reg” type.
Here, D and E are declared as “reg”, as they are at LHS. Therefore,
D cannot be declared as “inout”.
When the sensitivity list contains “*”, the “always” block gets
triggered for any input signal changes.
42. 21/01/2019 42Aravinda K., Dept. of E&C, NHCE
Note
1. “wire” does not store information, whereas “reg” stores
information. The initial value of a “wire” is “z” (high impedance),
and that of “reg” is “x” (unknown).
2. The operator “=” has a blocking nature inside “always”, whereas
it has a non-blocking (concurrent) nature outside “always”.
3. The operator “<=” has a non-blocking nature inside “always”,
and has no usage as an assignment operator outside “always”.
4. The LHS elements inside the procedural blocks have to be
declared as “reg” data type. But “reg” data type cannot be present
at the LHS of a continuous assignment statement.
5. For synthesizable codes, it is better to use non-blocking
assignments for sequential logic, and blocking assignments for
combinational logic, and not to mix both in the same block.
44. 21/01/2019 44Aravinda K., Dept. of E&C, NHCE
Modeling of flip-flops using “always” block
When a rising edge of the clock
occurs, Q is set equal to D. If the
flip-flop has a delay of 5 ns, then
the statement can be: Q <= #5 D;
If Q changes when D changes,
then it is a transparent latch. In
this code, Q changes when G = 1.
Either (G or D) or (G, D) are
acceptable, in the sensitivity list.
This flip-flop is with active-low
asynchronous “clear” input.
When clear = 0, the flip-flop is
reset; otherwise, Q is updated
with the rising edge of the clock.
45. 21/01/2019 45Aravinda K., Dept. of E&C, NHCE
“if” statements cannot be used
as concurrent. Brace indicates
that any number of “else if” can
be included. Bracket indicates
that “else” is optional.
46. 21/01/2019 46Aravinda K., Dept. of E&C, NHCE
J K Qn
0 0 Qn-1
0 1 0
1 0 1
1 1 Q’n-1
This flip-flop is with active-low
asynchronous “preset” (SN) and
“clear” (RN) inputs, and triggers
on the falling edge of clock.
The characteristic equation of
the flip-flop is, Q+ = JQ’ + K’Q.
47. 21/01/2019 47Aravinda K., Dept. of E&C, NHCE
“Qint” is defined as an internal signal because, RHS cannot have
an output identifier, and inout type cannot be declared as reg.
8 ns represents the time taken to set or to clear, and 10 ns
represents the time taken for Q to change.
In the “if” statement, either (~RN) or (RN == 1’b0) are acceptable.
48. 21/01/2019 48Aravinda K., Dept. of E&C, NHCE
“always” blocks using event control statements
When sensitivity list is not specified or not
required, event control statements such as
“wait” can be used.
In contrast, when wait statements are
included, the always block cannot have
sensitivity list.
The wait statement is used as a level-
sensitive event control. It can also be used
to handshake between two processes.
49. 21/01/2019 49Aravinda K., Dept. of E&C, NHCE
1. (a) It will compile, but will not simulate correctly because, the
“carry” statement has no dependency on “add” signal.
2. (d) It will not compile because, when compiler gets to “else”, it
does not find the corresponding “if” before.
Note: Both codes can be corrected by adding “begin” and “end”.
1 2
(a) It will compile, but will not simulate correctly.
(b) It will compile and simulate, but will not synthesize correctly.
(c) It will work correctly both in simulation and synthesis.
(d) It will not get compiled at all.
50. 21/01/2019 50Aravinda K., Dept. of E&C, NHCE
Verilog data types
Net Variable
Keywords
wire (connections)
tri (tristate)
wand (wired and)
wor (wired or)
Keywords
reg (register)
time (stores timing)
integer (without point)
real (floating point)
realtime (fractional time)
51. 21/01/2019 Aravinda K., Dept. of E&C, NHCE 51
wand and wor indicate that the net is being driven by more inputs;
the synthesis tool automatically generates the respective gates.
module p1(x,y,z);
input x,y;
output z;
wor p;
assign p=x&y;
assign p=~x&~y;
assign z=p;
endmodule
module p2(x,y,z);
input x,y;
output z;
wire p;
assign p=x&y;
assign p=~x&~y;
assign z=p;
endmodule
module p3(x,y,z);
input x,y:
output z;
wire p,q ;
assign p=x&y;
assign q=~x&~y;
assign z=p|q;
endmodule
WRONG CODE GENERAL CODE
52. 21/01/2019 52Aravinda K., Dept. of E&C, NHCE
Verilog operators
Unary Arithmetic
+ plus
- minus
! logical negation
~ bitwise negation
& reduction AND
| reduction OR
^ reduction XOR
Relational and shift
+ add
- subtract
* multiply
/ divide
% modulus
** exponent
< less than
> greater than
<= less than or equal
>= greater than or equal
<< logical left shift
>> logical right shift
<<< arithmetic left shift
>>> arithmetic right shift
53. 21/01/2019 53Aravinda K., Dept. of E&C, NHCE
Verilog operators contd…
Logical Bitwise
== equality
!= inequality
=== case equality
!== case inequality
&& logical AND
|| logical OR
Other
& AND
| OR
^ XOR
^~ ~^ equal
?: conditional
{} concatenation
{{}} replication
55. 21/01/2019 55Aravinda K., Dept. of E&C, NHCE
Expression Operation Result
C >> 2 Shift right by 2 places 000110
C >> 2 & D Bitwise AND 000010
~ B Bitwise INVERT 000
{A, ~B} Concatenate 110000
({A, ~B}) | (C >> 2 & D) Bitwise OR 110010
(({A, ~B}) | (C >> 2 & D)) & D Bitwise AND 110010
(({A, ~B}) | (C >> 2 & D)) & D ==
110010
Equality check TRUE
Example: A = 110, B = 111, C = 011000, D = 111011
56. 21/01/2019 56Aravinda K., Dept. of E&C, NHCE
Unary reduction reduces a vector into a single bit.
When parentheses are not used, “Unary” operators have the
highest precedence and “Other” operators have the lowest
precedence, in the class in which the operators are listed.
Operators belonging to the same class have same precedence,
and are applied from left to right in an expression.
& &&
Operates on Boolean type as
well as on binary data
Operates only on the Boolean
data type (TRUE or FALSE)
Evaluates both sides of the
expression
Evaluates only the LHS of the
expression
When A = 5, B = 4, C = 3, then
(A>=B) && (B<=C) yields (1) && (0) yields (0).
57. 21/01/2019 57Aravinda K., Dept. of E&C, NHCE
Expression Operation Result
A >> 4 Logical right shift 00001010
A >>> 4 Arithmetic right shift 11111010
A << 4 Logical left shift 01010000
A <<< 4 Arithmetic left shift 01010000
reg signed [7:0] A = 8’hA5;
(A = 10100101)
Expression Operation Result
B >> 4 Logical right shift 00001010
B >>> 4 Arithmetic right shift 00001010
B << 4 Logical left shift 01010000
B <<< 4 Arithmetic left shift 01010000
reg [7:0] B = 8’hA5;
(B = 10100101)
58. 21/01/2019 58Aravinda K., Dept. of E&C, NHCE
Expression Operation Result
A >> 4 Logical right shift 00001010
A >>> 4 Arithmetic right shift 00001010
A << 4 Logical left shift 01010000
A <<< 4 Arithmetic left shift 01010000
integer signed A = 8’hA5;
(A = 00000000000000000000000010100101)
integer A = 8’shA5;
(A = 11111111111111111111111110100101)
Expression Operation Result
A >> 4 Logical right shift 11111010
A >>> 4 Arithmetic right shift 11111010
A << 4 Logical left shift 01010000
A <<< 4 Arithmetic left shift 01010000
59. 21/01/2019 59Aravinda K., Dept. of E&C, NHCE
Verilog models for Multiplexers
The expression for the output is,
F = A’I0+AI1
60. 21/01/2019 60Aravinda K., Dept. of E&C, NHCE
The expression for the output is,
F = A’B’I0+A’BI1+AB’I2+ABI3
Code with the procedural assignment, using the “case” statement
Code with the continuous statement
61. 21/01/2019 61Aravinda K., Dept. of E&C, NHCE
Code with the procedural assignment, using the “if” statement
Important coding practices while writing synthesizable Verilog:
1. Whenever possible, use concurrent assignments to design
the combinational logic.
2. Whenever procedural assignments are used for the
combinational logic, use blocking assignments.
3. Use “always @(*)”, to avoid accidental omissions of inputs
in the sensitivity list.
63. 21/01/2019 63Aravinda K., Dept. of E&C, NHCE
Concurrent Blocking Non-blocking
assign y = a & b; y = a & b; y <= a & b;
Assignment is
immediate
Assignment is
immediate
Assignment is
parallel
Suitable for
combinational logic
Suitable for
combinational logic
Suitable for
sequential logic
Order of the
statements is not
important
Order of the
statements is
important
Order of the
statements is not
important
64. 21/01/2019 64Aravinda K., Dept. of E&C, NHCE
Synthesis output: A 3-bit shift
register, with serial input A,
and outputs Q1, Q2, Q3.
Synthesis output: A single flip-
flop, with input A, and a single
output Q3.
65. 21/01/2019 65Aravinda K., Dept. of E&C, NHCE
1. Register with
synchronous
“clear” and “load”
2. Register with “left
shift” operation and
concatenation
66. 21/01/2019 66Aravinda K., Dept. of E&C, NHCE
3. Synchronous
counter
4. Standard synchronous
counter, 74163
67. 21/01/2019 67Aravinda K., Dept. of E&C, NHCE
P is “enable” signal and T is “carry connection” signal. “clear” overrides
“load” and “count” functions, and “load” overrides “count” function.
68. 21/01/2019 68Aravinda K., Dept. of E&C, NHCE
This is a structural
modeling, which
interconnects the
previous defined
modules. c74163
is component’s
name; ct1, ct2 are
instance names.
5. Cascading of
74163, to get
8-bit counter
69. 21/01/2019 69Aravinda K., Dept. of E&C, NHCE
Synthesis of “Left
shift” register
Verilog cannot synthesize delays.
Similarly, “initial” blocks are
ignored by the synthesis tools.
70. 21/01/2019 70Aravinda K., Dept. of E&C, NHCE
This code is meant for a
combinational circuit, but
creates an additional latch
to hold the value of F, when
Sel changes to 2’b11. This
latch creates timing issues.
The additional latch can be
avoided, if all possible cases
of the inputs are included.
When all possible execution
paths are covered, holding a
value is not necessary.
The additional latch can also
be avoided, by initializing
the combinational output in
the beginning of “always”
block. In this way, holding a
value becomes unnecessary.
71. 21/01/2019 71Aravinda K., Dept. of E&C, NHCE
Important coding practices while writing synthesizable Verilog:
4. Use an edge-triggered clock in the sensitivity list (using the
“posedge” or “negedge” keywords).
5. Should not make assignments to the same variable, in
more than one “always” block.
6. Unwanted latches can be avoided, by means of –
i) including “else” clauses for “if” statements. ii) specifying
all cases for “case” statements, or having a “default” clause
at the end. iii) initializing the combinational outputs at the
beginning of the “always” block.
72. 21/01/2019 72Aravinda K., Dept. of E&C, NHCE
Behavioral and Structural Verilog
Any circuit can be represented in multiple forms
of abstraction; e.g., different designers think of
NAND gate in different representations. In the
same way, the function F = AB + BC can be
described in two different ways:
73. 21/01/2019 73Aravinda K., Dept. of E&C, NHCE
Behavioral
models
Data flow (RTL)
models
Structural
models
These models describe the system
at a higher level of abstraction,
without implying any particular
structure or technology. (e.g., full
adder’s truth table description)
These models describe the system
at a lower level of abstraction, by
means of components and their
interconnections. (e.g., full adder in
terms of half adders)
These models describe the system
at an intermediate level, called as
Register Transfer Language. (e.g.:
full adder’s algebraic expressions)
74. EXAMPLE: SEQUENCE DETECTOR THAT DETECTS “101”
Modeling a sequential machine
21/01/2019 Aravinda K., Dept. of E&C, NHCE 74
77. 21/01/2019 77Aravinda K., Dept. of E&C, NHCE
Behavioral modeling for a Mealy sequential circuit
State table
An example is the state machine of a
BCD to excess-3 code converter, which
can be designed in four different ways:
1. Behavioral: with two “always” blocks
2. Behavioral: with one “always” block
3. Data flow: with combinational logic
4. Structural: with combinational logic
78. 21/01/2019 78Aravinda K., Dept. of E&C, NHCE
1. With two “always” blocks:
i) One for combinational part
ii) Other for state register
79. 21/01/2019 79Aravinda K., Dept. of E&C, NHCE
2. With one “always” block
When compared to this
model, the earlier one is
better because,
it corresponds more
closely to the hardware
implementation.
80. 21/01/2019 80Aravinda K., Dept. of E&C, NHCE
3. With combinational logic
(data flow model)
This model
requires
state
assignments,
and the
derivation of
the next
state
equations.
81. 21/01/2019 81Aravinda K., Dept. of E&C, NHCE
4. With combinational logic
(structural model)
This model exactly corresponds to
the hardware that was intended,
but requires more effort to
produce. Hence, to have quicker
“time-to-market”, designers often
use behavioral model.