The document discusses the history and evolution of VLSI and VHDL, focusing on the invention of transistors and integrated circuits, advancements in silicon technology, and enhancing design approaches to meet market demands. It highlights the importance of VHDL in modeling digital systems, facilitating design specifications, testing, and simulation, as well as various coding and architecture styles in VHDL. Additionally, it emphasizes cost reduction strategies and design optimization for high-performance integrated circuits.

1. THE WORLD OF VLSI
&
VHDL
Yesterday, Today
&
Tomorrow

2. The World of VLSI
• History of the Integrated Circuit (IC) design
• The IC Technologies

3.  History of the IC designIn 1947 Transistor was
invented & demonstrated @ Bell Labs
 The first IC appeared in the market in 1961
 ~14 years after the transistorFlip-flop:
 2 transistors & resistorsCost
 ~$100
• The Silicon Technology is Growing...
• Now on the same amount of Silica
 ~500 times
 faster operations 10 million transistors,
 1/2 mile of interconnectCost few cents!!!
 The Technology changes compared to the
IC Design cycle

4. Moore’s Law
 In 1965, GardonMoore stated that the silicon
technology will double the number of transistors
on a chip every 2 years!!!
 And it is happening !!!!!!

5. The Search of products
 “How to reduce the high designing cost for
future success of this technology ??? ”:
 1968 Noyce
 Reduce the cost of design process
 Find product with large market-Regular structure,
Many applications
1968 :Noyce, Moore & Grove Forms Intel
!!SemiconductorMemory Chip

6. Microprocessor Technology
 Microprocessor = IC Tech +SoftwareProcessor
 Power+Memory capacity Software market

10. Advantages of VLSI ?
 Less AREA (compactness at system levels)
 Less POWERConsumption
 Less TESTING(more complex testing)
 Higher RELIABILITY
(due to improved on-chip interconnects)
 Higher SPEED(due to reduced interconnect
length)
 Significant COST SAVINGS

11. The goal of the IC designer
 Meet the market requirements
 Satisfying customers need
 Beating the competition
 Increasing performance or functionality of the product
Reducing cost compared to the available solutions
 Achieved by:
 Using next generation Silicon technologies
 New design concepts & tools
 High level of integration
 The Design is an optimization problem with
parameters as Technology, Time, Cost and Customer
requirements

12. Design Approaches
 Custom
 full control of design
 best results, slowest design time.
 Semi-custom (std cell)
 use Cell libraries from vendor
 cad tools, faster design time
 EPLA/EPLD -FPGA
 Electrically Programmable (in the Field)

13. ASIC(Application Specific Integrated Circuit)
 Implements custom functions according to description
 Not off-the-shelf
 Can be described in HDL (Verilog,VHDL)
 in an abstract technology Independent fashion
 Verified using a simulator
 Analogous to software debugger
 Constructed out of logical function cells
 (AND,OR) and Re-Usable Macro
 Building blocks (ADDERs, REGISTERs)
 Mapped or translated using Synthesis products
Implemented in
 Field Programmable, Standard Cell or Gate Array families
 For high volume production
 Designers pay CAD vendors ~$50K -$500K for Design tools
 Designer pay foundry( ~ $200K -.5M) and per part agreement

14. Field Programmable Gate Array
 A chip that can be configured by a user to
implement different digital logic circuits
 Invented in 1984
 FPGA building blocks:
 Programmable logic blocks
 Programmable interconnectField

17. To compress the digital world.
To explore the hidden perfection and create
the brain of a machine.
*The above two are considered as a very difficult
tasks in the field of electronics engineering, where
in fact it’s a very simple technology.

18.  VHDL is for coding models of a digital system.
 Reasons for modeling:
◦ Requirements specification
◦ Documentation
◦ Testing using simulation
◦ Formal verification
◦ Synthesis
 Goal:
◦ Most ‘reliable’ design process, with minimum cost
and time
◦ Avoid design errors!

19.  VHDL is a programming language that allows one
to model and develop complex digital systems in a
dynamic environment.
 Object Oriented methodology for you C people
can be observed -- modules can be used and
reused.
 Allows you to designate in/out ports (bits) and
specify behavior or response of the system.

20.  C is procedural language whereas VHDL is semi
concurrent & semi sequential language.
 C is Case Sensitive whereas VHDL is case
insensitive.
 There are some similarities, as with any
programming language, but syntax and logic are
quite different.

21. • Interfaces (PORTS)
• Behavior
• Structure
• Test Benches
• Simulation
• Synthesis

22. Dataflow
Behavioral
Structural
Kind of BORING sounding huh??
Well, it gets more exciting with the details !!
:)

23. Uses statements that defines the actual
flow of data.....
such as,
x <= y -- this is NOT less than equal to
-- told you its not C
this assigns the Boolean signal x to the value of Boolean
signal y... i.e. x = y
this will occur whenever y changes....

24. Entity declaration…
(Describes the input/output ports of a module)
entity name port names port mode (direction)
entity reg4 is
port ( d0, d1, d2, d3, en, clk : in bit;
q0, q1, q2, q3 : out bit );
end entity reg4;
punctuation
port type
reserved words

25.  Architecture body
 Describes an implementation of an entity
 May be several per entity
 Behavioral architecture
 Describes the algorithm performed by the module
 Contains
Process statements, each containing
 Sequential statements, including
Signal assignment statements and
Wait statements

26.  Omit entity at end of entity declaration.
 Omit architecture at end of architecture body.
 Omit is in process statement header.
entity reg4 is architecture behav of reg4 is
port ( d0, d1, d2 : in bit begin
d3, en, clk : in bit; process (d0, ... )
q0, q1, q2, q3 : out bit ...
); begin
end reg4; ...
end process ;
end behav;

27.  Structural architecture
 implements the module as a composition of
subsystems
 contains
○ signal declarations, for internal interconnections
 the entity ports are also treated as signals
○ component instances
 instances of previously declared entity/architecture
pairs
○ port maps in component instances
 connect signals to component ports

28.  An architecture can contain both behavioral
and structural parts
 Process statements and component instances
○ Collectively called concurrent statements
 Processes can read and assign to signals
 Example: register-transfer-level (RTL) model
 Data path described structurally
 Control section described behaviorally

29. multiplier multiplicand
shift_reg
control_ shift_
section adder
reg
product

30.  Testing a design by simulation
 Use a test bench model
 A model that uses your model
 Apply test sequences to your inputs
 Monitors values on output signals
 Either using simulator.
 Or with a process that verifies correct operation
 Or logic analyzer.

31.  Discrete event simulation
 Time advances in discrete steps.
 When signal values change—events occur.
 A processes is sensitive to events on input
signals
 Specified in wait statements.
 Resumes and schedules new values on output
signals.
○ Schedules transactions.
○ Event on a signal if value changes.

32. Initial Design Entry VHDL, Schematic, State
Diagram
Optimize Boolean Expression
into a standard form
Logic Optimization - To optimize area or speed
Minimized Blocks
Technology Mapping - To minimize area
Where the logic block is placed
Placement ?
- With optimum routing wire
Connection between cells
Routing - To minimize area.
Used to configure the final
Programming Unit circuit

35.  Implement the VHDL portion of coding for synthesis.
 Identify the differences between behavioral and
structural coding styles.
 Distinguish coding for synthesis versus coding for
simulation.
 Use scalar and composite data types to represent
information.
 Use concurrent and sequential control structure to
regulate information flow.
 Implement common VHDL constructs (Finite State
Machines [FSMs], RAM/ROM data structures).

36. • Executable specification.
• Functionality separated from implementation.
• Simulate early and fast (Manage complexity)
• Explore design alternatives.
• Get feedback (Produce better designs)
• Automatic synthesis and test generation (ATPG for
ASICs)
• Increase productivity (Shorten time-to-market)
• Technology and tool independence.
• Portable design data (Protect investment)

37.  Digital Signal Processing.
 IC Testing & Analysis.
 FPGA Design Verification.
 FPGA Development.
 Hardware Design.
 IC designing.
 ASIC Development.

38. • THANK YOU
E-Mail
Gaurav_rai@live.com
•