Introduction to VHDL - Part 1


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Lecture 10

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  • For additional information, contact any of the following individuals: Dan Solarek Professor and Chairman [email_address] [email_address] Voice: 419-530-3377 Allen Rioux Director of Online Services [email_address] [email_address] Voice: 419-530-3377 To leave a message for any of these individuals call the department secretary at 419-530-3159. You may send a FAX to 419-530-3068 Richard Springman Director of Student Services [email_address] [email_address] Voice: 419-530-3276 Myrna Swanberg Academic Program Coordinator [email_address] [email_address] Voice: 419-530-3062
  • Introduction to VHDL - Part 1

    1. 1. Introduction to VHDL An Overview EET 3350 Digital Systems Design Dan Solarek
    2. 2. What is VHDL? VHDL = VHSIC Hardware Description Language where VHSIC = Very High Speed Integrated Circuit A technology independent, standard language for: hardware description simulation synthesis 2
    3. 3. What is VHDL? VHDL is a programming language that has been designed and optimized for describing the behavior of digital systems. Syntax is similar to C (actually, more like Ada) It is highly typed – includes a rich set of data types Allows concurrent processing Not a general purpose programming language 3
    4. 4. History of VHDL Development Outgrowth of the DARPA VHSIC Program Vendors designing large chips needed to exchange data describing their designs IBM, Texas Instruments, and Intermetrics got the contract in 1983 and released VHDL 7.2 in 1985 Released to the IEEE for standardization in 1986 Became IEEE Std 1076-1987 Reballoted/upgraded to IEEE Std 1076-1993 Released IEEE Std 1164-1993, STD_LOGIC_1164 9-valued logic definition, math functions for std_logic 4
    5. 5. Why VHDL?It is a Standard Data Exchange medium between Vendors Communications medium between CAD Tools Not Proprietary Promotes interoperability and design re-useNot technology-specificHuman-ReadableCan be used to describe the behavior of a design, or tosynthesize the design itselfSupports a wide range of abstraction levels Can model a system, board, chip, register-transfer-level (RTL), or gate level designs 5
    6. 6. VHDL Features Supports Hierarchy Flexible design methodology: Top-down, bottom-up, or both Has elements to make large-scale design easier e.g., components, functions, procedures, packages, configuration Supports three types of modeling styles: Behavioral (sequential statement model [like a program]) Dataflow (concurrent statement modeling) or mixed Structural (for connecting components) Test Benches can be written in the same language circuits can be verified by simulation before synthesis Propagation delays, min-max delays, setup and hold timing, timing constraints, etc. can all be described naturally 6
    7. 7. Basic Hardware Design Flow 7
    8. 8. Steps in VHDL-based design flowFront-end Block Comp- Simu- steps Coding diagram ilation lation Very Painful, but not uncommon painfulBack-end Syn- Timing / Fitting steps thesis verification 8
    9. 9. VHDL Design Flow1. Hierarchical / block diagram Figuring out the basic approach and building blocks at the block-diagram level. Large logic designs are usually hierarchical, and VHDL gives you a good framework for defining modules and their interfaces and filling in the details later.2. Coding Actual writing of VHDL code for modules, their interfaces, and their internal details. 9
    10. 10. Design Flow3. Compilation Analyses your code for syntax errors and checks it for compatibility with other modules on which it relies. Compilation also creates the internal information that is needed for simulation.4. Simulation A VHDL simulator allows you to define and apply inputs to your design, and to observe its outputs. Simulation is part of a larger step called verification. A functional verification is performed to verify that the circuit’s logical operation works as desired independent of timing considerations and gate delays. 10
    11. 11. Design Flow5. Synthesis Converting the VHDL description into a set of primitives or components that can be assembled in the target technology. For example, with PLDs or CPLDs, the synthesis tool may generate two-level sum-of products equations. With ASICs, it may generate a netlist that specifies how the gates should be interconnected.6. Fitting / Placement & Routing Maps the synthesized components onto physical devices. 11
    12. 12. Design Flow7. Timing verification At this stage, the actual circuit delays due to wire lengths, electrical loading, and other factors are known, so precise timing simulation can be performed. Study the circuit’s operation including estimated delays, and verify that the setup, hold, and other timing requirements for sequential devices (like flip-flops) are met. 12