This document discusses the Hardware Description Language (HDL) VHDL. It provides an overview of VHDL, including that it is used to describe and simulate digital circuits, and is an IEEE standard. The key elements of VHDL are then described - entities define input/output ports, architectures describe how the circuit operates, and configurations define how designs are linked together. Examples of each element are provided. Finally, it briefly discusses VHDL modeling styles and objects like constants, variables, and signals.

1. K.S.R College Of Engineering
Department - Computer Science and Engineering
Subject - Digital principles and computer design
Subject code - 20EE231
Name - Varsha.S.K
Register no. - 73152213101
Semester - 02
Section - CSE-’B’
Date - 11.07.2023

2. Hardware Description Language (HDL)
• HDL stands for Hardware Description Language.
• It is a programming language that is used to describe, simulate, and
create hardware like digital circuits (ICS).
• HDL is mainly used to discover the faults in the design before
implementing it in the hardware.
• The main advantage of HDLs is that it provides flexible modeling
capabilities can express the large complex designs (>107gates).
• Today, there are many HDLs available in the market, but VHDL and
Verilog are the most popular HDLs.

3. VHDL(Very High-Speed Integration Circuit HDL
(Hardware Description Language))
• VHDL stands for Very High-Speed Integration Circuit HDL (Hardware
Description Language).
• It is an IEEE (Institute of Electrical and Electronics Engineers)
standard hardware description language that is used to describe and
simulate the behavior of complex digital circuits.
• The most popular examples of VHDL are Odd Parity Generator, Pulse
Generator, Priority Encoder, Behavioral Model for 16 words, 8bit
RAM, etc.

4. Advantages of VHDL
• It supports various design methodologies like Top-down approach and
Bottom-up approach.
• It provides a flexible design language.
• It allows better design management.
• It allows detailed implementations.
• It supports a multi-level abstraction.

5. Disadvantages of VHDL:
• It requires specific knowledge of the structure and syntax of the
language.
• It is more difficult to visualize and troubleshoot a design.
• Some VHDL programs cannot be synthesized.
• VHDL is more difficult to learn.

6. Basic Elements of VHDL
• These are the following three basic elements of VHDL:
1) Entity
2) Architecture
3) Configuration

7. Entity:
• The Entity is used to specify the input and output ports of the circuit.
An Entity usually has one or more ports that can be inputs (in),
outputs (out), input-outputs (inout), or buffer.
• An Entity may also include a set of generic values that are used to
declare properties of the circuit.

8. Entity Declaration:
•Simplified syntax:
Entity entity_name is
ort (
port_1_name : mode data_type;
ort_2_name : mode data_type;
.......
Port_n_name : mode data_type
);
end entity_name;

9. • Example:
entity orgate is
port (
a : in std_logic;
b : in std_logic;
c : out std_logic
);
end orgate;

10. Using generic:
Syntax:
entity entity_name is
generic (
generic_1_name : data_type;
generic_2_name : data_type;
........
Generic_n_name : data_type
);
port (
port_1_name : mode data_type;
port_2_name : mode data_type;
........
Port_n_name : mode data_type
);
end entity_name;

11. Example:
entity Logic_Gates is
generic (Delay : Time := 10ns);
port (
Input1 : in std_logic;
Input2 : in std_logic;
Output : out std_logic
);
end Logic_Gates;

12. Architecture:
• Architecture is the actual description of the design, which is used to
describe how the circuit operates. It can contain both concurrent and
sequential statements.

13. Architecture Declaration:
Syntax:
Architecture architecture_name of
entity_name is
begin
(concurrent statements )
end architecture_name;

14. Example:
Architecture synthesis of andgate is
begin
c <= a AND b;
end synthesis;

15. Configuration:
• A Configuration defines how the design hierarchy is linked together. It
is also used to associate architecture with an entity.

16. Configuration Declaration:
Syntax:
configuration configuration_name of entity_name is
--configuration declarations
for architecture_name
for instance_label : component_name
use entity library_name.entity_name(architecture_name);
end for;
--
end for;
end [configuration] [configuration_name];

17. Example:
configuration demo_config of even_detector_testbench is
for tb_archi
for uut : even_detector
use entity work.even_detector (sop_archi);
end for;
end for;
end demo_config;

18. Types of Modeling styles in VHDL:
1.Data flow modeling (Design Equations)
2.Behavioral modeling (Explains Behaviour)
3.Structural modeling (Connection of sub modules)

19. VHDL objects:
• VHDL uses the following three types of objects:
1)Constant:
•Constant is an object which can only hold a single value that
cannot be changed during the whole code.
Example:
constant number_of_bytes integer:=8;

20. 2)Variables:
•A variable also holds a single value of a given type. The value of
the variable may be changed during the simulation by using variable
assignment operator.
• Variables are used in the processes and subprograms.
•Variables are assigned by the assignment operator “:=“.
Example:
variable index: integer :=0;

21. 3) Signals:
•Signals can be declared in architecture and used anywhere
within the architecture. Signals are assigned by the assignment
operator “<=“.
Example:
Signal sig1: std_logic;
Sig1 <= ‘1’

22. Thank you...!