Analog Electronic Circuits - Module 3

MODULE 3
BJT & JFET
FREQUENCY RESPONSE
ANALOG ELECTRONIC CIRCUITS
(ECE34)

FREQUENCY RESPONSE
OF AN AMPLIFIER
• It is the graph of the gain
v/s frequency.
• At low frequencies, the
decrease in voltage gain
is due to the external
discrete capacitors.
• At high frequencies, the
decrease in voltage gain
is due to the internal
device capacitances.
• The external wiring shunt
capacitance also affects
the high frequency gain.
Aravinda K., Dept. of E&C, NHCE 202/10/2017

• f1 and f2 are called as lower and upper cutoff
frequencies. They are also called as half-power
frequencies.
• This is because, they are marked on the gain curve
at 0.707 of Av(max), which is equal to 0.5 of
Ap(max).
• The midband of an amplifier is defined as the range
of frequencies between 10f1 and 0.1f2.
• The voltage gain at the outside of the midband can
be obtained as –

• Direct coupled amplifier is called as dc amplifier,
as it can amplify dc signals.
• As the coupling capacitor is absent, there is no
lower cutoff frequency.
• Op amp is a dc amplifier, with high voltage gain,
high i/p impedance and low o/p impedance.

Gain in Decibel
Aravinda K., Dept. of E&C, NHCE 5
Factor Decibel, dB
X1 0
X2 +3
X4 +6
X8 +9
X10 +10
X0.5 -3
X0.1 -10
Factor Decibel, dB
X1 0
X2 +6
X4 +12
X8 +18
X10 +20
X0.5 -6
X0.1 -20
02/10/2017

Cascaded stages
Example: If AV1 = 100 and AV2 = 200, then AVT = 20,000.
AVT (dB) = 20 log (20,000) = 86.
Now, AV1 (dB) = 20 log (100) = 40, and AV2 (dB) =
20 log (200) = 46. Hence, AVT (dB) = 40 + 46 = 86.
02/10/2017

Impedance matching
Communication system Characteristic impedance (Z0)
Microwave system 50 Ω
Coaxial cable 75 Ω
Twin-lead 300 Ω
Telephone system 600 Ω
02/10/2017

Maximum power gets transferred when source and
load impedances are of same value.
When all impedances are matched, the decibel power
gain equals the decibel voltage gain.
02/10/2017

Exercise - 1
Find the total Ap and Av, and the individual voltage gains.
Solution: Net decibel gain = 23 + 36 + 31 = 90 dB. Hence,
Ap = Antilog (90/10) = 1,000,000,000. Av = Antilog (90/20) =
31,623. Now, AV1 = Antilog (23/20) = 14.1, AV2 = Antilog
(36/20) = 63.1, AV3 = Antilog (31/20) = 35.5

Milliwatt and Volt reference
Power P in dBm
1 W +30
100 mW +20
10 mW +10
1 mW 0
100 μW -10
10 μW -20
1 μW -30
Voltage V in dBV
1 V 0
100 mV -20
10 mV -40
1 mV -60
100 μV -80
10 μV -100
1 μV -120
02/10/2017

Exercise - 2
An amplifier rated at
50W o/p is connected
to an 8 ohms speaker.
Its power gain is 30 dB
and voltage gain 42 dB.
Find the input power,
input voltage and
impedance required
for the rated output.
i) Pi = 50 / Antilog (3)
= 50 mW.
ii) Vo = sqrt (50X8) = 20V.
Vi = 20 / Antilog (2.1)
= 159 mV.
iii) Ri = sqr (159mV) / 50 mW
= 0.51 ohms
02/10/2017

Bode Plots
• Octave refers to double the frequency, and Decade
refers to ten times the frequency.
• When we plot the graph of frequency versus gain,
the linear scale is not suitable because, we require
X-axis to contain octaves as well as decades.
• Therefore, semilog graph sheet is used where X-axis
is compressed. Such plot is called as “Bode plot”.

Example: If the point marked is ¼” away from 102
line, and if the distance between 102 and 103 lines
is ¾”, then the value is, 102X10(¼/¾) = 10(7/3) = 215.
02/10/2017

Before f1 & after f2, the dB gain decreases at 20 dB per
decade. This occurs due to either coupling capacitor or
bypass capacitor, whichever is dominant. Hence, the
“roll-off factor” for this amplifier is 20 dB/decade.
Practical
Bode
plot
Ideal
Bode
plot
02/10/2017

Human
Auditory
Response
• The human ear
responds to changes
in audio power
levels, in a common
logarithmic fashion.
• 0.2 nbar pressure
level corresponds to
the threshold of
hearing, which gets
mentioned as 0 dBs.

Name
with
respect
to
Sine wave Lag circuit Lead circuit
Square wave Integrating circuit Differentiating circuit
Frequency Low pass circuit High pass circuit
Amplifier Bypass circuit Coupling circuit
02/10/2017

with

Frequency analysis of BJT stage
• In a capacitor coupled
amplifier, it becomes
necessary to obtain the
theoretical values of the
cut-off frequencies,
before finalizing the
amplifier design.
• Now, for obtaining the
lower cut-off frequency,
it becomes necessary to
find out the dominant
capacitor for the
decreasing frequency,
out of the 3 capacitors.
02/10/2017

Input side Output side Emitter side
where
R = RG + Rin
where
R = RC + RL
Zout is that of
Emitter follower
02/10/2017

Exercise for obtaining f1
• For the input side,
= 1.78 KΩ; f1 = 190 Hz
• For the output side,
Hence, f1 = 5.32 Hz
• For the emitter side,
= 25.1 Ω; f1 = 635 Hz
From the mid-band, when we
move to lower frequency side,
the emitter bypass circuit has
larger value, & hence 635 Hz is
the lower cut-off frequency.
02/10/2017

Collector side Base side
where
R = RC || RL
C = Cc’ + Cstray
Obtaining the upper cut-off frequency
Cc’ is between collector & base;
Cstray is Wiring capacitance.
Cc’ needs to be converted into
its Miller components;
Ce’ is between base & emitter.
where
fT = Ai x BW
02/10/2017

• For the base side, given
Cc’ = 2.1 pF, fT = 300 MHz;
• For the collector side,
given Cstray = 10 pF;
For base side, f2 = 1.48 MHz.
For collector side, f2 = 4.96 MHz.
From mid-band, when we move
to higher frequency, base side
has lesser value. Hence, upper
cut-off frequency is 1.48 MHz.
02/10/2017

LOW FREQUENCY ANALYSIS
• For the input side,
• For the output side,
Therefore, from the mid-band,
when we move to the lower
frequency side, the dominant
low-frequency cut-off value is,
f1 = 13.8 Hz.
Frequency analysis of FET stage
02/10/2017

• The FET has 3 internal capacitances: Cgs, Cgd and Cds.
But these are difficult to measure, and therefore, the
manufacturers list the capacitances under short circuit
conditions. Hence, for the input, output and feedback
paths, the internal capacitances can be listed as,
Ciss = Cgs + Cgd, Coss = Cds + Cgd and Crss = Cgd
HIGH FREQUENCY ANALYSIS
02/10/2017

• By utilizing the data provided by the manufacturer,
the internal capacitances can be written as –
Cgd = Crss, Cgs = Ciss – Crss and Cds = Coss – Crss
• Using Cgd, the input and output Miller capacitances
can be written as –
Cin(M) = Cgd (Av+1) and Cout(M) = Cgd [(Av+1)/Av]
• The voltage gain for the common source amplifier is
given by –
Av = gm rd where rd = RD || RL

• Given Ciss = 60 pF, Coss = 25
pF, Crss = 5 pF, gm = 97 mS:
Answer: Cgd = 5 pF, Cgs = 60-5
= 55 pF, Cds = 25-5 = 20 pF.
• For the gate side,
• For the drain side,
For gate side, f2 = 2.2 MHz. For
drain side, f2 = 48 MHz. Hence,
from mid-band, when we move
to the higher frequency side, the
dominant high-frequency cut-off
value is 2.2 MHz.
02/10/2017

END
OF
MODULE 3

Analog Electronic Circuits - Module 3

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Analog Electronic Circuits - Module 3