Submit Search
Upload
Survey On Two-Term Dot Product Of Multiplier Using Floating Point
•
0 likes
•
35 views
IRJET Journal
Follow
https://irjet.net/archives/V4/i1/IRJET-V4I172.pdf
Read less
Read more
Engineering
Report
Share
Report
Share
1 of 6
Download now
Download to read offline
Recommended
Area and power performance analysis of floating point ALU using pipelining
Area and power performance analysis of floating point ALU using pipelining
IRJET Journal
Floating point arithmetic operations (1)
Floating point arithmetic operations (1)
cs19club
Unit 3.1
Unit 3.1
Kiran Bagale
Python PCEP Logic Bit Operations
Python PCEP Logic Bit Operations
IHTMINSTITUTE
Topic 1.2
Topic 1.2
Sue Whale
Operations Research
Operations Research
Muthulakshmilakshmi2
Operation Research
Operation Research
SwathiSundari
Operation reasearch
Operation reasearch
Muthulakshmilakshmi2
Recommended
Area and power performance analysis of floating point ALU using pipelining
Area and power performance analysis of floating point ALU using pipelining
IRJET Journal
Floating point arithmetic operations (1)
Floating point arithmetic operations (1)
cs19club
Unit 3.1
Unit 3.1
Kiran Bagale
Python PCEP Logic Bit Operations
Python PCEP Logic Bit Operations
IHTMINSTITUTE
Topic 1.2
Topic 1.2
Sue Whale
Operations Research
Operations Research
Muthulakshmilakshmi2
Operation Research
Operation Research
SwathiSundari
Operation reasearch
Operation reasearch
Muthulakshmilakshmi2
Computer paper 3 may june 2004 9691 cambridge General Certificate of educatio...
Computer paper 3 may june 2004 9691 cambridge General Certificate of educatio...
Alpro
Performance of uncorrupted pixel count decision based
Performance of uncorrupted pixel count decision based
eSAT Publishing House
IRJET- An Efficient Multiply Accumulate Unit Design using Vedic Mathematics A...
IRJET- An Efficient Multiply Accumulate Unit Design using Vedic Mathematics A...
IRJET Journal
Topic 4.2
Topic 4.2
Sue Whale
Topic 4.1
Topic 4.1
Sue Whale
Basics of Digital Electronics
Basics of Digital Electronics
International Institute of Information Technology (I²IT)
Topic 2
Topic 2
Sue Whale
Quantitative Analysis For Decision Making
Quantitative Analysis For Decision Making
aminsand
Arithmetic
Arithmetic
Michael Gordon
Assignment problem
Assignment problem
Anggy Herny Anggraeni
Assignment method
Assignment method
R A Shah
Lesson 33: The Assignment Problem
Lesson 33: The Assignment Problem
Matthew Leingang
Design and Simulation of Radix-8 Booth Encoder Multiplier for Signed and Unsi...
Design and Simulation of Radix-8 Booth Encoder Multiplier for Signed and Unsi...
ijsrd.com
Topic 1.4
Topic 1.4
Sue Whale
Computer Architecture
Computer Architecture
Ravi Kumar
Topic 5.1
Topic 5.1
Sue Whale
Data representation
Data representation
Chew Hoong
Implementation of an Effective Self-Timed Multiplier for Single Precision Flo...
Implementation of an Effective Self-Timed Multiplier for Single Precision Flo...
IRJET Journal
Design of 32-bit Floating Point Unit for Advanced Processors
Design of 32-bit Floating Point Unit for Advanced Processors
IJERA Editor
DESIGN OF DOUBLE PRECISION FLOATING POINT MULTIPLICATION ALGORITHM WITH VECTO...
DESIGN OF DOUBLE PRECISION FLOATING POINT MULTIPLICATION ALGORITHM WITH VECTO...
jmicro
At36276280
At36276280
IJERA Editor
IRJET - Design of a Low Power Serial- Parallel Multiplier with Low Transition...
IRJET - Design of a Low Power Serial- Parallel Multiplier with Low Transition...
IRJET Journal
More Related Content
What's hot
Computer paper 3 may june 2004 9691 cambridge General Certificate of educatio...
Computer paper 3 may june 2004 9691 cambridge General Certificate of educatio...
Alpro
Performance of uncorrupted pixel count decision based
Performance of uncorrupted pixel count decision based
eSAT Publishing House
IRJET- An Efficient Multiply Accumulate Unit Design using Vedic Mathematics A...
IRJET- An Efficient Multiply Accumulate Unit Design using Vedic Mathematics A...
IRJET Journal
Topic 4.2
Topic 4.2
Sue Whale
Topic 4.1
Topic 4.1
Sue Whale
Basics of Digital Electronics
Basics of Digital Electronics
International Institute of Information Technology (I²IT)
Topic 2
Topic 2
Sue Whale
Quantitative Analysis For Decision Making
Quantitative Analysis For Decision Making
aminsand
Arithmetic
Arithmetic
Michael Gordon
Assignment problem
Assignment problem
Anggy Herny Anggraeni
Assignment method
Assignment method
R A Shah
Lesson 33: The Assignment Problem
Lesson 33: The Assignment Problem
Matthew Leingang
Design and Simulation of Radix-8 Booth Encoder Multiplier for Signed and Unsi...
Design and Simulation of Radix-8 Booth Encoder Multiplier for Signed and Unsi...
ijsrd.com
Topic 1.4
Topic 1.4
Sue Whale
Computer Architecture
Computer Architecture
Ravi Kumar
Topic 5.1
Topic 5.1
Sue Whale
Data representation
Data representation
Chew Hoong
What's hot
(17)
Computer paper 3 may june 2004 9691 cambridge General Certificate of educatio...
Computer paper 3 may june 2004 9691 cambridge General Certificate of educatio...
Performance of uncorrupted pixel count decision based
Performance of uncorrupted pixel count decision based
IRJET- An Efficient Multiply Accumulate Unit Design using Vedic Mathematics A...
IRJET- An Efficient Multiply Accumulate Unit Design using Vedic Mathematics A...
Topic 4.2
Topic 4.2
Topic 4.1
Topic 4.1
Basics of Digital Electronics
Basics of Digital Electronics
Topic 2
Topic 2
Quantitative Analysis For Decision Making
Quantitative Analysis For Decision Making
Arithmetic
Arithmetic
Assignment problem
Assignment problem
Assignment method
Assignment method
Lesson 33: The Assignment Problem
Lesson 33: The Assignment Problem
Design and Simulation of Radix-8 Booth Encoder Multiplier for Signed and Unsi...
Design and Simulation of Radix-8 Booth Encoder Multiplier for Signed and Unsi...
Topic 1.4
Topic 1.4
Computer Architecture
Computer Architecture
Topic 5.1
Topic 5.1
Data representation
Data representation
Similar to Survey On Two-Term Dot Product Of Multiplier Using Floating Point
Implementation of an Effective Self-Timed Multiplier for Single Precision Flo...
Implementation of an Effective Self-Timed Multiplier for Single Precision Flo...
IRJET Journal
Design of 32-bit Floating Point Unit for Advanced Processors
Design of 32-bit Floating Point Unit for Advanced Processors
IJERA Editor
DESIGN OF DOUBLE PRECISION FLOATING POINT MULTIPLICATION ALGORITHM WITH VECTO...
DESIGN OF DOUBLE PRECISION FLOATING POINT MULTIPLICATION ALGORITHM WITH VECTO...
jmicro
At36276280
At36276280
IJERA Editor
IRJET - Design of a Low Power Serial- Parallel Multiplier with Low Transition...
IRJET - Design of a Low Power Serial- Parallel Multiplier with Low Transition...
IRJET Journal
F044033742
F044033742
IJERA Editor
Ap32283286
Ap32283286
IJERA Editor
IRJET- Single Precision Floating Point Arithmetic using VHDL Coding
IRJET- Single Precision Floating Point Arithmetic using VHDL Coding
IRJET Journal
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...
IJERA Editor
Double Precision Floating Point Multiplier using Verilog
Double Precision Floating Point Multiplier using Verilog
IRJET Journal
Design and Analysis of High Performance Floating Point Arithmetic Unit
Design and Analysis of High Performance Floating Point Arithmetic Unit
ijtsrd
Design and Implementation of 8 Bit Multiplier Using M.G.D.I. Technique
Design and Implementation of 8 Bit Multiplier Using M.G.D.I. Technique
IJMER
Implementation and Simulation of Ieee 754 Single-Precision Floating Point Mul...
Implementation and Simulation of Ieee 754 Single-Precision Floating Point Mul...
inventionjournals
IRJET- Implementation of Floating Point FFT Processor with Single Precision f...
IRJET- Implementation of Floating Point FFT Processor with Single Precision f...
IRJET Journal
A High Speed Transposed Form FIR Filter Using Floating Point Dadda Multiplier
A High Speed Transposed Form FIR Filter Using Floating Point Dadda Multiplier
IJRES Journal
Jz2517611766
Jz2517611766
IJERA Editor
Jz2517611766
Jz2517611766
IJERA Editor
Design and Implementation of 8 Bit Multiplier Using M.G.D.I. Technique
Design and Implementation of 8 Bit Multiplier Using M.G.D.I. Technique
IJMER
IRJET - Design and Implementation of Double Precision FPU for Optimised Speed
IRJET - Design and Implementation of Double Precision FPU for Optimised Speed
IRJET Journal
IRJET- Efficient Design of Radix Booth Multiplier
IRJET- Efficient Design of Radix Booth Multiplier
IRJET Journal
Similar to Survey On Two-Term Dot Product Of Multiplier Using Floating Point
(20)
Implementation of an Effective Self-Timed Multiplier for Single Precision Flo...
Implementation of an Effective Self-Timed Multiplier for Single Precision Flo...
Design of 32-bit Floating Point Unit for Advanced Processors
Design of 32-bit Floating Point Unit for Advanced Processors
DESIGN OF DOUBLE PRECISION FLOATING POINT MULTIPLICATION ALGORITHM WITH VECTO...
DESIGN OF DOUBLE PRECISION FLOATING POINT MULTIPLICATION ALGORITHM WITH VECTO...
At36276280
At36276280
IRJET - Design of a Low Power Serial- Parallel Multiplier with Low Transition...
IRJET - Design of a Low Power Serial- Parallel Multiplier with Low Transition...
F044033742
F044033742
Ap32283286
Ap32283286
IRJET- Single Precision Floating Point Arithmetic using VHDL Coding
IRJET- Single Precision Floating Point Arithmetic using VHDL Coding
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...
Double Precision Floating Point Multiplier using Verilog
Double Precision Floating Point Multiplier using Verilog
Design and Analysis of High Performance Floating Point Arithmetic Unit
Design and Analysis of High Performance Floating Point Arithmetic Unit
Design and Implementation of 8 Bit Multiplier Using M.G.D.I. Technique
Design and Implementation of 8 Bit Multiplier Using M.G.D.I. Technique
Implementation and Simulation of Ieee 754 Single-Precision Floating Point Mul...
Implementation and Simulation of Ieee 754 Single-Precision Floating Point Mul...
IRJET- Implementation of Floating Point FFT Processor with Single Precision f...
IRJET- Implementation of Floating Point FFT Processor with Single Precision f...
A High Speed Transposed Form FIR Filter Using Floating Point Dadda Multiplier
A High Speed Transposed Form FIR Filter Using Floating Point Dadda Multiplier
Jz2517611766
Jz2517611766
Jz2517611766
Jz2517611766
Design and Implementation of 8 Bit Multiplier Using M.G.D.I. Technique
Design and Implementation of 8 Bit Multiplier Using M.G.D.I. Technique
IRJET - Design and Implementation of Double Precision FPU for Optimised Speed
IRJET - Design and Implementation of Double Precision FPU for Optimised Speed
IRJET- Efficient Design of Radix Booth Multiplier
IRJET- Efficient Design of Radix Booth Multiplier
More from IRJET Journal
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...
IRJET Journal
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTURE
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTURE
IRJET Journal
A COMPARATIVE ANALYSIS OF RCC ELEMENT OF SLAB WITH STARK STEEL (HYSD STEEL) A...
A COMPARATIVE ANALYSIS OF RCC ELEMENT OF SLAB WITH STARK STEEL (HYSD STEEL) A...
IRJET Journal
Effect of Camber and Angles of Attack on Airfoil Characteristics
Effect of Camber and Angles of Attack on Airfoil Characteristics
IRJET Journal
A Review on the Progress and Challenges of Aluminum-Based Metal Matrix Compos...
A Review on the Progress and Challenges of Aluminum-Based Metal Matrix Compos...
IRJET Journal
Dynamic Urban Transit Optimization: A Graph Neural Network Approach for Real-...
Dynamic Urban Transit Optimization: A Graph Neural Network Approach for Real-...
IRJET Journal
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...
IRJET Journal
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...
IRJET Journal
A REVIEW ON MACHINE LEARNING IN ADAS
A REVIEW ON MACHINE LEARNING IN ADAS
IRJET Journal
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...
IRJET Journal
P.E.B. Framed Structure Design and Analysis Using STAAD Pro
P.E.B. Framed Structure Design and Analysis Using STAAD Pro
IRJET Journal
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...
IRJET Journal
Survey Paper on Cloud-Based Secured Healthcare System
Survey Paper on Cloud-Based Secured Healthcare System
IRJET Journal
Review on studies and research on widening of existing concrete bridges
Review on studies and research on widening of existing concrete bridges
IRJET Journal
React based fullstack edtech web application
React based fullstack edtech web application
IRJET Journal
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...
IRJET Journal
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.
IRJET Journal
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...
IRJET Journal
Multistoried and Multi Bay Steel Building Frame by using Seismic Design
Multistoried and Multi Bay Steel Building Frame by using Seismic Design
IRJET Journal
Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...
Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...
IRJET Journal
More from IRJET Journal
(20)
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTURE
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTURE
A COMPARATIVE ANALYSIS OF RCC ELEMENT OF SLAB WITH STARK STEEL (HYSD STEEL) A...
A COMPARATIVE ANALYSIS OF RCC ELEMENT OF SLAB WITH STARK STEEL (HYSD STEEL) A...
Effect of Camber and Angles of Attack on Airfoil Characteristics
Effect of Camber and Angles of Attack on Airfoil Characteristics
A Review on the Progress and Challenges of Aluminum-Based Metal Matrix Compos...
A Review on the Progress and Challenges of Aluminum-Based Metal Matrix Compos...
Dynamic Urban Transit Optimization: A Graph Neural Network Approach for Real-...
Dynamic Urban Transit Optimization: A Graph Neural Network Approach for Real-...
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...
A REVIEW ON MACHINE LEARNING IN ADAS
A REVIEW ON MACHINE LEARNING IN ADAS
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...
P.E.B. Framed Structure Design and Analysis Using STAAD Pro
P.E.B. Framed Structure Design and Analysis Using STAAD Pro
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...
Survey Paper on Cloud-Based Secured Healthcare System
Survey Paper on Cloud-Based Secured Healthcare System
Review on studies and research on widening of existing concrete bridges
Review on studies and research on widening of existing concrete bridges
React based fullstack edtech web application
React based fullstack edtech web application
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...
Multistoried and Multi Bay Steel Building Frame by using Seismic Design
Multistoried and Multi Bay Steel Building Frame by using Seismic Design
Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...
Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...
Recently uploaded
Call Girls Service Nagpur Tanvi Call 7001035870 Meet With Nagpur Escorts
Call Girls Service Nagpur Tanvi Call 7001035870 Meet With Nagpur Escorts
Call Girls in Nagpur High Profile
SPICE PARK APR2024 ( 6,793 SPICE Models )
SPICE PARK APR2024 ( 6,793 SPICE Models )
Tsuyoshi Horigome
(RIA) Call Girls Bhosari ( 7001035870 ) HI-Fi Pune Escorts Service
(RIA) Call Girls Bhosari ( 7001035870 ) HI-Fi Pune Escorts Service
ranjana rawat
Roadmap to Membership of RICS - Pathways and Routes
Roadmap to Membership of RICS - Pathways and Routes
M Maged Hegazy, LLM, MBA, CCP, P3O
Introduction to Multiple Access Protocol.pptx
Introduction to Multiple Access Protocol.pptx
upamatechverse
(SHREYA) Chakan Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Esc...
(SHREYA) Chakan Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Esc...
ranjana rawat
UNIT-II FMM-Flow Through Circular Conduits
UNIT-II FMM-Flow Through Circular Conduits
rknatarajan
IMPLICATIONS OF THE ABOVE HOLISTIC UNDERSTANDING OF HARMONY ON PROFESSIONAL E...
IMPLICATIONS OF THE ABOVE HOLISTIC UNDERSTANDING OF HARMONY ON PROFESSIONAL E...
RajaP95
APPLICATIONS-AC/DC DRIVES-OPERATING CHARACTERISTICS
APPLICATIONS-AC/DC DRIVES-OPERATING CHARACTERISTICS
KurinjimalarL3
Call Girls Service Nashik Vaishnavi 7001305949 Independent Escort Service Nashik
Call Girls Service Nashik Vaishnavi 7001305949 Independent Escort Service Nashik
Call Girls in Nagpur High Profile
(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escorts
(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escorts
ranjana rawat
Processing & Properties of Floor and Wall Tiles.pptx
Processing & Properties of Floor and Wall Tiles.pptx
pranjaldaimarysona
result management system report for college project
result management system report for college project
Tonystark477637
HARDNESS, FRACTURE TOUGHNESS AND STRENGTH OF CERAMICS
HARDNESS, FRACTURE TOUGHNESS AND STRENGTH OF CERAMICS
RajkumarAkumalla
Top Rated Pune Call Girls Budhwar Peth ⟟ 6297143586 ⟟ Call Me For Genuine Se...
Top Rated Pune Call Girls Budhwar Peth ⟟ 6297143586 ⟟ Call Me For Genuine Se...
Call Girls in Nagpur High Profile
UNIT-V FMM.HYDRAULIC TURBINE - Construction and working
UNIT-V FMM.HYDRAULIC TURBINE - Construction and working
rknatarajan
High Profile Call Girls Nagpur Isha Call 7001035870 Meet With Nagpur Escorts
High Profile Call Girls Nagpur Isha Call 7001035870 Meet With Nagpur Escorts
ranjana rawat
247267395-1-Symmetric-and-distributed-shared-memory-architectures-ppt (1).ppt
247267395-1-Symmetric-and-distributed-shared-memory-architectures-ppt (1).ppt
ssuser5c9d4b1
Call Girls in Nagpur Suman Call 7001035870 Meet With Nagpur Escorts
Call Girls in Nagpur Suman Call 7001035870 Meet With Nagpur Escorts
Call Girls in Nagpur High Profile
Microscopic Analysis of Ceramic Materials.pptx
Microscopic Analysis of Ceramic Materials.pptx
purnimasatapathy1234
Recently uploaded
(20)
Call Girls Service Nagpur Tanvi Call 7001035870 Meet With Nagpur Escorts
Call Girls Service Nagpur Tanvi Call 7001035870 Meet With Nagpur Escorts
SPICE PARK APR2024 ( 6,793 SPICE Models )
SPICE PARK APR2024 ( 6,793 SPICE Models )
(RIA) Call Girls Bhosari ( 7001035870 ) HI-Fi Pune Escorts Service
(RIA) Call Girls Bhosari ( 7001035870 ) HI-Fi Pune Escorts Service
Roadmap to Membership of RICS - Pathways and Routes
Roadmap to Membership of RICS - Pathways and Routes
Introduction to Multiple Access Protocol.pptx
Introduction to Multiple Access Protocol.pptx
(SHREYA) Chakan Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Esc...
(SHREYA) Chakan Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Esc...
UNIT-II FMM-Flow Through Circular Conduits
UNIT-II FMM-Flow Through Circular Conduits
IMPLICATIONS OF THE ABOVE HOLISTIC UNDERSTANDING OF HARMONY ON PROFESSIONAL E...
IMPLICATIONS OF THE ABOVE HOLISTIC UNDERSTANDING OF HARMONY ON PROFESSIONAL E...
APPLICATIONS-AC/DC DRIVES-OPERATING CHARACTERISTICS
APPLICATIONS-AC/DC DRIVES-OPERATING CHARACTERISTICS
Call Girls Service Nashik Vaishnavi 7001305949 Independent Escort Service Nashik
Call Girls Service Nashik Vaishnavi 7001305949 Independent Escort Service Nashik
(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escorts
(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escorts
Processing & Properties of Floor and Wall Tiles.pptx
Processing & Properties of Floor and Wall Tiles.pptx
result management system report for college project
result management system report for college project
HARDNESS, FRACTURE TOUGHNESS AND STRENGTH OF CERAMICS
HARDNESS, FRACTURE TOUGHNESS AND STRENGTH OF CERAMICS
Top Rated Pune Call Girls Budhwar Peth ⟟ 6297143586 ⟟ Call Me For Genuine Se...
Top Rated Pune Call Girls Budhwar Peth ⟟ 6297143586 ⟟ Call Me For Genuine Se...
UNIT-V FMM.HYDRAULIC TURBINE - Construction and working
UNIT-V FMM.HYDRAULIC TURBINE - Construction and working
High Profile Call Girls Nagpur Isha Call 7001035870 Meet With Nagpur Escorts
High Profile Call Girls Nagpur Isha Call 7001035870 Meet With Nagpur Escorts
247267395-1-Symmetric-and-distributed-shared-memory-architectures-ppt (1).ppt
247267395-1-Symmetric-and-distributed-shared-memory-architectures-ppt (1).ppt
Call Girls in Nagpur Suman Call 7001035870 Meet With Nagpur Escorts
Call Girls in Nagpur Suman Call 7001035870 Meet With Nagpur Escorts
Microscopic Analysis of Ceramic Materials.pptx
Microscopic Analysis of Ceramic Materials.pptx
Survey On Two-Term Dot Product Of Multiplier Using Floating Point
1.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395 -0056 Volume: 04 Issue: 01 | Jan -2017 www.irjet.net p-ISSN: 2395-0072 © 2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 446 SURVEY ON TWO-TERM DOT PRODUCT OF MULTIPLIER USING FLOATING POINT 1MukeshKrishna. R, 2MohanaPriya.S, 3ManickaVasagam.P Department Electrical and Electronics Engineering Students, Dr. Mahalingam College of Engineering and Technology, Udumalai road, Pollachi. -------------------------------------------------------------------------------------------------------------- ABSTRACT-- The survey is based on the Floating Point in two-term Dot-Product of multiplier referred as discrete design. Floating Point is a wide variety for increasing accuracy, high speed, high performance and reducing delay, area and power consumption. This application of floating point is used for algorithms of Digital Signal Processing and Graphics. Many floating point application is to reduce area, from the survey the fused floating point gives better performance using both the single precision and the double precision in multiplication, addition and subtraction. The scientific notations sign bit, mantissa and exponent are used. The real numbers are divided into two, fixed component of significant range (lack of dynamic range) and exponential component in floating point (largest dynamic range). By converting from 24-bit to 48-bit fused floating point used to normalize the exponent part and rounding operation for latency reducing and the results are executed in the verilog hardware description Language. Index Terms-- Dot-Product Unit, fused floating point operations, normalization, rounding operations, latency, VHDL. I.INTRODUCTION The demand of floating point multiplier is more in Three-Dimensional (3D) array and also used in graphics and image processing. Fast Fourier Transform (FFT), Discrete Cosine Transform (DCT) and Butterfly operations are needed floating point numbers [1]. Due to output data size is twice larger than the input data size so complexity, area and time are consumed by the multipliers. The best design challenge to get high speed working is in Field Programmable Gate Array (FPGA). The floating point shows the base, the location, the precision and it normalized or not. There are many models for multiplication floating point. Precision is the main role in floating point. We deal with both single and double precision floating point. The main significant of floating point number are (Sign bit * Mantissa * Base Exponent). The single precision has 24-bits which contain 0 to 31, left to right and double precision has 64-bits which contain 0 to 63, left to right [2]. The difference of these two precision is data, the double precision has twice the data of RAM, Cache and Band Width and reduce the performance. The result of sign bit by XOR and carry save adder used for two exponent components.
2.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395 -0056 Volume: 04 Issue: 01 | Jan -2017 www.irjet.net p-ISSN: 2395-0072 © 2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 447 1.1Data formats for single and double precision: Sign bit S Biased Exponent 8 bit – E Unsigned fraction 23 – bits P a) Single Precision Data Format Sign bit S Biased Exponent 11 bit – E Unsigned fraction 53– bits P b) Double Precision Data Format 1.2 Format Parameters: The implementation of hardware and software has basic IEEE format. In the standard IEEE format the floating points are in binary number. The binary floating point numbers are single precision and double precision. The single precision contains 32 bits and the precision which adds the fraction and hidden bits 23+1, exponent bit 8 is used. The maximum and the minimum values from +127 to - 126. For the double precision, contain 64 bits and the precision which has 52+1, exponent bit is 11 is used. The maximum and the minimum values from -126 to -1022. For quadruple precision, hidden bits are 112+ 1 and the maximum and the minimum value from - 16382 to + 16383 [3]. 1.3 Representation of the floating point: Denormalized: Exponent part contain zeros and fraction or significand contain non-zeros denormalized is taken. Denormalized occur in zeros and lower normalized range [3]. Zero is a special value for exponent field all zeros and fraction zeroes. Overflow: Overflow occur limited range in smallest value and higher range in highest value. It indicate the range when reach extreme value. It doesn’t show the indication when one operand is infinity. It must have the exact range [4]. When the result reaches extreme range, bias should adjust and a NaN is delivered instead. Underflow: Underflow takes place when floating point is smaller than the smallest value. It may be negative or positive exponent from -128 to 127, when lesser than -128 underflow occur. The result may be zero or denormal [4]. There is loss of accuracy after the denormalized numbers. Under flow adjust the result from overflow delivery. Infinity: The value of -infinity and +infinity used in exponent 0s and 1s. Sign bit for positive 0 and negative 1 are used. It denotes infinity as special value for operations to continue past overflow situations. It used undefined operations [5]. Not a Number: It is an invalid value when does not show the real number representation. The exponent has 1s and the fraction has non-zeroes are taken in NaNs [6].
3.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395 -0056 Volume: 04 Issue: 01 | Jan -2017 www.irjet.net p-ISSN: 2395-0072 © 2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 448 II. APPROACH According to IEEE 754 2008 supports the floating point multiplier which has efficient carry saver. For the high performance of multiplier, pipe lining stages are used to increase operating frequency multiplier [5]. Here two approaches are seen for dot product unit, floating point adder and multiplier. The floating point 32 bit is in parallel operation is used for many application and minimizing the silicon area. A*(B+C) shows the parallel operation but in the fused floating point 3 cycles are reduced from 8 cycles instead of 2 cycles in 8 cycle. This greatly improves the performance. By rounding operation the addition cycle eliminated and directly performs the multiplication [6]. For the exact result of floating point operation rounding is needed. The different modes used are Rounding Mode Encoding Unrounded Rounded Nearest Even 00 3.4 3 Zero 01 5.6 6 Positive Infinity 10 3.5 4 Negative Infinity 11 2.5 2 III. FLOATING POINT MULTIPLICATION OPERATION The fused dot product derived from floating point add sub unit. They done separately and multiplexers choose add and sub with XOR process [7]. Converting decimal number to the floating point number, block diagram for floating point multiplier. Block diagram of floating point multiplier 3.1 FLOATING POINT ALGORITHM: 1. Converting the value to binary, take fractional part for separating the integral value and fractional value. This fractional part is converting by multiplication [8]. Multiply by 2 repeatedly and harvest each one bit. It shows the decimal value to floating point. For Example: Convert 2.625 to floating Point format: The integral part is 210 = 102 The fractional parts are 0.625*2= 1.25 – 1 0.25 *2= 0.5 -- 0 0.5 *2= 1.0 -- 1 For 0.62510 = 0.1012 and 2.62510 = 10.1012 2. Adding an exponent part to binary number: The Product of Append and 2 power Exponent in the end of binary numbers.
4.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395 -0056 Volume: 04 Issue: 01 | Jan -2017 www.irjet.net p-ISSN: 2395-0072 © 2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 449 10.1012 = 10.1012 * 20 3. Normalization: The value doesn’t change when exponent adjust to one bit left in binary number. 10.1012*20 = 1.01012* 21 5. Mantissa: Mantissa or significand is next to leading number which filled with zeroes on the right. Mantissa – 0101 6. Now add the bias to exponent of 2 in exponent field, for all biasing 2k-1 – 1, k=number of bits in exponent field. For example 8 – bit format 23-1 -1 = 3 32 –bit format 28-1 -1 = 127 Here the exponent power is 1, so 1 + 3 = 4 = 1002 7. The sign bit of negative is 1 and positive is 0 of given number. For 8 bit and 32 bit SIG N BIT MANTISSA EXPONENT 0 100 0101 0 10001001 0101000000000000 0000000 3.2 MULTIPLICATION OPERATION: Take 2 floating point number A= -18.0 and B= 9.5 Their binary values are A= -10010.0 B= +1001.1 and [9] the normalization A= -1.001*24 B= +1.0011*23 1 10000011 001000000000000000 00000 0 10000010 001100000000000000 00000 3.3 Multiplication of Mantissa: For normalization [10] adding 1 to the most significant bit is useful, A 100100000000000000000000 B 100110000000000000000000 0 1 0101011000000000 0000000 0000000000000000 0000000 The result is in 48 bit: 0*558000000000 3.4 Adding the exponents: For mantissa multiplication remove bias in two operands and add again the bias [10]. E result= (Ea-127) + (Eb-127) +127 E r= Ea+ Eb-127 then E r= 10000110 3.5 Calculation: The Sign result Sr by EXOR of two operands Sa= 1 and Sb= 0 is Sr= Sa Sb Sr= 1 0 = 1 The final result of sign, exponent and mantissa are 1 1000011 0 0101011000000000000000000 0 A*B = -18.0* 9.5 = -1.0101011*2134-127 = -10101011.0 =-171.010
5.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395 -0056 Volume: 04 Issue: 01 | Jan -2017 www.irjet.net p-ISSN: 2395-0072 © 2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 450 IV. PROPOSED SYSTEM The discrete design and floating point in 32 bit are the worst case for reducing the area and consumption. The proposed system is fused floating point dot product unit multiplication in double precision 48 bit reduce the delay and silicon area. It increases the speed faster than single precision floating point. It also decreases 40% of the worst errors. Floating points were implemented by conventional floating point and fused floating dot product unit multiplication in double precision. This A* B± C* D used in parallel operation is done by 2 cycles. For fused dot product is done in single cycle [11]. The design has been simulated in MODEL SIM, create design in work library as 45nm CMOS study cell and compile the design by go to simulation and start simulate to run, before that source code in VHDL [12]. VHDL is a high level language and used for digital circuits and systems. The system verilog input generates stimulus output. It is easy and similar to C programming and also used in Engineering Design Automation Tool. The fused floating points V. CONCLUSION The floating point multiplier is varied by 32 bit and 48 bit inputs. The simulation for both single precision and double precision design and implementation are analyzed [13]. The parallel operation is faster speed than the series single precision floating point. Comparing the fused floating point is higher performance than discrete values. The delay and silicon area are reduced and gives high speed more than 70%. Sometimes more performance in dual path reduction and pipe lining are used [14]. The more accurate result are performed by eliminating the rounding modes and normalization. The fused floating points are used for processors, system controllers and hardware. VI. REFERENCE [1] 32 bit Single Precision floating point Multiplier, Ms.Radhika Jumde, AVBIT, Pawnar, Wardha. [2] IEEE Standard for floating point arithmetic, IEEE Standard 754-2008, New York, Inc., Aug.29, 2008. [3] Saleh and E.Swartzlander, Jr., “A floating point fused dot product unit,” in Proc. IEEE Int. Conf. Compute Design, 2008, pp. 427—431. [4] Design and Simulation of Binary floating point multiplier using VHDL, U.V. Chaudhari and Prof.A.P.Dhande, Feb-2015. [5] Simulation and Synthesis for multipliers using VHDL, Raj kumar singh, Shivanada Reddy, 2008. [6] IEEE 754 floating point fused add sub unit, Sharmila Hemanandha, Siva Subramanian, Aug- 2015. [7] Floating point fused dot –Product Unit, kishore, Prakash, May-2015. [8] Floating Point Adder and Multiplier, Eduardo Sanchez EPFL- HEIG- VD. Aug-2013. [9] Normalization on floating point Multiplication using Verilog HDL, V.Narasimha, V.Swathi,
6.
International Research Journal
of Engineering and Technology (IRJET) e-ISSN: 2395 -0056 Volume: 04 Issue: 01 | Jan -2017 www.irjet.net p-ISSN: 2395-0072 © 2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 451 [10] Multiplication of floating point numbers using VHDL, Ms. Sobin Daniel, Sep-2014. [11] A floating point multiplier, Concordia University. [12] Design and Implementation of different multiplier using VHDL by Moumita Ghosh, Rourkela, 2007. [13] Design of floating point Multiplier, Vamsi Krishna, Trivedi, Mar-2014. [14] VHDL Modeling of floating point for VLSI designer Library, Wai-Leong Pang, Kah-Yoong Chan, Sew-Kin Wong, Choon- Siang Tan, July- 2012.
Download now