The document summarizes a study on the performance of a capacitor-less low dropout (LDO) voltage regulator using different types of resistors. A 1.8V LDO voltage regulator was designed and simulated using five different resistor types in Cadence. The performance metrics compared included output voltage accuracy, phase margin, unity gain bandwidth, and power supply rejection ratio. Simulation results showed differences in LDO performance depending on the resistor type. The LDO with hpoly resistor had the best stability performance, while the LDO with pdiffb resistor produced the highest power supply rejection ratio. In conclusion, the type of resistor used can significantly impact key performance characteristics of a capacitor-less LDO regulator.
A novel miniature coplanar band-pass filter for ISM applicationsjournalBEEI
This paper presents a novel approach to design a compact miniature coplanar band-pass filter by using rectangular split ring resonator. This proposed circuit is designed for the Industrial, Scientific and, Medical (ISM) frequency band applications at 2.4 GHz. At the first stage, a metamaterial resonator is designed and simulated in a TEM waveguide to verifiy its electromagnetic proprieties around the desired frequency bands. At the second stage, a band pass filter is designed using the proposed metamaterial resonator. Many parametric studies are realized to investigate the effect and influence of some resonator parameters on the proposed BPF performances. ADS Agilent and CST-MWS solvers are used in order to verify the simulated results. The circuit frequency responses show an excellent insertion loss and good return loss in the passband.
Circularly polarized antenna array based on hybrid couplers for 5G devicesjournalBEEI
This paper depicts a wideband circularly polarized (CP) antenna for 5G devices. The antenna array has a 3D structure including four simple printed dipole elements with directional radiations, high gain, and high efficiency. It achieves a CP by using the sequential rotation (SR) feeding based on 90°-3dB hybrid couplers in the proposed feeding network. The antenna array bandwidth is wide, 26.7%, with an operating frequency band from 3.35 GHz to 4.35 GHz. The antenna achieves a high peak gain of 10.73 dBi and high efficiency of 93.75%. Besides, the antenna gain is stable over the operating bandwidth (BW). At the centre operating frequency of 3.75 GHz, the angle of circular polarization is 51°. The antenna is designed and fabricated on the Rogers 4003 C substrate. The measured S11 is well matching with the simulation results. With the above characteristics, the proposed antenna can be a suitable candidate for 5G devices.
Outage performance users located outside D2D coverage area in downlink cellul...journalBEEI
Device-to-device (D2D) communication has been proposed to employ the proximity between two devices to enhance the overall spectrum utilization of a crowded cellular network. With the help of geometric probability tools, this framework considers the performance of cellular users under spatial separation with the D2D pair is investigated. The measurement results and analytical expression of outage probability show that the proposed frameworks improve the outage performance at a high signal-tonoise ratio (SNR) at the base station. Results also interpret that the distances between nodes in the D2D-assisted network make slight impacts on the performance of the cellular user.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Dielectric Resonator Reflectarray Antenna Unit Cells for 5G Applications IJECEIAES
This paper presents an investigation for the performance comparison of three different unit cell configurations operating at 26 GHz for 5G applications. The unit cells are cross shape dielectric resonator, cross microstrip patch and cross hybrid dielectric resonator. Verification of the comparison has been done by simulations using commercial Computer Simulation Technology Microwave Studio (CST MWS). The simulated results for reflection phase, slope variation, reflection loss and 10% bandwidth were analyzed and compared. The results indicate that the optimum configuration to be deployed for the reflectarray’s unit element in order to fulfill the 5G requirements of a wide bandwidth is the cross hybrid DRA. This configuration is a combination of cross DRA with cross microstrip patch as the parasitic element in order to tune the phase and provide a wide phase range with smooth variation slope. Cross hybrid DRA provided a wide phase range of 520° with 0.77 dB loss and 10% bandwidth of 160 MHz.
A novel miniature coplanar band-pass filter for ISM applicationsjournalBEEI
This paper presents a novel approach to design a compact miniature coplanar band-pass filter by using rectangular split ring resonator. This proposed circuit is designed for the Industrial, Scientific and, Medical (ISM) frequency band applications at 2.4 GHz. At the first stage, a metamaterial resonator is designed and simulated in a TEM waveguide to verifiy its electromagnetic proprieties around the desired frequency bands. At the second stage, a band pass filter is designed using the proposed metamaterial resonator. Many parametric studies are realized to investigate the effect and influence of some resonator parameters on the proposed BPF performances. ADS Agilent and CST-MWS solvers are used in order to verify the simulated results. The circuit frequency responses show an excellent insertion loss and good return loss in the passband.
Circularly polarized antenna array based on hybrid couplers for 5G devicesjournalBEEI
This paper depicts a wideband circularly polarized (CP) antenna for 5G devices. The antenna array has a 3D structure including four simple printed dipole elements with directional radiations, high gain, and high efficiency. It achieves a CP by using the sequential rotation (SR) feeding based on 90°-3dB hybrid couplers in the proposed feeding network. The antenna array bandwidth is wide, 26.7%, with an operating frequency band from 3.35 GHz to 4.35 GHz. The antenna achieves a high peak gain of 10.73 dBi and high efficiency of 93.75%. Besides, the antenna gain is stable over the operating bandwidth (BW). At the centre operating frequency of 3.75 GHz, the angle of circular polarization is 51°. The antenna is designed and fabricated on the Rogers 4003 C substrate. The measured S11 is well matching with the simulation results. With the above characteristics, the proposed antenna can be a suitable candidate for 5G devices.
Outage performance users located outside D2D coverage area in downlink cellul...journalBEEI
Device-to-device (D2D) communication has been proposed to employ the proximity between two devices to enhance the overall spectrum utilization of a crowded cellular network. With the help of geometric probability tools, this framework considers the performance of cellular users under spatial separation with the D2D pair is investigated. The measurement results and analytical expression of outage probability show that the proposed frameworks improve the outage performance at a high signal-tonoise ratio (SNR) at the base station. Results also interpret that the distances between nodes in the D2D-assisted network make slight impacts on the performance of the cellular user.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Dielectric Resonator Reflectarray Antenna Unit Cells for 5G Applications IJECEIAES
This paper presents an investigation for the performance comparison of three different unit cell configurations operating at 26 GHz for 5G applications. The unit cells are cross shape dielectric resonator, cross microstrip patch and cross hybrid dielectric resonator. Verification of the comparison has been done by simulations using commercial Computer Simulation Technology Microwave Studio (CST MWS). The simulated results for reflection phase, slope variation, reflection loss and 10% bandwidth were analyzed and compared. The results indicate that the optimum configuration to be deployed for the reflectarray’s unit element in order to fulfill the 5G requirements of a wide bandwidth is the cross hybrid DRA. This configuration is a combination of cross DRA with cross microstrip patch as the parasitic element in order to tune the phase and provide a wide phase range with smooth variation slope. Cross hybrid DRA provided a wide phase range of 520° with 0.77 dB loss and 10% bandwidth of 160 MHz.
Design and Simulation of Compact Wideband Rectangular Dielectric Resonator An...ijsrd.com
An objective of the paper is to optimize the parameters, and simulation analysis of compact wideband rectangular dielectric resonator antenna (RDRA). In this paper, a compact wideband, rectangular dielectric resonator antenna is presented using relatively low dielectric constant material and using double microstrip patch. The rectangular DRA is fed with a modified stepped microstrip feed to ensure efficient coupling between the RDRA and the feeder. The performance of the proposed antenna has been significantly improved by loading the RDRA with two narrow conducting metallic strips of suitable widths, which results in dual-resonance excitation and leads to a wider operating bandwidth (16.274-18.200 GHz). The frequency characteristics and radiation performance of the proposed antenna are successfully optimized. Design and simulation results are in excellent agreement.
Band-pass filter based on complementary split ring resonatorTELKOMNIKA JOURNAL
This letter presents a new circuit of the band-pass filter designed by using microstrip technology. Based on complementary split ring resonator and various series of optimization technic and a specific design method, a miniature band-pass filter with excellent electrical performances is achieved. First of all, the metamaterial unit cell is studied to obtain a desired resonant frequency and it is implemented in the ground plan in order to increase the characteristics of the bandpass behavior and decrease its operating frequencies. This proposed circuit is designed on an FR-4 substrate having a relative permittivity of 4.4 tangential losses of 0.025 and thickness of 1.6 mm. This filter is developed by using CST Microwave. The obtained features allow this filter to be used in diverse wireless applications such as IMT-E and WiMax.
Simulation and optimization of tuneable microstrip patch antenna for fifth-ge...IJECEIAES
Microstrip patch antennas (MPAs) are known largely for their versatility in terms of feasible geometries, making them applicable in many distinct circumstances. In this paper, a graphene-based tuneable single/array rectangular microstrip patch antenna (MPA) utilizing an inset feed technique designed to function in multiple frequency bands are used in a fifth-generation (5G) wireless communications system. The tuneable antenna is used to eliminate the difficulties caused by the narrow bandwidths typically associated with MPAs. The graphene material has a reconfigurable surface conductivity that can be adjusted to function at the required value, thus allowing the required resonance frequency to be selected. The simulated tuneable antenna comprises a copper radiating patch with four graphene strips used for tuning purposes and is designed to cover a wide frequency band. The proposed antenna can be tuned directly by applying a direct current (DC) voltage to the graphene strips, resulting in a variation in the surface impedance of the graphene strips and leading to shifts in the resonance frequency.
The Approach on Influence of Biasing Circuit in Wideband Low Noise Amplifier ...IJEACS
This proposed work investigates the effects of biasing
circuit in the ultra-wideband microwave low noise amplifier
which operates between 3GHz to 10GHz. The complete circuit is
visualized the importance of every component in the design with
respect to linear measurements like Gain, Noise Figure, Return
loss under unconditionally stable condition. The design and
realization are made by using Hybrid Microwave integrated
circuit in AWR microwave office. The thing that is absolutely
necessary and frequently the difficult step in the design of an
LNA is 'biasing circuit design'. The difficulty situation arises
because traditional methods LNA by using S-parameters data
files in EDA tools provides almost all linear measurements.
Hence a number of time consuming iterations of different biasing
circuits with optimization methods may be required to reach
targeted specifications with the fixed operating point at the
desired points in the load line. Considering this behavior, various
alternate biasing circuit schemes are prepared and founded the
results associated with it. Furthermore, this paper unmistakably
clarifies the impacts of the biasing circuit by utilizing
intermodulation and harmonics distortion technique for
portrayal characterization. Different cases and sorts of the
biasing circuits with various biasing focuses have been tested and given clear perspective of the biasing ideas.
Coplanar waveguide low pass filter based on square complementary split ring r...TELKOMNIKA JOURNAL
In this paper, we present a novel coplanar waveguide low pass filter (LPF)structure based on the use of square complementary split ring resonators (CSRRs) in order to enhance the performances of a low pass filter. Especially, to enlarge the bandwidth of the LPF, the insertion losses and to increase the rejection of the LPF. The CSRRs are optimised and inserted periodically along the center conductor of the CPW line with a CPW ground integrating stubs permitting to enlarge the bandwidth. The simulation results of this filter show a -3 dB cut-off frequency equal to fc = 5.28 GHz. The designed filter has a good rejection in the stop band which below -20 dB and presents a good insertion loss in the bandwidth. The proposed filter has been fabricated and tested which give a good agreement between simulation and measurement results, the whole dimensions of the validated filter are 35.48x21.16 mm2. The originality of this work is the wide rejection band and the miniature dimensions.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and modeling of solenoid inductor integrated with FeNiCo in high frequ...TELKOMNIKA JOURNAL
In this work, the design and modeling of the solenoid inductor are discussed. The layout of integrated inductors with magnetic cores and their geometrical parameters are developed. The quality factor Q and inductance value L are derived from the S-parameters and plotted versus frequency. The effect of solenoid inductor geometry on inductance and quality factor are studied via simulation using MATLAB. The solenoid inductor geometry parameters considered are the turn’s number, the magnetic core length, the width of a magnetic core, the gap between turns, the magnetic core thickness, the coil thickness, and solenoid inductor oxide thickness. The performance of the proposed solenoid inductor integrated with FeNiCo is compared with other solenoid inductors.
A wideband dielectric resonator antenna with a cross slot aperture for 5G com...TELKOMNIKA JOURNAL
This paper represents design of a wideband Rectangular Dielectric Resonator antenna fed by an aperture coupled technique. A bandwidth of 2.2 GHz has been achieved using a cross slot aperture in a ground plane for Dielectric Resonator Antenna (DRA). The simulated gain value achieved is 6.5 dBi. The Rectangular Dielectric Resonator which has been designed in this paper can be used in 5G application frequency band of 24.25-27.5 GHz. The calculated percentage bandwidth is 15.38%. An optimization of slot dimensions has also mentioned which can help to select a desired impedance match. The measured gain and bandwidth are efficient to use this design for various 5G applications. This unit cell wideband DRA can be used for millimeter wave frequencies of 5G.
Investigation of Integrated Rectangular SIW Filter and Rectangular Microstrip...IJASCSE
This paper presents an investigation based on the resonant circuit approach to characterize an integrated microwave filter and antenna from a lumped element prototype. This approach is used to design an integrated filter and antenna to reduce the overall size of the physical dimensions of the RF/microwave front-end subsystem. This study focuses on the integration of a rectangular Substrate Integrated Waveguide (SIW) filter with a rectangular microstrip patch antenna to produce a filtering and radiating element in a single device. The physical layouts of the SIW filter and rectangular microstrip patch antenna based on single- and dual-mode will be developed. To prove the concept, the integrated microwave filter and antenna at a center frequency of 2 GHz is demonstrated and validated through simulation and laboratory experiments. The experimental performance yielded promising results that were in good agreement with the simulated results. This study is beneficial for microwave systems, given that the reduction of the complexity of design and physical dimension as well as cost are important for applications such as base stations and multiplexers in wireless communication systems.
Reconfigurable ultra wideband to narrowband antenna for cognitive radio appli...TELKOMNIKA JOURNAL
Frequency reconfigurable antennas are very attractive for many wireless applications.They offer many advantages such as simplicity and compactness. In this electronicpaper, we propose a reconfigurable antenna operating in the S and C bands. Theproposed antenna uses a BAP65-02 RF diode to switch between the ultra widebandfrom 2.92 to 6.19 GHz to the narrowband from 2.92 to 3.93 GHz. The ultra widebandis obtained by a partial rectangular ground plane with a symmetrical rectangular slotand the narrowband is obtained by adding a parasitic element electrically connectedto the ground plane by the PIN diode when it is positively biased. This patch antennaoperates in the Federal Communications Commission band (FCC) and can be used forbiomedical applications such as radiometry imaging. The numerical simulation resultsbased on the finite element method and the finite integral method show a very goodagreement between them.
Impact of client antenna’s rotation angle and height of 5g wi fi access point...ijwmn
This paper investigates the impact of antenna rotation’s angle at the receiver side and antenna height at
transmitter side on radio channel’s amount of fading. Amount of fading is considered as a measure of
severity of fading conditions in radio channels. It indicates how severe the fading level relative to Rayleigh
fading channel. The results give an input to optimize height of 5G Wi-Fi access point for better link
performance for different antenna’s rotation angles at receiver side. The investigation covers three
different indoor environments with different multipath dispersion levels in delay and direction domains;
lecture hall, corridor, and banquet hall.
DESIGN AND ANALYSIS OF COMPACT UWB BAND PASS FILTERijeljournal
This paper presents design, implementation and analysis of an ultra-wideband (UWB) band-pass-filter using parallel-coupled microstrip line with defective ground plane and a uniform multi-mode resonator. The structure of the filter is designed on microwave substrate GML 1000 of dielectric constant 3.2 and height is 0.762 mm. Simulation is carried out by CST MSW software and optimized structure is fabricated. The frequency response is measured on vector analyzer and measured results show close approximation with simulation results. In this article modeling of the proposed filter is also reported. The electric model of the filter is analyzed by circuit theory and MATLAB. This model is validated by comparing the results with the CST simulation and VNA measured results. This filter is compact in size of dimension 30˟1.87 mm2 may be useful for modern wireless application of communication.
A new design of a microstrip rectenna at 5.8 GHz for wireless power transmiss...IJECEIAES
Due to the ever-increasing power demand, the need of electricity and eco-friendly power in every nook and corner of the world, many reaserch topics have been devoted to deal with this problematic. This paper is taking part of the proposed solutions with the presentation of a novel 5.8 GHz rectenna system for wireless power transmission applications. In one hand, a miniaturized 5.8 GHz circular polarized patch antenna has been designed and simulated by using the Advanced Design System (ADS). In the other hand, a rectifier structure has been investigated and optimized by the use of the Harmonic Balance method available in ADS. The circuit is based on 5 HSMS2820 Schottky diodes implemented in a voltage multiplier topology and a load resistance of 1 KOhm. Both of the structures have been validated by simulation and experimental results and good agreement has been concluded.
This paper proposes a compact size design of wideband bandpass filter (BPF). The broad-side coupling microstrip-slot technique is used to accomplish a good passband response with very low insertion loss across a wideband frequency range. The BPF that is designed using Rogers RO4003C substrate shows a good performance with the respective maximum reflection coefficient and insertion loss of -10 dB and 1.2 dB between 0.92 GHz and 5 GHz. This type of BPF filter is useful in any communication applications.
An improved design of CMOS dynamic latch comparator with dual input dual output with a simple
design of three stages is represented. The basic disadvantages of latch type comparators are overcome by
producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power
consumption is reduced to 450uW. It is designed for 1.8V DC supply voltage and 1 MHz clock frequency for
PVT variations. The simulation of the comparator is done in Cadence® Virtuoso Analog Design Environment
using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage. The delay is
brought down to 5nS. The active area appreciably is reduced. Layout of the proposed comparator has been
simulated in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS have been verified.
Design and Simulation of Compact Wideband Rectangular Dielectric Resonator An...ijsrd.com
An objective of the paper is to optimize the parameters, and simulation analysis of compact wideband rectangular dielectric resonator antenna (RDRA). In this paper, a compact wideband, rectangular dielectric resonator antenna is presented using relatively low dielectric constant material and using double microstrip patch. The rectangular DRA is fed with a modified stepped microstrip feed to ensure efficient coupling between the RDRA and the feeder. The performance of the proposed antenna has been significantly improved by loading the RDRA with two narrow conducting metallic strips of suitable widths, which results in dual-resonance excitation and leads to a wider operating bandwidth (16.274-18.200 GHz). The frequency characteristics and radiation performance of the proposed antenna are successfully optimized. Design and simulation results are in excellent agreement.
Band-pass filter based on complementary split ring resonatorTELKOMNIKA JOURNAL
This letter presents a new circuit of the band-pass filter designed by using microstrip technology. Based on complementary split ring resonator and various series of optimization technic and a specific design method, a miniature band-pass filter with excellent electrical performances is achieved. First of all, the metamaterial unit cell is studied to obtain a desired resonant frequency and it is implemented in the ground plan in order to increase the characteristics of the bandpass behavior and decrease its operating frequencies. This proposed circuit is designed on an FR-4 substrate having a relative permittivity of 4.4 tangential losses of 0.025 and thickness of 1.6 mm. This filter is developed by using CST Microwave. The obtained features allow this filter to be used in diverse wireless applications such as IMT-E and WiMax.
Simulation and optimization of tuneable microstrip patch antenna for fifth-ge...IJECEIAES
Microstrip patch antennas (MPAs) are known largely for their versatility in terms of feasible geometries, making them applicable in many distinct circumstances. In this paper, a graphene-based tuneable single/array rectangular microstrip patch antenna (MPA) utilizing an inset feed technique designed to function in multiple frequency bands are used in a fifth-generation (5G) wireless communications system. The tuneable antenna is used to eliminate the difficulties caused by the narrow bandwidths typically associated with MPAs. The graphene material has a reconfigurable surface conductivity that can be adjusted to function at the required value, thus allowing the required resonance frequency to be selected. The simulated tuneable antenna comprises a copper radiating patch with four graphene strips used for tuning purposes and is designed to cover a wide frequency band. The proposed antenna can be tuned directly by applying a direct current (DC) voltage to the graphene strips, resulting in a variation in the surface impedance of the graphene strips and leading to shifts in the resonance frequency.
The Approach on Influence of Biasing Circuit in Wideband Low Noise Amplifier ...IJEACS
This proposed work investigates the effects of biasing
circuit in the ultra-wideband microwave low noise amplifier
which operates between 3GHz to 10GHz. The complete circuit is
visualized the importance of every component in the design with
respect to linear measurements like Gain, Noise Figure, Return
loss under unconditionally stable condition. The design and
realization are made by using Hybrid Microwave integrated
circuit in AWR microwave office. The thing that is absolutely
necessary and frequently the difficult step in the design of an
LNA is 'biasing circuit design'. The difficulty situation arises
because traditional methods LNA by using S-parameters data
files in EDA tools provides almost all linear measurements.
Hence a number of time consuming iterations of different biasing
circuits with optimization methods may be required to reach
targeted specifications with the fixed operating point at the
desired points in the load line. Considering this behavior, various
alternate biasing circuit schemes are prepared and founded the
results associated with it. Furthermore, this paper unmistakably
clarifies the impacts of the biasing circuit by utilizing
intermodulation and harmonics distortion technique for
portrayal characterization. Different cases and sorts of the
biasing circuits with various biasing focuses have been tested and given clear perspective of the biasing ideas.
Coplanar waveguide low pass filter based on square complementary split ring r...TELKOMNIKA JOURNAL
In this paper, we present a novel coplanar waveguide low pass filter (LPF)structure based on the use of square complementary split ring resonators (CSRRs) in order to enhance the performances of a low pass filter. Especially, to enlarge the bandwidth of the LPF, the insertion losses and to increase the rejection of the LPF. The CSRRs are optimised and inserted periodically along the center conductor of the CPW line with a CPW ground integrating stubs permitting to enlarge the bandwidth. The simulation results of this filter show a -3 dB cut-off frequency equal to fc = 5.28 GHz. The designed filter has a good rejection in the stop band which below -20 dB and presents a good insertion loss in the bandwidth. The proposed filter has been fabricated and tested which give a good agreement between simulation and measurement results, the whole dimensions of the validated filter are 35.48x21.16 mm2. The originality of this work is the wide rejection band and the miniature dimensions.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and modeling of solenoid inductor integrated with FeNiCo in high frequ...TELKOMNIKA JOURNAL
In this work, the design and modeling of the solenoid inductor are discussed. The layout of integrated inductors with magnetic cores and their geometrical parameters are developed. The quality factor Q and inductance value L are derived from the S-parameters and plotted versus frequency. The effect of solenoid inductor geometry on inductance and quality factor are studied via simulation using MATLAB. The solenoid inductor geometry parameters considered are the turn’s number, the magnetic core length, the width of a magnetic core, the gap between turns, the magnetic core thickness, the coil thickness, and solenoid inductor oxide thickness. The performance of the proposed solenoid inductor integrated with FeNiCo is compared with other solenoid inductors.
A wideband dielectric resonator antenna with a cross slot aperture for 5G com...TELKOMNIKA JOURNAL
This paper represents design of a wideband Rectangular Dielectric Resonator antenna fed by an aperture coupled technique. A bandwidth of 2.2 GHz has been achieved using a cross slot aperture in a ground plane for Dielectric Resonator Antenna (DRA). The simulated gain value achieved is 6.5 dBi. The Rectangular Dielectric Resonator which has been designed in this paper can be used in 5G application frequency band of 24.25-27.5 GHz. The calculated percentage bandwidth is 15.38%. An optimization of slot dimensions has also mentioned which can help to select a desired impedance match. The measured gain and bandwidth are efficient to use this design for various 5G applications. This unit cell wideband DRA can be used for millimeter wave frequencies of 5G.
Investigation of Integrated Rectangular SIW Filter and Rectangular Microstrip...IJASCSE
This paper presents an investigation based on the resonant circuit approach to characterize an integrated microwave filter and antenna from a lumped element prototype. This approach is used to design an integrated filter and antenna to reduce the overall size of the physical dimensions of the RF/microwave front-end subsystem. This study focuses on the integration of a rectangular Substrate Integrated Waveguide (SIW) filter with a rectangular microstrip patch antenna to produce a filtering and radiating element in a single device. The physical layouts of the SIW filter and rectangular microstrip patch antenna based on single- and dual-mode will be developed. To prove the concept, the integrated microwave filter and antenna at a center frequency of 2 GHz is demonstrated and validated through simulation and laboratory experiments. The experimental performance yielded promising results that were in good agreement with the simulated results. This study is beneficial for microwave systems, given that the reduction of the complexity of design and physical dimension as well as cost are important for applications such as base stations and multiplexers in wireless communication systems.
Reconfigurable ultra wideband to narrowband antenna for cognitive radio appli...TELKOMNIKA JOURNAL
Frequency reconfigurable antennas are very attractive for many wireless applications.They offer many advantages such as simplicity and compactness. In this electronicpaper, we propose a reconfigurable antenna operating in the S and C bands. Theproposed antenna uses a BAP65-02 RF diode to switch between the ultra widebandfrom 2.92 to 6.19 GHz to the narrowband from 2.92 to 3.93 GHz. The ultra widebandis obtained by a partial rectangular ground plane with a symmetrical rectangular slotand the narrowband is obtained by adding a parasitic element electrically connectedto the ground plane by the PIN diode when it is positively biased. This patch antennaoperates in the Federal Communications Commission band (FCC) and can be used forbiomedical applications such as radiometry imaging. The numerical simulation resultsbased on the finite element method and the finite integral method show a very goodagreement between them.
Impact of client antenna’s rotation angle and height of 5g wi fi access point...ijwmn
This paper investigates the impact of antenna rotation’s angle at the receiver side and antenna height at
transmitter side on radio channel’s amount of fading. Amount of fading is considered as a measure of
severity of fading conditions in radio channels. It indicates how severe the fading level relative to Rayleigh
fading channel. The results give an input to optimize height of 5G Wi-Fi access point for better link
performance for different antenna’s rotation angles at receiver side. The investigation covers three
different indoor environments with different multipath dispersion levels in delay and direction domains;
lecture hall, corridor, and banquet hall.
DESIGN AND ANALYSIS OF COMPACT UWB BAND PASS FILTERijeljournal
This paper presents design, implementation and analysis of an ultra-wideband (UWB) band-pass-filter using parallel-coupled microstrip line with defective ground plane and a uniform multi-mode resonator. The structure of the filter is designed on microwave substrate GML 1000 of dielectric constant 3.2 and height is 0.762 mm. Simulation is carried out by CST MSW software and optimized structure is fabricated. The frequency response is measured on vector analyzer and measured results show close approximation with simulation results. In this article modeling of the proposed filter is also reported. The electric model of the filter is analyzed by circuit theory and MATLAB. This model is validated by comparing the results with the CST simulation and VNA measured results. This filter is compact in size of dimension 30˟1.87 mm2 may be useful for modern wireless application of communication.
A new design of a microstrip rectenna at 5.8 GHz for wireless power transmiss...IJECEIAES
Due to the ever-increasing power demand, the need of electricity and eco-friendly power in every nook and corner of the world, many reaserch topics have been devoted to deal with this problematic. This paper is taking part of the proposed solutions with the presentation of a novel 5.8 GHz rectenna system for wireless power transmission applications. In one hand, a miniaturized 5.8 GHz circular polarized patch antenna has been designed and simulated by using the Advanced Design System (ADS). In the other hand, a rectifier structure has been investigated and optimized by the use of the Harmonic Balance method available in ADS. The circuit is based on 5 HSMS2820 Schottky diodes implemented in a voltage multiplier topology and a load resistance of 1 KOhm. Both of the structures have been validated by simulation and experimental results and good agreement has been concluded.
This paper proposes a compact size design of wideband bandpass filter (BPF). The broad-side coupling microstrip-slot technique is used to accomplish a good passband response with very low insertion loss across a wideband frequency range. The BPF that is designed using Rogers RO4003C substrate shows a good performance with the respective maximum reflection coefficient and insertion loss of -10 dB and 1.2 dB between 0.92 GHz and 5 GHz. This type of BPF filter is useful in any communication applications.
An improved design of CMOS dynamic latch comparator with dual input dual output with a simple
design of three stages is represented. The basic disadvantages of latch type comparators are overcome by
producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power
consumption is reduced to 450uW. It is designed for 1.8V DC supply voltage and 1 MHz clock frequency for
PVT variations. The simulation of the comparator is done in Cadence® Virtuoso Analog Design Environment
using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage. The delay is
brought down to 5nS. The active area appreciably is reduced. Layout of the proposed comparator has been
simulated in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS have been verified.
FAST TRANSIENT RESPONSE LOW DROPOUT VOLTAGE REGULATORijseajournal
This paper presents the design of Low Drop-Out (LDO) voltage regulator has fast transient response and which exploits a few current else low quiescent current in the operational amplifier PMOS type. We use band-gap reference for eliminate the temperature dependence. The proposed LDO voltage regulator implemented in 0.18-μm CMOS technology, we use Folded cascode CMOS amplifiers high performance in the stability , provide fast transient response which explains a fast settling, the LDO itself should provide in the output regulator voltages at t equal 2ps with transient variation of the voltage less than 170mV. High accuracy in the DC response terms, the simulation results show that the accuracy of the output regulator voltages is 1.54±0.009V, and power consumption of 1.51 mW.
A low quiescent current low dropout voltage regulator with self-compensationjournalBEEI
This paper proposed a low quiescent current low-dropout voltage regulator (LDO) with self-compensation loop stability. This LDO is designed for Silicon-on-Chip (SoC) application without off-chip compensation capacitor. Worst case loop stability phenomenon happen when LDO output load current (Iload) is zero. The second pole frequency decreased tremendously towards unity-gain frequency (UGF) and compromise loop stability. To prevent this, additional current is needed to keep the output in low impedance in order to maintain second pole frequency. As Iload slowly increases, the unneeded additional current can be further reduced. This paper presents a circuit which performed self-reduction on this current by sensing the Iload. On top of that, a self-compensation circuit technique is proposed where loop stability is selfattained when Iload reduced below 100μA. In this technique, unity-gain frequency (UGF) will be decreaed and move away from second pole in order to attain loop stability. The decreased of UGF is done by reducing the total gain while maintaining the dominant pole frequency. This technique has also further reduced the total quiescent current and improved the LDO’s efficiency. The proposed LDO exhibits low quiescent current 9.4μA and 17.7μA, at Iload zero and full load 100mA respectively. The supply voltage for this LDO is 1.2V with 200mV drop-out voltage. The design is validated using 0.13μm CMOS process technology.
ENERGY-EFFICIENT LOW DROPOUT REGULATOR WITH SWITCHING MECHANISM AND COURSE RE...ijesajournal
The proposed work presents an Energy-efficient, low dropout (LDO) regulator with switching mechanism reduces the energy consumption of IoT devices when the sensors are in idle time. Based on the analysis of IoT devices and sensors, modern power management designs for IoT demands for fully integrated solutions to decrease power consumption while maintaining the quick transient response to signal variations. LDO voltage regulators, as power management devices should adjust to modern technological and industrial trends. To increase the current capability with a minimum standby quiescent current under small-signal operation, the proposed work has a switching circuit acting as an ON and OFF switch. To reduce the dropout a course regulator and loop filter is added and circuit is enhanced for maximum reduced dropout. As a result, the efficiency gets increased.
ENERGY-EFFICIENT LOW DROPOUT REGULATOR WITH SWITCHING MECHANISM AND COURSE RE...ijesajournal
The proposed work presents an Energy-efficient, low dropout (LDO) regulator with switching mechanism
reduces the energy consumption of IoT devices when the sensors are in idle time. Based on the analysis of
IoT devices and sensors, modern power management designs for IoT demands for fully integrated solutions
to decrease power consumption while maintaining the quick transient response to signal variations. LDO
voltage regulators, as power management devices should adjust to modern technological and industrial
trends. To increase the current capability with a minimum standby quiescent current under small-signal
operation, the proposed work has a switching circuit acting as an ON and OFF switch. To reduce the
dropout a course regulator and loop filter is added and circuit is enhanced for maximum reduced dropout.
As a result, the efficiency gets increased.
MODELING AND SIMULATION OF SOLAR PHOTOVOLTAIC APPLICATION BASED MULTILEVEL IN...ecij
As the solar market is blooming and forecasted to continue this trend in the coming years. The efficiency and reliability of PV based system has always been a contention among researchers. Therefore, multilevel inverters are gaining more assiduity as it has multitude of benefits. It offers high power capability along with low output harmonics. The main disadvantage of MLI is its complexity and requirement of large
number of power devices and passive components. This paper presents a topology that achieves 37.5% reduction in number of passive components and power devices for five-level inverter. This topology is basically based on H-bridge with bi-directional auxiliary switch. This paper includes a stand-alone PV
system in which designing and simulation of Boost converter connected with multilevel inverter for ac load is presented. Perturb and observe MPPT algorithm has been implemented to extract maximum power. The premier objective is to obtain Voltage with less harmonic distortion economically. Multicarrier Sinusoidal PWM techniques have been implemented and analysed for modulation scheme. The Proposed system is
simulated n MATLAB/Simulink platform.
MODELING AND SIMULATION OF SOLAR PHOTOVOLTAIC APPLICATION BASED MULTILEVEL IN...ecij
As the solar market is blooming and forecasted to continue this trend in the coming years. The efficiency and reliability of PV based system has always been a contention among researchers. Therefore, multilevel inverters are gaining more assiduity as it has multitude of benefits. It offers high power capability along with low output harmonics. The main disadvantage of MLI is its complexity and requirement of large
number of power devices and passive components. This paper presents a topology that achieves 37.5% reduction in number of passive components and power devices for five-level inverter. This topology is basically based on H-bridge with bi-directional auxiliary switch. This paper includes a stand-alone PV system in which designing and simulation of Boost converter connected with multilevel inverter for ac load is presented. Perturb and observe MPPT algorithm has been implemented to extract maximum power. The premier objective is to obtain Voltage with less harmonic distortion economically. Multicarrier Sinusoidal
PWM techniques have been implemented and analysed for modulation scheme. The Proposed system is simulated n MATLAB/Simulink platform.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
A 10 d bm 25 dbm, 0.363 mm2 two stage 130 nm rf cmos power amplifierVLSICS Design
This paper proposes a 2.4 GHz RF CMOS Power amplifi
er and variation in its main performance
parameters i.e, output power, S-parameters and powe
r added efficiency with respect to change in supply
voltage and size of the power stage transistor. The
supply voltage was varied form 1 V to 5 V and the
range
of output power at 1dB compression point was found
to be from 10.684 dBm to 25.08 dBm respectively.
The range of PAE is 16.65 % to 48.46 %. The width o
f the power stage transistor was varied from 150 μm
to 500 μm to achieve output power of range 15.47 dB
m to 20.338 dBm. The range of PAE obtained here is
29.085 % to 45.439 %. The total dimension of the la
yout comes out to be 0.714 * 0.508 mm
2
.
Transformerless Topology for Grid-Conected Inverters With Unipolar PWM ControlIJERA Editor
Most of the PV systems are designed with transformer for safety purpose with galvanic isolation. However, the transformer is big, heavy and expensive. Also, it reduces the overall frequency of the conversion stage. Generally PV inverter with transformer is having good efficiency. To overcome these problems, transformer less PV system is introduced. It is smaller, lighter, cheaper and higher in efficiency. However, dangerous leakage current will flow between PV array and the grid due to the stray capacitance. There are different types of configurations available for transformer less inverters like H5, H6, HERIC, and Dual paralleled buck inverter. But each configuration is suffering from its own disadvantages like high conduction losses, shoot-through issues of switches, dead-time requirements at zero crossing instants of grid voltage to avoid grid shoot-through faults and MOSFET reverse recovery issues. The main objective of the proposed transformer less inverter is to address two key issues: One key issue for a transformer less inverter is that it is necessary to achieve high efficiency compared to other existing inverter topologies. Another key issue is that the inverter configuration should not have any shoot-through issues for higher reliability.
Microelectronic technology
This report briefly discusses the need for Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), their structure and principle of operation. Then it details the fabrication and characterization of the MOSFETs fabricated at the microelectronic lab at University of Malaya
shows the simulation and analysis of a MOSFET device using the MOSFet tool. Several powerful analytic features of this tool are demonstrated, including the following:
calculation of Id-Vg curves
potential contour plots along the device at equilibrium and at the final applied bias
electron density contour plots along the device at equilibrium and at the final applied bias
spatial doping profile along the device
1D spatial potential profile along the device
A Novel Integrated AC-DC Five Level Converter Strategy for Power Factor Corre...IJMTST Journal
Multilevel configuration has the advantage of its simplicity and modularity over the configurations of the other converters. With the application of multilevel converter in the high voltage and large power occasions in recent years, its modulation strategy has become a research hot point in the field of power electronics. The proposed power-factor-correction circuit can achieve unity power factor and ripple-free input current using a coupled inductor. The proposed rectifier can also produce input currents that do not have dead band regions and an output current that is continuous for all load conditions. The features of this converter are that it has lower input section peak current stresses and a better harmonic content than similar converter with a non-interleaved output, the output current is continuous for all load ranges, and the dc bus voltage is less than 450 for all line and load conditions. In this paper, the operation of the new converter is explained, its steady-state characteristics are determined by analysis, and these characteristics are used to develop a procedure for the design of the converter. Hence the simulation results are obtained using MATLAB/SIMULINK software. The proposed system provides a closed loop control for variable output voltage. The SSPFC AC/DC converter can operate with lower peak voltage stresses across the switches and the DC bus capacitors as it is a three-level converter. The proposed concept can be implemented with 5-level for efficient output voltage.
Design of 6 bit flash analog to digital converter using variable switching vo...VLSICS Design
This paper presents the design of 6-bit flash analog to digital Converter (ADC) using the new variable
switching voltage (VSV) comparator. In general, Flash ADCs attain the highest conversion speed at the
cost of high power consumption. By using the new VSV comparator, the designed 6-bit Flash ADC exhibits
significant improvement in terms of power and speed of previously reported Flash ADCs. The simulation
result shows that the converter consumes peak power 2.1 mW from a 1.2 V supply and achieves the speed of
1 GHz in a 65nm standard CMOS process. The measurement of maximum differential and integral
nonlinearities (DNL and INL) of the Flash ADC are 0.3 LSB and 0.6 LSB respectively.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
JMeter webinar - integration with InfluxDB and GrafanaRTTS
Watch this recorded webinar about real-time monitoring of application performance. See how to integrate Apache JMeter, the open-source leader in performance testing, with InfluxDB, the open-source time-series database, and Grafana, the open-source analytics and visualization application.
In this webinar, we will review the benefits of leveraging InfluxDB and Grafana when executing load tests and demonstrate how these tools are used to visualize performance metrics.
Length: 30 minutes
Session Overview
-------------------------------------------
During this webinar, we will cover the following topics while demonstrating the integrations of JMeter, InfluxDB and Grafana:
- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
- What are the benefits of integrating InfluxDB and Grafana into the load testing stack?
- Which features are provided by Grafana?
- Demonstration of InfluxDB and Grafana using a practice web application
To view the webinar recording, go to:
https://www.rttsweb.com/jmeter-integration-webinar
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
Generating a custom Ruby SDK for your web service or Rails API using Smithyg2nightmarescribd
Have you ever wanted a Ruby client API to communicate with your web service? Smithy is a protocol-agnostic language for defining services and SDKs. Smithy Ruby is an implementation of Smithy that generates a Ruby SDK using a Smithy model. In this talk, we will explore Smithy and Smithy Ruby to learn how to generate custom feature-rich SDKs that can communicate with any web service, such as a Rails JSON API.
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
Neuro-symbolic is not enough, we need neuro-*semantic*
Study on performance of capacitor less ldo with different types of resistor
1. Study on Performance of Capacitor-less LDO with
Different Types of Resistor
Wan Maziyah Ab. Halim
Dept. of Electronic Engineering
UNiKL BMI
Malaysia
maziyah.halim@s.unikl.edu.my
Yuzman Yusoff
Research and Development (IC),
MIMOS Bhd.
Malaysia
yuzman@mimos.my
Julie Roslita Rusli
Dept. of Electronic Engineering
UNiKL BMI
Malaysia
julie@unikl.edu.my
Chia Chieu Yin
Research and Development (IC),
MIMOS Bhd.
Malaysia
cy.chia@mimos.my
Suhaidi Shafie
Dept. of Electrical & Electronic
Engineering
UPM
Malaysia
suhaidi@upm.edu.my
Abstract—This paper studies the impact of utilizing different
resistor types in capacitor-less low drop-out (LDO) voltage
regulator on its key performance characteristics. In order to
achieve this, a 1.8 V LDO voltage regulator is designed and
characterized using 180 nm CMOS technology with a supply
voltage of 3.3 V. Simulations are done in schematic level using
Cadence on five different types of resistor for the same LDO,
and the performance in terms of output voltage accuracy,
stability and power supply rejection ratio (PSRR) are
compared. From the simulation results, significant differences
are observed in the LDO’s performance with different types of
resistor. The LDO with hpoly resistor gives the best results in
terms of stability while pdiffb resistor LDO produces the highest
PSRR.
Keywords—capacitor-less LDO, capacitor-less LDO
performance comparison, LDO resistor type comparison
I. INTRODUCTION
The expansion of mobile electronics area makes a low
dropout (LDO) voltage regulator an important building block
in power management system as it can be designed to supply
a specific desired output voltage needed by the circuits from
limited supply voltage. It enables the user to regulate an output
voltage from a higher input voltage in a simple and
inexpensive way [1] as it is used to approximate an ideal
voltage source in real life [2]. A basic LDO circuit consists of
four main parts; the error amplifier, the pass transistor, the
feedback network and the load as shown in Fig. 1 [2]. One of
the recent improvement areas in LDOs is to make it capacitor-
less. In LDOs, a bulky external capacitor, denoted as CL in
Fig. 1, is often needed to provide stability and good transient
response. Stability is critical in LDO design since the unity
gain bandwidth (UGBW) and the poles locations are directly
affected by the load current IL [3]. The PSRR can also be
improved by using the large off-chip load capacitor. However,
the drawback of using it is mainly the need to use external
component, hence preventing the LDO to be used in system-
on-chip (SOC) solutions, besides higher cost and increased
total printed circuit board (PCB) area [3]. Therefore, a LDO
that has good stability and high PSRR but does not require a
large external capacitor will provide a great advantage to a
system which aims for minimum external component and
minimal area, which is what portable device is all about these
days.
An LDO’s performance is measured and evaluated based
on a few key criteria. One of the key criteria is the stability,
and the parameter which is used to determine it is the phase
margin. In order for the system to be considered stable, the
phase margin needs to be at least 60°. Another key criterion of
the LDO is the PSRR. PSRR refers to the amount of voltage
ripple at the output of the LDO coming from the input voltage
[3]. The PSRR is measured in decibel (dB), with greater
magnitudes implying better ripple rejection at the output.
Variation across temperature and process also have to be
considered, especially in systems involving resistors and
capacitors. These variations can affect the output voltage
accuracy of the LDO, since they can cause a change in a
particular parameter in the elements, such as resistance,
current and etc. This is because capacitors and resistors are
circuit elements in which their values change with temperature
[4].
Multiple studies and research were done in different areas
of a LDO to improve its performance. For error amplifiers,
different circuit approach and topologies were studied in order
to find the best solution. Studies were also done on the pass
transistor, on whether it is best to use NMOS or PMOS to get
the best results under different conditions. There are also
complementary circuits suggested in other studies to improve
the PSRR of the LDO. Since numerous studies were done in
the mentioned areas and other complementary circuits of the
LDO, this paper will focus on the impact of different resistor
types on the LDO performance. Different resistor types have
different parameters, such as sheet resistivity which will affect
its total area, parasitic capacitance, and variation in
temperature and process. These parameters might affect the
performance of the LDO in the key criteria discussed
Fig. 1 Basic LDO topology
2. previously. Due to its capacitor-less feature, parasitic
capacitance has become an important parameter to be
considered, as the LDO will not have the large external
capacitor for stability compensation. Since there will be two
resistors in the voltage divider, matching is also an important
feature to achieve optimum results [5].
II. LDO DESIGN
A. LDO Sub-circuits Design
The LDO in this paper employed a single stage differential
op-amp topology for its error amplifier as shown in Fig. 2. The
topology was chosen for design simplicity and stability
purpose [6].
The pass transistor used for the LDO is a PMOS. PMOS
is widely used in most LDOs as the pass transistor due to its
characteristic of operation which turns on when the gate
voltage is lower than the source voltage by a threshold voltage.
This makes it suitable for systems with low supply voltage [7],
which is currently the case for most integrated circuit designs
as CMOS technology becomes smaller in scale with time. If a
NMOS is to be used as the pass transistor, a higher voltage
which is sufficient enough to turn on the pass transistor is
required. If the supply voltage is not high enough,
complementary circuits to boost up the voltage at the gate is
needed.
Two resistors were used for the feedback network in the
LDO as shown in Fig. 1. In this design, the value of VREF is
1.2 V, and it will set the feedback node of the LDO to this
voltage. A 120 kΩ resistor for R2 was needed to maintain the
pre-set current of 10 µA going through the two resistors. R1
was set to 60 kΩ in order to generate the 1.8 V output voltage
of the LDO.
The load current set for the simulation was 10 mA, with a
load capacitor of 100 pF. The load capacitance was decided
based on available capacitor-less LDOs [8] [9].
B. Tested Resistor Types
Various resistor types are available in the 180 nm CMOS
process library. There are resistors with smaller resistance
value (in the range of tens to kΩ) while there are also resistors
which can provide larger resistance values (up to the range of
MΩ). Each resistor type comes with its own parasitic element
modelled by the foundry, which means the parasitics were
considered and included when the resistor was simulated. The
resistors tested in this paper are all in the larger resistance
value category, as the resistance of R1 and R2 are in the range
of tens and hundreds of kΩ. The resistors tested were finalized
to be five types as listed below:
i. hpoly (High P+ poly resistor)
ii. pplyb (P poly unsalicide resistor)
iii. pdiffb (P+ diffusion unsalicide resistor)
iv. ndiffb (N+ diffusion unsalicide resistor)
v. sbninw (N+ diffusion unsalicide resistor on nwell)
III. DESIGN AND TEST METHODOLOGY
In designing the LDO used for this study, the initial step
was to design and characterize an error amplifier to satisfy
certain basic requirements such as gain, stability and PSRR.
The error amplifier was then integrated with a PMOS pass
transistor and a feedback network using ideal resistors to
develop a complete LDO. The size of the pass transistor was
properly tuned until it can drive the current set at the output
node.
The simulated results of ideal resistors were obtained, and
the resistors for the feedback network were changed from
ideal to real resistors listed in section II (B). Simulations were
repeated for every type of resistor. The parameters of each
resistor material were set so that R1 and R2 would have the
same width. The purpose of fixing the width was to match
both resistors R1 and R2. R1 and R2 were divided into
segments with each segment having the same width and
length. This provides great advantage in matching and
parasitic distribution in layout design. The usage of unit
resistor is important for precision over large temperature
range [10]. Table I specifies the details of the parameters set
for all resistors used in the tests.
TABLE I. RESISTOR MATERIAL TYPE AND RESPECTIVE
PARAMETERS SET
W/L ratio
No. of
Segments
W/L ratio
No. of
Segments
Ideal n/a n/a n/a n/a n/a
hpoly 1/9 6 1/9 12 840
pplyb 1/31 6 1/31 12 2600
pdiffb 1/23 20 1/23 40 6600
ndiffb 1/29 30 1/29 60 12000
sbninw 1/33 30 1/33 60 18500
Material
R1 = 60 kΩ R2 = 120 kΩ Estimated
Total Area
/ µm2
Fig. 2. Single-stage Op-amp Circuit
3. IV. RESULTS AND DISCUSSION
The LDOs with different resistors were compared in the
following criteria:
A. Output voltage accuracy
B. Phase margin
C. UGBW
D. PSRR
A. Output Voltage Accuracy
The output voltage of the LDO with all resistors showed
fairly accurate reading from 99.99% to 100% of accuracy as
shown in Table II, taking the expected value of 1.8 V as 100%
benchmark. This shows that there is almost no degradation in
resistance value and no changes in current at the output node.
LDOs with hpoly, pplyb and pdiffb produced the output
voltage of 1.7999 V, while the LDOs with ndiffb and sbninw
produced 1.8 V, the same with the expected output voltage of
the LDO. All output voltages are shown in Fig. 3.
The output voltage was also simulated from a temperature
of -40 °C to 125 °C, and the results showed very small
variation for the five types of resistor, within the range of 30
µV to 50 µV. Based on Fig. 4, hpoly and pplyb have almost
identical variation curve across temperature, overlapping
with the ideal resistor’s curve. As for pdiffb, the pattern is the
same with hpoly and pplyb but at 20 µV lower potential.
Resistors ndiffb and sbninw have slightly different curve
patterns from the rest at higher temperatures.
In terms of process variation as can be seen in Fig. 5, three
defined process in the library for the resistors were simulated;
minimum, typical and maximum. The LDO with hpoly and
pplyb resistors have the smallest voltage difference between
minimum and maximum with 0.8 µV of voltage change,
while the LDO with sbninw resistor, with 6.8 µV has the
largest voltage change. From the voltage change shown in
Table II, it can be observed that the value becomes larger for
resistors which have larger total area which was shown in
Table I.
B. Phase Margin
The phase margin produced by using ideal resistors was
84.8°, which is considered very stable for most systems, and
followed closely by the LDO with hpoly, with a phase margin
of 83.6°, showing a slight degradation from the ideal resistor.
The LDO using pplyb came in third with 80.7°. Out of the
five tested resistors, hpoly and pplyb were the only types
which maintained the phase margin to be above 60°. The
phase margin for the LDO using pdiffb was 53.0°, followed
by sbninw with 50.4° and the lowest phase margin was 38.9°,
produced by ndiffb with a difference of 45.9° compared to the
ideal resistors LDO. All phase margin curves are included in
Fig. 6.
Obvious degradation in phase margins could be observed
for LDOs using ndiffb and sbninw resistors probably due to
the parasitic capacitance produced by them. As the sheet
resistivity for the two materials are much lower (below 100
Ω) compared to hpoly, pplyb and pdiffb (between 300Ω to 1
kΩ), the estimated total areas for ndiffb and sbninw were
therefore larger, producing higher parasitic capacitance. If the
parasitic capacitance is large enough, the position of the
secondary pole could possibly be shifted, causing the system
to become less stable.
Fig. 3 LDO Output voltage for all types of resistor.
Fig. 4 LDO output voltage across temperature for all resistor types
Fig. 5 LDO output voltage with process variation for all resistor types
4. C. UGBW
All materials produced the same DC gain of approximately
76 dB as can be seen in Fig. 7. In terms of UGBW, LDOs with
hpoly and pplyb had the same value with the ideal resistor
UGBW of 1.86 MHz. The LDO with pdiffb resistor showed a
slight decline to 1.58 MHz, followed by sbninw with 1.49
MHz. The lowest UGBW came from the LDO with ndiffb
resistor with 1.23 MHz of UGBW, showing degradation of
630 kHz from the LDO with the ideal resistors.
D. PSRR
As shown in Fig. 8, the PSRR for ideal resistor LDO were
approximately 76 dB, 65 dB, 25 dB and 6 dB at 10 Hz, 1 kHz,
100 kHz and 1 MHz respectively. The PSRR for all resistor
types were around the same values as the ideal resistor LDO
at 10 Hz. At 1 kHz, except for LDO using pdiffb resistor
which obtained higher PSRR at about 72 dB, all other
resistors had 65 dB of PSRR. At 100 kHz, the LDO with
pdiffb resistor again showed the highest PSRR with 34 dB,
while the rest of the resistors obtained the same PSRR as the
ideal resistor LDO with 25 dB. The variation of PSRR at 1
MHz was more distinct for LDOs with pdiffb, ndiffb and
sbninw with 10 dB, 1 dB and 3 dB respectively, while hpoly
and pplyb showed the same PSRR as the ideal resistor LDO
with 6 dB. While the LDOs using hpoly and pplyb resistors
had the closest results to ideal resistor, the LDO using pdiffb
resistor showed the highest PSRR at all three frequencies
compared to the other materials, while ndiffb has the lowest
PSRR at 1MHz frequency, as can be seen in Table II. The
only difference between pdiffb and the other resistors is its
body connection. While the body connections for hpoly,
pplyb and ndiffb were to ground, the body of pdiffb was
connected to the supply voltage. This implies that the
parasitic capacitance models of the pdiffb resistor was also
connected to the supply voltage. Table II summarizes the
simulated performances of the LDO with different types of
resistor.
TABLE II. STABILITY AND PSRR COMPARISON FOR DIFFERENT
RESISTOR TYPE LDOS
V. CONCLUSION
From the results, it is concluded that there are significant
impacts in LDO performance when using different types of
resistor. All five different types of resistor produce high level
of accuracy for the output voltage with very small variation
across temperature and under different process. In overall,
hpoly has the best results comparable to the ideal resistor in
terms of stability, with 1% difference in phase margin and
identical UGBW with the ideal resistor, followed closely by
pplyb. In terms of PSRR on the other hand, pdiffb shows the
highest result, with a significant increase of approximately
11% at 1 kHz, 36% at 100 kHz and 67% at 1 MHz as
compared to the ideal resistor. The drawback of pdiffb resistor
Vout (V)
Accuracy
(%)
ΔV-Process
(µV)
@10 Hz @1 kHz @100 kHz @1 MHz
Ideal 1.7999 99.99 n/a 1.86 M 84.8 76 65 25 6
hpoly 1.7999 99.99 0.8 1.86 M 83.6 76 65 25 6
pplyb 1.7999 99.99 0.8 1.86 M 80.7 76 65 25 6
pdiffb 1.7999 99.99 3.5 1.58 M 53.0 76 72 34 10
ndiffb 1.8000 100.00 4.1 1.23 M 38.9 76 65 25 1
sbninw 1.8000 100.00 6.9 1.49 M 50.4 76 65 25 3
PSRR (dB)
Resistor
Type
UGBW
(Hz)
Phase
Margin
(°)
Output Voltage Accuracy
Fig. 6 Phase margins for all materials
Fig. 7 DC gain for all materials
Fig. 8 PSRR for all materials
5. is its relatively much lower sheet resistivity compared to
hpoly and pplyb, which results in very large area consumption
for large resistance values, thus making it less suitable for
LDOs which aim for low quiescent current. Nonetheless, if
PSRR is the highest priority, pdiffb would make the best
option given that bigger current is acceptable to compensate
lower resistance value in order to reduce the total area of the
resistor.
ACKNOWLEDGMENT
The authors would like to thank Universiti Kuala Lumpur
British Malaysia Institute (UNiKL BMI), MIMOS and
Universiti Putra Malaysia (UPM) for supporting and
accommodating this research.
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