Storage Class Memory: Learning from 3D NAND
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Keynote presentation from Flash Memory Summit 2016 by Dr. Siva Sivaram. Learn his perspective on opportunities and challenges in developing a memory cell solution for the Storage Class Memory market, and lessons learned from 3D NAND.
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Storage Class Memory: Learning from 3D NAND
- 1. Siva Sivaram EVP of Memory Technology, Western Digital Corporation August 9, 2016 Storage Class Memory: Learning from 3D NAND ©2016 Western Digital Corporation or its affiliates. All rights reserved. 1
- 2. Forward-Looking Statements SAFE HARBOR | DISCLAIMERS ©2016 Western Digital Corporation or its affiliates. All rights reserved. This presentation contains forward-looking statements that involve risks and uncertainties, including, but not limited to, statements regarding our product and technology positioning, the anticipated benefits of our new technologies and transitioning into 3D NAND. Forward-looking statements should not be read as a guarantee of future performance or results, and will not necessarily be accurate indications of the times at, or by, which such performance or results will be achieved, if at all. Forward-looking statements are subject to risks and uncertainties that could cause actual performance or results to differ materially from those expressed in or suggested by the forward-looking statements. Additional key risks and uncertainties include the impact of continued uncertainty and volatility in global economic conditions; actions by competitors; difficulties associated with go-to-market capabilities and transitioning into 3D NAND; business conditions; growth in our markets; and pricing trends and fluctuations in average selling prices. More information about the other risks and uncertainties that could affect our business are listed in our filings with the Securities and Exchange Commission (the “SEC”) and available on the SEC’s website at www.sec.gov, including our and SanDisk’s most recently filed periodic reports, to which your attention is directed. We do not undertake any obligation to publicly update or revise any forward-looking statement, whether as a result of new information, future developments or otherwise, except as otherwise required by law.
- 3. The Western Digital Family of Brands ©2016 Western Digital Corporation or its affiliates. All rights reserved. 3 Bringing the Possibilities of Data to Life
- 4. A Global Leader in Storage Technology $18.3 $15.9 $11.2 $11.2 $10.3 $5.5 $4.8 $3.4 $2.5 LTMRevenue1 (Information Storage) (NAND) (NAND) (NAND)(Storage & Memory) (NAND) 1 LTM revenues based on most recent public filings and Wall Street research; Western Digital and SanDisk LTM as of 4/1/2016; Toshiba represents March 2016 LTM revenue. ©2016 Western Digital Corporation or its affiliates. All rights reserved. 4
- 5. Source: IDC Digital Universe Study, sponsored by EMC, December 2012 Zettabytes of data in 2020 or Terabyte Drives of Data ©2016 Western Digital Corporation or its affiliates. All rights reserved. 5
- 6. Moving Mountains of Data Core Register Core L1 Cache Core L2 Cache Shared L3 Cache DRAM HDD ©2016 Western Digital Corporation or its affiliates. All rights reserved. 6 Source: Western Digital estimates
- 7. BIG DATA Applications >90% misses 96% data transfer The Data Bottleneck Hits Misses Compute Memory Access Conventional Applications <1% misses 10% data transfer CacheAccess SystemEnergy/ TimeConsumption Source: S.Wong, CCD 2015 presentation ©2016 Western Digital Corporation or its affiliates. All rights reserved. 7
- 8. Data Centric Computer Architectures Rack Scale Architecture 100G Ethernet Server Nodes Server Nodes Pooled SCM Server Nodes Pooled Flash JBOD Cheap CPUs Around PB of SCM ©2016 Western Digital Corporation or its affiliates. All rights reserved. 8 AP eDRAM SCM SCM ControllerDDR / New CPU / CS SRAM / eDRAM SSD CNTLR PCIe-NVMe SCM SCM Controller NANDTM DDR / New DRAM / MRAM DDR
- 9. DRAM & NAND Cell Sizes 2000 2005 2010 2015 2020 1,000,000 100,000 10,000 1,000 100 10 Cellsize(nm2)/L DRAM NAND x2 NAND x3 30X ©2016 Western Digital Corporation or its affiliates. All rights reserved. 9 Source: Western Digital estimates
- 10. Moving Mountains of Data Core Register Core L1 Cache Core L2 Cache Shared L3 Cache DRAM HDD ©2016 Western Digital Corporation or its affiliates. All rights reserved. 10 Source: Western Digital estimates
- 11. $10B Market SCM Compute Applications / Market Evolution 2016 2017 2018 2019 2020 2021 Universal Memory SCM Fast Storage DRAM Extension DRAM Displacement ©2016 Western Digital Corporation or its affiliates. All rights reserved. 11 Source: Western Digital estimates
- 12. Storage NAND HDD 0.01 0.1 1 10 AccessTime(sec) 1.E-02 1.E-03 1.E-04 1.E-05 1.E-06 1.E-07 1.E-08 1.E-09 Memory & Storage Hierarchy VolatileNon-Volatile Memory DRAM SRAM STT-MRAM ReRAM Embedded Die Cost ($/GB) PCM Storage-Class Memory ReRAM CBRAM ©2016 Western Digital Corporation or its affiliates. All rights reserved. 12
- 13. Cost Scalability Scale Ecosystem The FAB 4 of Semiconductor Nirvana ©2016 Western Digital Corporation or its affiliates. All rights reserved. 13 Case Study 2D NAND 3D NAND Transition
- 14. 2001 2003 2005 2007 2009 2011 2013 2015 2017 2020 Cost 1Gb, X2-160nm 128Gb, X3 19nm 128Gb, X3 1Ynm 128Gb, X3 1Znm 2Gb, X2-130nm 4Gb, X2-90nm 8Gb, X2-70nm 16Gb, X3-56nm 32Gb, X3-43nm 64Gb, X3 24nm 64Gb, X3-32nm In NAND We Trust: More than Moore OVER 50,000X Cumulative cost reduction over 20 years* Note: Images are not to scale *Based on historical SanDisk NAND pricing 1992* ©2016 Western Digital Corporation or its affiliates. All rights reserved. 14
- 15. When the Chips are Down, the Wafers are Up! Number of wafers produced in 2016 In Yokkaichi How Tall Would it Be? ©2016 Western Digital Corporation or its affiliates. All rights reserved. 15
- 16. When the Chips are Down, the Wafers are Up! Mount Fuji 12,388ft When the Chips are Down, the Wafers are Up! Mount Kilimanjaro 19,340ft Burj Khalifa 2717ft Eiffel Tower 984ft ©2016 Western Digital Corporation or its affiliates. All rights reserved. 16 Number of wafers produced in 2016 In Yokkaichi
- 17. 2D NAND Architecture BL SGD SGS WL Source Plate Floating Gate (memory cell)BL Contact NAND String Si-sub ©2016 Western Digital Corporation or its affiliates. All rights reserved. 17
- 18. Scaling Stopped the Music for 2D NAND! 3D NAND: A necessary revolution ©2016 Western Digital Corporation or its affiliates. All rights reserved. 18 − Cost of lithography − Density of electron storage in the floating gate − Proximity effects from adjacent cells Case Study 2D NAND 3D NAND Transition
- 19. SG SG Control Gate 3D NAND Cell ©2016 Western Digital Corporation or its affiliates. All rights reserved. 19 Poly-Si Body Gate Charge Trap Layer
- 20. 3D NAND Architecture SGD SGS WL Memory Holes Source Plate Memory Cell ©2016 Western Digital Corporation or its affiliates. All rights reserved. 20
- 21. Proximity Effect in BiCS 4X nm 3X nm 2X nm 1X nm BiCS WL Direction BL Direction ProximityEffect ©2016 Western Digital Corporation or its affiliates. All rights reserved. 21
- 22. ©2016 Western Digital Corporation or its affiliates. All rights reserved. 22 World’s first 64-layer 3D NAND architecture Capacities up to 512Gb on a single chip Smallest 256Gb chip in the industry OEM sampling in the current quarter; retail shipments expected in calendar Q4 2016 NAND Cost Scaling Continues Our Next Generation 3D NAND Technology is Here
- 23. The BiCS Scaling March ©2016 Western Digital Corporation or its affiliates. All rights reserved. 23 24L BiCS1 BiCS2 48L BiCS3 64L BiCS5 BiCS4
- 24. 0% 25% 50% 75% 100% Industry 2D NAND vs. 3D NAND Bit Output 2D NAND 3D NAND Manufacturing Scale: Mountains of wafers being converted to 3D NAND 3D Industry bit cross-over in mid-2017 ©2016 Western Digital Corporation or its affiliates. All rights reserved. 24 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2D
- 25. Cost($/GB)[LogScale] 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 ~2x ~20x DRAM SCM BiCS ©2016 Western Digital Corporation or its affiliates. All rights reserved. 25 Cost Scaling for SCM Market Adoption Note: Technology transition cadence assumed 18 months for all technologies ReRAM & 3DXP greenfield fabs, NAND & DRAM existing fabs * DRAM data source: IDC ASP forecast with 45% GM assumed ** 13 nm: assumes EUV @ 1.4x i-ArF capex cost, 2160 w/day
- 26. 3D Technologies for SCM 3D NAND3D XPoint ©2016 Western Digital Corporation or its affiliates. All rights reserved. 26 • Cell and Materials • Selector • Process Architecture • Product • Ecosystem
- 27. Cross Point Memory Implementations 8-layer 3D cross-point array memory ca. 2002 32Gb, 24nm, 2-layer 3D cross-point array ReRAM 2013 ©2016 Western Digital Corporation or its affiliates. All rights reserved. 27
- 28. Latency & Endurance Lower Cost Ecosystem Support Scalability with 3D Scale & Capital Efficiency ©2016 Western Digital Corporation or its affiliates. All rights reserved. 28 3D Resistive RAM as Storage Class Memory 3D ReRAM ReRAM is Western Digital’s Choice for SCM
- 29. 29©2016 Western Digital Corporation or its affiliates. All rights reserved. Summary Data explosion enabled by edge devices 3D NAND: A revolution underway 3D ReRAM is a scalable SCM solution Western Digital + SanDisk: A leading combination Lower latency memory component needed for data-centric computing
- 30. Bringing the possibilities of data to life. ©2016 Western Digital Corporation or its affiliates. All rights reserved.
Editor's Notes
- 3. combined marketshare - storage leader (maybe show the chart that compares our combined revenue to other storage companies)
- JOHN: Have HP picture fill page with the title The Machine, then click and have it fade away and the other two appear and fill the page with a new title “The Future”. Make the RSA graphic prettier so it matches their style. The RSA should be on the right and the other picture on the left, both need to be bigger than they are now.
- Use VN cell size !!!!
- And as we look at the landscape of memory, it is clear that DRAM pricing is a barrier to it becoming a solution to this problem. DRAM, like 2D flash has hit a lithographic scaling physical limit and isn’t able to provide a cost effective solution to architects trying to deal with this Big Data problem. And NAND, while it continues to scale and provide ever more affordable highly responsive storage, doesn’t meet the latency required to keep these data hungry CPUs satisfied. Thus we have see the rise of a new class of memories, dubbed “storage class memory”. This set of technologies provides power and cost efficient memories with latencies in the hundreds of nanoseconds that will both extend CPU cache miss memories while also providing cost efficient DRAM replacement in some applications.
- Flash has been able to keep pace with semiconductor scaling, changing nodes every 13 to 18 months, while moving from single-bit to MLC to three-bit per cell technology. This has allowed flash memory to outpace Moore’s law and reduce cost over 50,000X over the last 20 years. It’s now well-publicized that the scaling pace of planar, or 2D, NAND flash is slowing due to lithography challenges and other device limitations introduced at these extremely dense nodes. There are quantum effects due to the limited electrons, intercell capacitive coupling, and disturb effects from ordinary flash operation. 3D Flash is now taking the lead in furthering the economic gains of memory scaling now by building layers of flash memory cells in the vertical direction. The adverse affects previously mentioned are counteracted by the fact that this scaling can be done economically even at relaxed lithography nodes as I will go through in the next couple slides. While 3D NAND is the focus of most product development at the time, it should be noted that 2D memories still supply the majority today’s flash market while delivering better economics. Comparisons of 15nm X3, or TLC, memories to their 32 layer 3D counterparts show very competitive costs and are delivering competitive products to the market. Without new applications driving flash consumption, Moore’s law doesn’t drive a growing business In order to sustain Moore’s law, significant innovation is needed in our memory and system development
- We need an analogy that compares the # of wafers produced with really tall things. He’ll do it in a 4 part build where he shows a huge pile of wafers on the left, then says…”In 2016 the number of wafers produced by SanDisk would be as tall as?” Eiffel Tower (add the number of feet it is) Burj Khalifa (2,717 feet) Mount Fuji (12,388 feet) Mt Kilimanjaro (19,340 feet)… This is the big AHA cause that’s how many wafers they produce in one year!
- We need an analogy that compares the # of wafers produced with really tall things. He’ll do it in a 4 part build where he shows a huge pile of wafers on the left, then says…”In 2016 the number of wafers produced by SanDisk would be as tall as?” Eiffel Tower (add the number of feet it is) Burj Khalifa (2,717 feet) Mount Fuji (12,388 feet) Mt Kilimanjaro (19,340 feet)… This is the big AHA cause that’s how many wafers they produce in one year!