We are in the big transition from HDD to Flash based SSD drive for intensive data storage industry. This presentation overviews Flash Memory basics, and why it is happening now. This also mentions beyond 3D-NAND Flash memory candidates.

1. HDD TO FLASH & BEYOND
- TECHNOLOGY / CARRIER CHALLENGES -
OCT 18, 2016
SATORU ARAKI
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2. HDD TO FLASH & BEYOND – EXECUTIVE SUMMARY
ØPOSITIONING IN NEXT NEW TECHNOLOGY WAVES
• Data Storage is one of the Key Module in IoT Big Waves, as well as Sensor,
Wireless, Software, and AI
• FLASH has Promising Future in Huge Volume Expansion, because of 3D
Capacity Scalability & Cost Reduction
• However, Storage-Class Memory is emerging to cover DRAM and FLASH area
Ø FLASH MEMORY CHALLENGES
• 3D NAND Continuous Scalability Expansion: >100 by 2020, >500 Layer by
2030 per ITRS2015
• Cost and Performance
Ø EMERGING STORAGE CLASS MEMORY CHALLENGES
• Current Candidates: 3D XPoint, ReRAM, MRAM, FeRAM
• Cost, Scalability, Performance
• Vertical Structure Integration
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3. AGENDA
Ø RECENT FORECAST/FACT STATEMENT
Ø IOT - POSITIONING IN NEXT NEW TECHNOLOGY WAVES
Ø DATA STORAGE HIERARCHY
Ø FLASH MEMORY BASICS
Ø 3D NAND TECHNOLOGY
Ø COMPETITIVE LANDSCAPE
Ø BEYOND 3D NAND – NON VOLATILE MEMORY
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4. RECENT FORECAST/FACT STATEMENTS
Ø IoT – 50 Billion Devices will be connected to the network
Ø IoT Market Scale – $45B in 2020
Ø FLASH Memory Market Scale – $31B in 2015
Ø Data Generation – 44 Zeta Bytes in 2020
Ø Recent Merge & Acquisition Info & Rumors
• Qualcomm -> NXP, $30B
• Softbank -> ARM, $33B
• Renesas -> Intersil, $3B
• WD -> SanDisk, $15B
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IoT Market
Data Generation

5. 3D-NAND POSITION IN NEXT TECHNOLOGY WAVES – MY VIEW
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Big DataAI
Deep Learning
Cloud
Human
Internet
NAND
Flash
Standardization
Control
IoT Sensor SSD
HDD
LinkedIn Ref Page
Generation
§ Sensor
§ Wireless
Storage
§ Memory
§ HDD
Processing
§ Software
Perception
§ AI Deep Learning

6. DATA STORAGE HIERARCHY
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§ FLASH Memory Replaces Performance and Consumer HDD
§ DRAM on Top of the Hierarchy – Very Expensive
§ Persistent (Storage Class) Memory – Emerging to Invade DRAM
Flash
Memory
Performance HDD
Consumer HDD
Ref. 1

7. DATA STORAGE MEMORY HIERARCHY – HDD TO FLASH
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§ Storage-Class Memory Emerging to Cover DRAM Space
§ New Non-Volatile Memory – ReRAM, Phase Change, MRAM
Ref. 2

8. FLASH MEMORY BASICS
§ Modification from MOS-FET, by Inserting Floating Gate
• Injecting Electrons into Floating Gate by Tunneling Effect
§ Multi-Level bits by Controlling Electrons in FG
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Gate
SiO2
Gate: 0 V Gate: +
Source
(N)
Drain
(N)P-type
+-
Gate
SiO2
Source
(N)
Drain
(N)
P-type
+-
+
N
MOS-FET
PN
+-
CG
++ FG ++
Gate: 0 V Gate: +
Source
(N)
Drain
(N)
P-type
+-
CG
- FG -
Source
(N)
Drain
(N)
P-type
+-
+
FLASH
N
Vgate
Vgate
VTH
Dis
VTH
Dis
“1” “0”
VTH
“Multi”
4 bit (QLC) – 16 level
3 bit (TLC) – 8 level
2 bit (MLC) – 4 level
1 bit (SLC) – 2 level

9. WHY 3D-NAND ?
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§ 3D Multilayer Structure Enables Higher Bit Density/area
Charge Trap
(SONOS)
SiO2
Si9N10
SiO2
Poly-Si
source drain
CG
90deg
flip
SiO2
Poly-Si
Si9N10
SiO2 Poly-Si
1
2
3
N-
1
N
V-Channel
(3D)
...
...
Functional Layers by
Vertical Wall Deposition
Ref. 2

10. 3D-NAND DESIGN VARIATIONS
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Design Pipe shaped-BiCS V-NAND Conventional FG
Extended
Sidewall CG
Dual CG w
Surrounding FG
Separated
Sidewall CG
Design
Type Charge Trap Floating Gate
Who Toshiba/SanDisk Samsung Baseline Tohoku Univ 2010 Hynix 2010 Intel/Micron
Pros
§ Higher Scalability
§ Improved Retention
§ Faster Erase Speed
§ Longer Retention
§ Wider Vt Window
§ Reliable MLC op
§ High Speed P/E
§ Wide Read Margin
Cons § Thicker than FG
§ Thicker than FG
§ CT Complexity
§ Interference
§ Disturbance
§ Interference
§ Disturbance
§ High Direct Coupling
Ref. 1

11. SAMSUNG VS INTEL/MICRON IN 32L
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§ FG type (Intel/Micron) may
have thinner stack, plus
better area efficiency than
CT type (Samsung, SanDisk)
§ Area efficiency also better?

12. FLASH PROCESS ROADMAP– COMPETITION
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§ Samsung leads the
competition as 3D volume
production from 2014
§ Toshiba/SanDisk follows
§ Intel/Micron comes up with
new 3D Xpoint in 2016.
Production unknown

13. 3D-NAND POSITIONING IN MEMORY TREND – ITRS2015
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§ Official Roadmap shows 100 Layers in 2020, and continuously
increase >500 Layers in 2030
§ Max Bit may stay in TLC – 3 bit

14. EMERGING STORAGE CLASS MEMORY – BEYOND FLASH
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§ Storage-Class Memory – New Category to Cover Both DRAM & FLASH
§ Non-Volatile
§ Several Candidates as of now: 3D XPoint, ReRAM, MRAM, FeRAM, etc
Storage-Class
Memory
Ref. 1
Key Requirements:
§ Cost
§ Scalability
§ Performance

15. 3D XPOINT BY INTEL/MICRON
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§ 3D XPoint is a ReRAM with Phase Change Material?
Ref. 6

16. Resistive RAM – NON VOLATILE MEMORY
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§ Pros:
ü Simple Device Structure
ü Faster R/W Speed
§ Cons
ü Critical Layer Patterning
ü New Material Development
Ref. 1

17. BEYOND 3D-NAND, 3D XPOINT
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§ 3D Vertical Structure with ReRAM is the GOAL?
3D NAND Process
+
ReRAM
Future Direction ??
ü >100 Layers Possible ?
ü Simple Cell Structure ?
ü Faster Speed ?
Ref. 2

18. MKW VENTURES AT FLASH MEMORY SUMMIT 2016
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Ref. 5

19. 3D-ReRAM – SanDisk View
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§ 3D Multilayer Structure Enables Higher Bit Density/area
Ref. 2

20. TECHNOLOGY & CARRIER CHALLENGES – WHAT CAN WE BRING?
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Challenges
§ Semiconductor Device Experience
§ Device Know-how
§ Product Kow-how
Transferrable Skills
§ Tunnel Barrier Knowhow
§ Thin Film Deposition, Etching Knowhow
§ Reliability Methodology
Challenges
§ No track record in Semi
§ No direct leadership experience
§ Proven Certificate – PMP, PgMP, CSM
§ Experience in Semi, part timer?
Transferrable Carrier
§ Engineering Management Skills
§ Leadership Traits
§ Project, Prog, Prod Management Skills
TECHNOLOGY CARRIER

21. REFERENCES
1. “3D FLASH MEMORIES”, Ed. Rino Micheloni, Springer ISBN 978-94-017-8510-6
2. Siva Sivaram, Keynote-4: Creating Storage Class Memory: Learning from 3D NAND Flash Memory Summit
2016, Link
3. ITRS2015 Executive Summary, Link
4. TECHINSIGHTS, NAND Flash Memory Roadmap, Link
5. Mark Webb, MKW Ventures, Flash Memory Summit 2016, Link
6. Seshubabu Desu, 4DS Memory Limited, Flash Memory Summit 2016, Link
7. Jim Handy, Objective Analysis, Flash Memory Summit 2016, Link
8. Forbes, Roundup Of Internet of Things Forecasts And Market Estimates, 2015, Link
9. Gartner, Press Release, Processing, Sensing and Communications Semiconductor Device Portion of the IoT Is
Set for Rapid Growth, Link
10. ATKearney, Big Data and the Creative Destruction of Today's Business Models, Link
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22. Visual Management Board
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Near-Term Action Item
Responsible
Team Member
Due Date
Completion
Date
M / S / C
Priority
Comments
Create prototype parts kit Jane M. 4/27/09 M Parts missing
Draft test plan out for review Joe P. 5/1/09 5/8/09 S Complete
Complete circuit simulation Cedrick M. 5/1/09 M Need Resources!!
Order injection-mold tooling Joline Q. 5/5/09 M
Meet with key supplier Harry P. 5/10/09 C
Prepare for customer meeting Dave N. 5/10/09 S
Key Milestone
Responsible
Team Member
Planned
Completion
Date
Actual
Completion
Date
Cost
Status
Schedule
Status
Tech.
Status
Comments
Fabricate Prototype David Copperfield 6/7/09 6/7/09 Complete
Prototype Testing Oliver Twist 4/5/09 First Test Failed
Prototype Validated Tiny Tim 3/14/09 May Require Rework
Production Tooling Charles Darney 4/24/09 Supplier Issues
Test Plan Complete Sydney Carton 4/20/09 Resources Unavailable
Final Drawing Release Lucy Mannette 5/17/09
Fabricate Qual Units Charles Dickens 6/14/2009
Planned Work Project Timeline
Unplanned Work
Parking Lot
Week 1 Week 2
Mon Wed Fri Mon Wed Fri
Out
Out Out
Out
Tom
Dick
Harry
Jane
Sally
Mary
Two-Week Action Plan
Risk Management
0
5
10
15
20
25
Months from Project Start
Project“RiskRating”

23. BACK UP
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24. 3D-NAND Flash
- Challenges and Competitive Landscape-
JULY 8, 2016
SATORU ARAKI
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25. 3D Flash Challenges – Executive Summary
§ Positioning in Next New Technology Waves
◦ Promising in volume huge expansion, but 3D capacity scalability & cost are crucial
§ Process Challenges
◦ Reducing process variation in etched hole depth profile and size
◦ Tunneling barrier and charge trap layer material and process optimization
§ Device Challenges
◦ Design optimization for Vthreshold shift and reliability improvement
◦ Design scalability >100 layers
§ Tunneling Barrier Challenges
◦ Opportunity to improve design margin by new materials
§ Competitive Landscape
◦ Samsung ahead in 256 Gb (3D 48-layer TLC) – main battle field in 2016/2017
§ Next Actions in Product Engineering
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26. 3D-NAND Position in Next Technology Waves – my view
Big DataAI
Deep Learning
Cloud
Human
Internet
NAND
Flash
Standardizatio
n
Control
IoT Sensor SSD
HDD
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LinkedIn Ref Page
3D-NAND has Promising Future if;
§ Keep capacity scalability with
§ Cost competitiveness, Reliability

27. 3D Process Challenges
§ V-Connection Through Hole Etching Uniformity
◦ High Aspect Ratio, 48 à 64, 80 layer extendibility, variation minimization
◦ Hole size, depth profile, wall roughness, etc
§ Tunneling Barrier Uniformity for Hole Wall
◦ Key film interface quality improvement
◦ ALD deposition variation minimization in hole depth
◦ Restriction of the barrier material for ALD
§ Charge Trap Layer Material and Properties
◦ Material selection and process optimization
§ Longer Throughput, Lower Yield by 48 à 64, 80 Layer
§ Higher Hole Density due to Deposition Coverage to the Wall
§ Poly-Si Film Quality Improvement
§ Control Gate Lead Fabrication Process Complexity in 48 à 64, 80 Layer
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28. 3D Device Challenges
§ Flash Vthreshold Shift & Profile Widening due to 3D
◦ Need vertical key layer process quality variation minimization
◦ Need thin film physical quality improvement
§ Device Reliability
◦ Degradation delta in Layer-1 to N in Vertical direction
◦ Variation of 3 bit Read Vthreashold profile tails
◦ Charge Trap stable enough over Floating Gate?
§ Cost Competitiveness
◦ Much longer wf cycle time & lower yield against 2D
◦ Process maturity for volume mfg
§ Performance Yield
§ Scalability
◦ 80 layer will be the 3D max? >100 possible?
◦ 4 bit/cell possible?
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29. Tunneling Barrier Challenges
§ Barrier Deposition Process Uniformity
◦ Top to bottom barrier SiO2 thickness variation à S/N, reliability, yield issue
◦ Etching hole diameter / depth profile uniformity à V variation, reliability, yield issue
§ Material Improvement
◦ Many new materials being proposed but may not suitable for 3D: Gd2TiO5, Gd2O3, ZrO2, HfO2, etc
◦ Restriction for depositing to deep aspect ratio holes
◦ Potential to improve it by metal-CVD + oxidation ß TMR lessons in HDD
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Poly-Si
SiO2 SiO2
Si9N10
SiO2
Poly-Si
Floating Gate
(FG)
Charge Trap
(SONOS)
source drain source drain
CG
CG
SiO2
Poly-Si
Si9N10
SiO2 Poly-Si
1
2
3
N-1
N
90deg
flip
V-Channel
(3D)
. . .
. . .
Type Merit
FG SiO2 control
SONOS SiO2/SiN/SiO2/p-Si Faster prog/erase
High-k
Al2O3, La2O3, ZrO2, HfO2,
Gd2TiO5
Faster Prog/erase speed
MOHOS SiO2/Gd2TiO5/SiO2/p-Si
Faster programming/erase
Larger memory window
Tunneling Barrier

30. Competitive Landscape
§ 3D Implementation
◦ 256 Gbit chip production is the main battle field
◦ Samsung will start shipping in 2016
◦ Toshiba/SanDisk 2016/E, announced Fab2 inv and
construction, 3D ratio 50% 2017, 80% 2018
§ Capacity Champion Data
◦ Samsung:
◦ Micron: 768Gb TLC, 3D w/FG at ISSCC Feb, 2016
§ Cell Design per Deposition Steps in 256Gb
◦ Samsung 96, Toshiba/SanDisk 144, Micron 128 - why?
§ Emerging Tech: ReRAM, MRAM, etc
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J.Choe, Flash Memory Summit 2015, Comparison of
2x/1x nm 2D Planar and 3D V-NAND Architecture
§ 2D Production
◦ 75-80% Node 15nm in all Samsung,
Toshiba/SanDisk, Micron/Intel, SK Hynix
◦ Planned Node 9nm in 2018

31. § 256 Gb is the main battle field
◦ Samsung already in production
◦ Toshiba / SanDisk is about to start production this year
◦ Micron / Intel, SK Hynix behind – catching up aggressively
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Gen Date Capacity 3D-Tech Cell Depo Process Status Production Volume Investment Spec
1st Aug/2013 128 Gb MLC 24 layers 20nm
2nd May/2014 128 Gb MLC/TLC 32 layers V-NAND 20nm in Production
3rd Dec/2016 256 Gb TLC 48 layers V-NAND 96 depo 15/16nm Sampling PM971-NVMe, 512GB/p
540/520 MB/s r/w,
98k/90k r/e IOPS
1st
2nd Apr/2016 128 Gb MLC/TLC 32 layers BiCS
3rd Dec/2016 256 Gb TLC 48 layers BiCS 144 depo 15/16nm Sampling
3D production will start at
2016/E. Fab2 const will start
3/2017
2015:0, 2016: start,
2017:50%, 2018:80%
$8B from each, $15B total to
2018 fiscal/E
2015:0, 2016: start,
2017:50%, 2018:80%
64 Gb MLC 25nm
3rd 2016 256/386 Gb, MLC/TLC 32 layers 128 depo
2nd 3Q/2015 128 Gb MLC 36 layers
3rd 2016 48 layers
Samsung
Micron/
Intel
Toshiba/
SanDisk
SK Hynix
Competitive Landscape – cont’d

32. 3D Product Engineering - Next Actions
§ 3D NAND Product Launch – 1st Priority
§ Deeper Collaboration: Milpitas Design / Eng’g Team and Japan Wf Fab Team
◦ Utilize and fuse each team’s cultural strength
◦ Need a coordinator as a “Connection Pin”. How? – here is a ref link. Let’s discuss it later
§ Competitive Benchmarking for Design / Process Feedback
§ Many more ….. Let’s discuss them later on…
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