POWER ANALYSIS OF SLEEPY TRANSISTOR

1. Power Analysis Of Sleepy
Transistor
Associates
-Tushar lohit
- Umesh G
Under the guidance
BY
G.LOKESH

2. ABSTRACT- Static power consumption is a major concern in present technology
for making CMOS VLSI circuit. We present a better designing of
these circuits by introducing Sleepy transistor and reducing the
power consumption by comparing the power analysis of existing
technology and proposed technology.

3. SLEEPY TRANSISTOR
 The sleep transistor turn off the circuit by cutting
off the power rails in idle mode thus can reduce
leakage power effectively.
 These are similar to simple transistors
With high threshold voltge(Vth).

4. CMOS INVERTER CMOS INVERTER USING
SLEEPY TRANSISTOR
Cuts off VDD
from M2
transistor
Cuts of GND
from M1
transistor

5. No of transistor Power
consumption(watt)
W/L value (µm)
CMOS inverter 2 2.25e-004 2.5/.25
CMOS inverter
using sleepy
transistor
4 1.27e-004 1.5/.1
COMPARISON TABLE

6. OUTPUT WAVEFORMS
USING SLEEPY WITHOUT SLEEPY

7. NAND gate NAND gate using
sleepy transistor
INPUT A INPUT B OUTPUT
0 0 1
0 1 1
1 0 1
1 1 0
TRUTH TABLE

8. COMPARISON TABLE
No of transistor Power
consumption
W/L value (µm)
CMOS inverter 4 3.17e-006 2.5/.25
CMOS inverter
using sleepy
transistor
6 2.014e-006 0.3/0.1

9. OUTPUT WAVEFORMS

10. CONCLUSION
We have presented an efficient design methodology for reducing the leakage power in CMOS circuits.
The proposed technique in the thesis is “SLEEPY TRANSISTOR” and comparing the power consumption
with other existing techniques. The proposed technique is more effective in reducing power consumption
even though the number of transistors are increased .

11. REFERENCES
[1] H. Chang and S. S. Sapatnekar, “Full-Chip Analysis of Leakage Power Under Process Variations, Including Spatial
Correlations,” Proc. of the DAC, pp. 523-528, 2005.
[2] R. R. Rao, A. Devgan, D. Blaauw, and D. Sylvester, “Parametric Yield Estimation Considering Leakage
Variability,” Proc. of the DAC, pp. 442-447, 2004.
[3] C. Long and L. He, “Distributed Sleep Transistor Network for Power Reduction,” IEEE Transactions on
VLSI Systems, vol. 12, no. 9, pp. 937-946, Sep. 2004
[4] K. Shi, and D. Howard, “Challenges in Sleep Transistor Design and Implementation in Low-Power Designs,”
Proc. of the DAC, pp. 113-116, 2006.
[5] Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand “Leakage Current Mechanisms and Leakage
Reduction Techniques in Deep Submicrometer CMOS Circuits”, Proceedings of the IEEE, vol. 91, No. 2, February 2003.