by Dr. Amitava Gupta

1. Real-time Embedded Systems Lecture 6 Embedded Communication Part II Prof. Dr. Amitava Gupta Department of Power Engineering Jadavpur University, India Real-time Embedded Systems- Lecture 07

2. Real-time Embedded Systems- Lecture 07 Asynchronous Serial Communication Start bit 5 to 8 data bits 1,1.5 or 2 stop bits Parity bit (optional) The device which does this is a UART Converts bytes to sequence of bits while Tx Converts sequence of bits to bytes while RX

3. Real-time Embedded Systems- Lecture 07 Start bit 5 to 8 data bits 1,1.5 or 2 stop bits Parity bit (optional) UART in operation UART Intel 8251 RX TX Data from Ext. world Data bytes to CPU Data to Ext. world Data bytes from CPU

4. Real-time Embedded Systems- Lecture 07 UART Intel 8251 RX TX Data from Ext. world Data bytes to CPU, CPU does this explicitly Data to Ext. world Data bytes from CPU, CPU does this explicitly UART in operation: Overrun Rx Buffer, data is stored here first Tx Buffer Q. What is underrun? To avoid overrun, the speed at which the CPU reads or write must be matched. Rx and Tx buffers are I/O addressed.

5. Real-time Embedded Systems- Lecture 07 UART Intel 8251 RX TX Data from Ext. world Data bytes to CPU, CPU does this explicitly in a ISR Data to Ext. world Data bytes from CPU, CPU does this explicitly in a ISR Rx Buffer, data is stored here first Tx Buffer UART in operation: Interrupt driven I/O Connected to a IRQ of 8259, Rx ,Tx, Rx+Tx

6. Real-time Embedded Systems- Lecture 07 Discussion on Interrupt driven I/O (chalk and board)