1. Fully described BLOCKS of PP750 . 2. What is PPC? 3. Generations and Features 4. Pipelining 5. Fully described Blocks of PPC 750. 6. Slight comparison b/w PPC and Pentium Processor.

1. Raviraj Kour
( BLOCK DIAGRAM DESCRIPTION )

2. INDEX
 Question?
 What is PPC?
 POWER Architecture
 PPC
 PPC Generations
 Features
 Pipelining
 Block Diagram and description
 PPC Vs. Pentium
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3. QUESTION???
What do the world’s fastest supercomputer, network
and communication equipments such as Internet
routers and switches, the Mars Rover, consumer
electronics such as set top boxes, and the game
consoles all have in common?
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ANSWER
They are powered by microprocessors based on
IBM’s POWER Architecture Instruction Set.

4. What is POWER??
POWER is an old RISC instruction set architecture
designed by IBM. The name is a backronym for :
Performance Optimization With Enhanced RISC
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5. POWER ARCHITECTURE
 Designed by IBM in the late 1980s when that company wanted a
high-performance RISC architecture for their mid-range
workstations and servers.
 First implementation featured in the RS/6000 computers.
 This was the 10-chip RIOS-1 processor, later called POWER1.
 The RISC Single Chip (RSC) processor was developed from
RIOS-1.
 The First RISC Chip Design was 801 CPU.
 Two problems of 801 CPU design :
 No floating point instructions.
 No superscalar architecture used
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6. POWERPC
 Based on IBM's POWER architecture.
 Acronym of POWER Performance Computing.
 Designed by AIM alliance i.e.. Apple, IBM and
Motorola.
 A 32/64-bit instruction set of microprocessors derived
from POWER ISA, including some new elements.
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7. POWERPC GENERATIONS
 G1 - The 601, 500 and 800 family processors.
 G2 - The 602, 603, 604, 620, 8200 and 5000 families.
 G3 - The 750 and 8300 families.
 G4 - The 7400 and 8400* families.
 G5 - The 7500* and 8500 families.
 G6- The 7600*.
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8. FEATURES OF POWERPC
 Superscalar processor.
 Support for operation in both big-endian and little-
endian modes.
 Can switch from one mode to the other at run-time.
 Paged memory management architecture.
 Simple processor design and multiprocessor features.
 64-bit architecture.
 Separate set of FPRs for floating-point instructions.
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9. TOUR TO PPC 750
 Modified version of the POWER architecture.
 High-performance and superscalar microprocessor.
 As many as four instructions can be fetched from the instruction
cache per clock cycle.
 As many as two instructions can be dispatched per clock.
 As many as six instructions can be executed per clock (including
two integer instructions).
 Single-clock-cycle execution for most instructions.
 Six independent execution units and two register files.
 Two integer units (IUs) that share thirty-two GPRs for integer
operands.
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10. Contd…
 Three-stage FPU.
 Two-stage LSU.
 Rename buffers.
 Six GPR rename buffers.
 Six FPR rename buffers.
 Condition register buffering supports two CR writes per
clock.
 Completion unit.
 Guarantees sequential programming model and a
precise exception model.
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11. Contd…
 Power and thermal management :
 Three static modes :
 Doze : All the functional units are disabled except for the time
base/decrementer registers and the bus snooping logic.
 Nap : The nap mode further reduces power consumption by
disabling bus snooping, leaving only the time base register and
the PLL in a powered state.
 Sleep: All internal functional units are disabled, after which
external system logic may disable the PLL and SYSCLK.
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12. PIPELINING
 PowerPC 750 is a pipelined, superscalar processor.
 The FPU and LSU are also multiple-stage pipelines.
 Execution units operate independently and in parallel :
Branch processing unit (BPU).
Integer unit 1 (IU1)—executes all integer instructions
Integer unit 2 (IU2)—executes all integer instructions except
multiplies and divides.
64-bit floating-point unit (FPU).
Load/store unit (LSU).
System register unit (SRU).
PowerPC 750 can execute two instructions on every
clock cycle.
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FIG 1. Pipelining in PowerPC 750

14. Contd…
 In general, it processes instructions in four stages: fetch,
decode/dispatch, execute, and complete.
 PowerPC 750 has six independent execution units, two
for integer instructions, and one each for floating-point
instructions, branch instructions, load/store instructions,
and system register instructions.
 Having separate GPRs and FPRs allows integer,
floating-point calculations, and load and store
operations to occur simultaneously without interference.
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15. BLOCK DIAGRAM
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Fig. 1 : Block Diagram of POWERPC 750

16. DESCRIPTION OF BLOCKS
 Branch processing unit:
 Four instructions fetched per clock.
 One branch processed per cycle.
 Up to 1 speculative stream in execution, 1 additional
speculative stream in fetch.
 512-entry Branch History Table (BHT) for dynamic
prediction.
 64-entry, 4-way set associative Branch Target Instruction
Cache (BTIC) for eliminating branch delay slots.
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17. Contd…
 Dispatch unit:
 Holds as many as six instructions and dispatch two
instructions to six independent units (system, branch,
load/store, fixed-point unit 1, fixed-point unit 2, or floating-
point).
 It continuously attempts to load as many instructions as there
were vacancies created in IQ.
All instructions except branches are dispatched to their
respective EUs.
 Checks for source and destination register dependencies,
allocates rename buffers, determines whether a position is
available in the completion queue, and inhibits subsequent
instruction dispatching if these resources are not available.
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18. Contd…
 Load/store unit :
 One cycle load or store cache access.
 Effective address generation.
 Alignment, zero padding, sign extend for integer register file.
 Floating-point internal format conversion.
 Sequencing for load/store multiples and string operations.
 Store gathering.
 Cache and TLB instructions.
 System unit :
 Logical instructions and miscellaneous system instructions.
Special register transfer instructions.
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19. Contd…
 Fixed-point units :
 Fixed-point unit 1 (FXU1) : multiply, divide, shift, rotate,
arithmetic, logical.
 Fixed-point unit 2 (FXU2) : shift, rotate, arithmetic, logical.
 Single-cycle arithmetic, shift, rotate, logical.
 Multiply and divide support (multi-cycle).
 Early out multiply.
 Floating-point unit :
Support single- and double-precision floating-point arithmetic.
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20. Contd…
 Integrated power management :
Low-power 2.0/3.3V design.
Three static power saving modes: doze, nap, and sleep.
Automatic dynamic power reduction when internal functional units
are idle.
 Cache structure :
32K, 32-byte line, 8-way set associative instruction and data cache.
Single-cycle cache access.
Pseudo-LRU replacement.
Copy-back or write-through data cache.
Supports all PowerPC memory coherency modes.
Non-blocking instruction and data cache.
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21. Contd…
 Bus interface Unit :
Compatible with 60x processor interface.
32-bit address bus with parity checking.
64-bit data bus with parity checking.
Bus-to-core frequency multipliers from 2x to 10x.
 Integrated Thermal Management Assist Unit :
On-chip thermal sensor and control logic.
Thermal Management Interrupts for software regulation of
junction temperature.
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22. Contd…
 Level 2 (L2) cache interface :
 Internal L2 cache controller and 4K-entry tags.
 External data SRAMs.
 256K, 512K, and 1 MB 2-way set associative L2 cache support.
 Copy-back or write-through data cache.
 Supports register-buffer and register-register pipelining.
 Supports Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5
and ÷3.
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23. POWERPC Vs. PENTIUM
Pentium PowerPC 601
 Frequency 66 MHz 66 MHz
 Die Size 264 mm² 120 mm²
 Cache 16K 32K
 Power 14 Watts 9 Watts
 SPECInt92 64 60
 SPECfp92 57 80
 Price $950.00 $450.00
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24. REFERENCES
 http://www.mactech.com/articles/mactech/Vol.10/10.02/ThePowerPC
/index.html
 http://www-03.ibm.com/chips/products/powerpc/
 http://en.wikipedia.org/wiki/PowerPC
 http://nptel.ac.in/courses/Webcourse-contents/IIT-
KANPUR/microcontrollers/micro/ui/Course_home4_36.htm
 Fact Sheet - Motorola PowerPC Processor
 International Business Machines Corporation 2001, 2002 (Printed in
the United States of America 9/02)
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