International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
High Speed Fault Injection Tool (FITO) Implemented With VHDL on FPGA For Test...IJMER
This document describes a high speed fault injection tool (FITO) implemented on an FPGA for testing fault tolerant designs. FITO supports injecting different fault models like permanent faults, transient faults, and bit flips. It modifies VHDL design descriptions to insert extra logic for fault injection controlled by a fault injection signal (FIS). The fault injection manager schedules faults and asserts FIS. It was implemented using VHDL and tested on a Spartan-3E FPGA board using a redundant ALU processor design. FITO aims to provide high speed fault injection with good controllability and observability for evaluating fault tolerance of FPGA-based systems.
Programming of the ATE for Fuze calibration using Lab View Softwareijsrd.com
The FUZE is a self-powered radio transmitting and receiving unit, operating on Doppler principle. The HF circuit in Fuze is responsible for the proximity mode operation. During dynamic testing, all the parameters and their values are noted which are then used in anechoic box (static testing) as a reference reading for testing of FB40 Fuze. The anechoic box is connected to HF test station which guides the entire test to be performed on Fuze. The programming is done in LabView software. The tests are coded in LabView and then implemented on the test station to check the proper functioning of the Fuze.
Agilent flash programming agilent utility card versus deep serial memory-ca...AgilentT&M EMEA
This case study compares the flash programming performances of the Agilent Medalist i3070 Series (http://bit.ly/16hd1as) 5 in-circuit tester (ICT) with utility card flash programming solution against the Teradyne in-circuit tester with deep serial memory programming solution
An integrated approach for designing and testing specific processorsVLSICS Design
This paper proposes a validation method for the des
ign of a CPU on which, in parallel with the
development of the CPU, it is also manually describ
ed a testbench that performs automated testing on t
he
instructions that are being described. The testbenc
h consists of the original program memory of the CP
U
and it is also coupled to the internal registers, P
ORTS, stack and other components related to the pro
ject.
The program memory sends the instructions requested
by the processor and checks the results of its
instructions, progressing or not with the tests. Th
e proposed method resulted in a CPU compatible with
the
instruction set and the CPU registers present into
the PIC16F628 microcontroller. In order to shows th
e
usability and success of the depuration method empl
oyed, this work shows that the CPU developed is
capable of running real programs generated by compi
lers existing on the market. The proposed CPU was
mapped in FPGA, and using Cadence tools, was synthe
sized on silicon.
A Unique Test Bench for Various System-on-a-Chip IJECEIAES
This paper discusses a standard flow on how an automated test bench environment which is randomized with constraints can verify a SOC efficiently for its functionality and coverage. Today, in the time of multimillion gate ASICs, reusable intellectual property (IP), and system-ona-chip (SoC) designs, verification consumes about 70 % of the design effort. Automation means a machine completes a task autonomously, quicker and with predictable results. Automation requires standard processes with welldefined inputs and outputs. By using this efficient methodology it is possible to provide a general purpose automation solution for verification, given today’s technology. Tools automating various portions of the verification process are being introduced. Here, we have Communication based SOC The content of the paper discusses about the methodology used to verify such a SOC-based environment. Cadence Efficient Verification Methodology libraries are explored for the solution of this problem. We can take this as a state of art approach in verifying SOC environments. The goal of this paper is to emphasize the unique testbench for different SOC using Efficient Verification Constructs implemented in system verilog for SOC verification.
The document presents a comparative analysis of different fault injection methods using on-chip debug (OCD) infrastructures. It describes experiments conducted using a Freescale MPC-565 microprocessor with enhanced OCD capabilities. The experiments compare basic, extended, and OCD-enhanced fault injection configurations across offline and real-time scenarios. Results show that the OCD-enhanced method enables higher fault detection rates with lower performance overhead compared to other approaches.
1. The document proposes developing an intelligent measurement system using machine learning to improve detection rates for defects in steel strips and enable adaptive adjustment of measurement systems.
2. Key aspects include using machine learning models for defect classification and intelligent control of measurement parameters. This aims to increase accuracy and precision while accommodating flexible manufacturing.
3. Measurement data would be uploaded to the cloud and analyzed using intelligent algorithms and big data to provide condition-based maintenance recommendations and predictions to decrease downtime.
What is Microcontroller, Microcontroller vs Microprocessor, Development/Classication of microcontrollers, Harvard vs. Princeton Architecture, RISC AND CISC CONTROLLERS
Features of RISC, Microcontroller for Embedded Systems
10 x86 PC Embedded Applications, Choosing a Microcontroller
Criteria for Choosing a Microcontroller, Mechatronics, and Microcontrollers, A brief history of the PIC microcontroller, PIC Microcontrollers, Feature: PIC16F877, Simplied Features.
High Speed Fault Injection Tool (FITO) Implemented With VHDL on FPGA For Test...IJMER
This document describes a high speed fault injection tool (FITO) implemented on an FPGA for testing fault tolerant designs. FITO supports injecting different fault models like permanent faults, transient faults, and bit flips. It modifies VHDL design descriptions to insert extra logic for fault injection controlled by a fault injection signal (FIS). The fault injection manager schedules faults and asserts FIS. It was implemented using VHDL and tested on a Spartan-3E FPGA board using a redundant ALU processor design. FITO aims to provide high speed fault injection with good controllability and observability for evaluating fault tolerance of FPGA-based systems.
Programming of the ATE for Fuze calibration using Lab View Softwareijsrd.com
The FUZE is a self-powered radio transmitting and receiving unit, operating on Doppler principle. The HF circuit in Fuze is responsible for the proximity mode operation. During dynamic testing, all the parameters and their values are noted which are then used in anechoic box (static testing) as a reference reading for testing of FB40 Fuze. The anechoic box is connected to HF test station which guides the entire test to be performed on Fuze. The programming is done in LabView software. The tests are coded in LabView and then implemented on the test station to check the proper functioning of the Fuze.
Agilent flash programming agilent utility card versus deep serial memory-ca...AgilentT&M EMEA
This case study compares the flash programming performances of the Agilent Medalist i3070 Series (http://bit.ly/16hd1as) 5 in-circuit tester (ICT) with utility card flash programming solution against the Teradyne in-circuit tester with deep serial memory programming solution
An integrated approach for designing and testing specific processorsVLSICS Design
This paper proposes a validation method for the des
ign of a CPU on which, in parallel with the
development of the CPU, it is also manually describ
ed a testbench that performs automated testing on t
he
instructions that are being described. The testbenc
h consists of the original program memory of the CP
U
and it is also coupled to the internal registers, P
ORTS, stack and other components related to the pro
ject.
The program memory sends the instructions requested
by the processor and checks the results of its
instructions, progressing or not with the tests. Th
e proposed method resulted in a CPU compatible with
the
instruction set and the CPU registers present into
the PIC16F628 microcontroller. In order to shows th
e
usability and success of the depuration method empl
oyed, this work shows that the CPU developed is
capable of running real programs generated by compi
lers existing on the market. The proposed CPU was
mapped in FPGA, and using Cadence tools, was synthe
sized on silicon.
A Unique Test Bench for Various System-on-a-Chip IJECEIAES
This paper discusses a standard flow on how an automated test bench environment which is randomized with constraints can verify a SOC efficiently for its functionality and coverage. Today, in the time of multimillion gate ASICs, reusable intellectual property (IP), and system-ona-chip (SoC) designs, verification consumes about 70 % of the design effort. Automation means a machine completes a task autonomously, quicker and with predictable results. Automation requires standard processes with welldefined inputs and outputs. By using this efficient methodology it is possible to provide a general purpose automation solution for verification, given today’s technology. Tools automating various portions of the verification process are being introduced. Here, we have Communication based SOC The content of the paper discusses about the methodology used to verify such a SOC-based environment. Cadence Efficient Verification Methodology libraries are explored for the solution of this problem. We can take this as a state of art approach in verifying SOC environments. The goal of this paper is to emphasize the unique testbench for different SOC using Efficient Verification Constructs implemented in system verilog for SOC verification.
The document presents a comparative analysis of different fault injection methods using on-chip debug (OCD) infrastructures. It describes experiments conducted using a Freescale MPC-565 microprocessor with enhanced OCD capabilities. The experiments compare basic, extended, and OCD-enhanced fault injection configurations across offline and real-time scenarios. Results show that the OCD-enhanced method enables higher fault detection rates with lower performance overhead compared to other approaches.
1. The document proposes developing an intelligent measurement system using machine learning to improve detection rates for defects in steel strips and enable adaptive adjustment of measurement systems.
2. Key aspects include using machine learning models for defect classification and intelligent control of measurement parameters. This aims to increase accuracy and precision while accommodating flexible manufacturing.
3. Measurement data would be uploaded to the cloud and analyzed using intelligent algorithms and big data to provide condition-based maintenance recommendations and predictions to decrease downtime.
What is Microcontroller, Microcontroller vs Microprocessor, Development/Classication of microcontrollers, Harvard vs. Princeton Architecture, RISC AND CISC CONTROLLERS
Features of RISC, Microcontroller for Embedded Systems
10 x86 PC Embedded Applications, Choosing a Microcontroller
Criteria for Choosing a Microcontroller, Mechatronics, and Microcontrollers, A brief history of the PIC microcontroller, PIC Microcontrollers, Feature: PIC16F877, Simplied Features.
IRJET- PCB Test, Debug & Programming Made Easy with Universal Test JigIRJET Journal
This document discusses a universal test jig that uses XJTAG technology to test printed circuit boards. XJTAG allows testing, troubleshooting, and programming of PCBs containing both JTAG and non-JTAG devices. The universal test jig includes an I/O board connected to an XJLink 2.0 adapter to interface between the computer and device under test on the PCB. XJDeveloper software is used to develop and execute test programs, while the XJLink 2.0 hardware connects to the computer via USB to drive signals to and from the device under test.
This document discusses using JTAG (Joint Test Action Group) testing to test system-on-chip (SoC) interconnects. It proposes adding boundary scan cells to interconnect wires to test for faults like opens, shorts, and crosstalk-induced signal integrity issues. An Integrity Loss Sensor Cell is described that can detect voltage and delay violations. Experimental results show these sensor cells add only modest area overhead. The approach extends standard JTAG to enable comprehensive testing of SoC interconnects.
Join this video course on Udemy. Click the below link
https://www.udemy.com/mastering-rtos-hands-on-with-freertos-arduino-and-stm32fx/?couponCode=SLIDESHARE
>> The Complete FreeRTOS Course with Programming and Debugging <<
"The Biggest objective of this course is to demystifying RTOS practically using FreeRTOS and STM32 MCUs"
STEP-by-STEP guide to port/run FreeRTOS using development setup which includes,
1) Eclipse + STM32F4xx + FreeRTOS + SEGGER SystemView
2) FreeRTOS+Simulator (For windows)
Demystifying the complete Architecture (ARM Cortex M) related code of FreeRTOS which will massively help you to put this kernel on any target hardware of your choice.
The document discusses processes and inter-process communication (IPC). It describes how processes can be independent or cooperating. Cooperating processes require an IPC mechanism to exchange data and information, which can take two forms: shared memory or message passing. Shared memory involves processes accessing the same memory region, while message passing involves processes explicitly sending and receiving messages. The document provides examples of using shared memory and message passing for a producer-consumer problem.
The document discusses input/output (I/O) systems. It describes how I/O devices connect to computers through ports, busses, and device controllers. Device drivers present a uniform interface to access devices. Common I/O hardware concepts are discussed, including polling and interrupt-driven interactions between processors and controllers. Interrupt vectors route interrupts to specific handler routines. Interrupts are also used for exceptions and system calls.
Vulnerabilities analysis of fault and Trojan attacks in FSMKurra Gopi
The security of the whole system can be compromised if there
are vulnerabilities in the FSM.
I These vulnerabilities can be created by improper designs or by the
synthesis tool which introduces additional dont care states and transitions
during the optimization and synthesis process.
I An attacker can utilize these vulnerabilities to perform fault injection
attacks or insert malicious hardware modications (Trojan) to gain
unauthorized access to some specic states.
The document provides a summary of Michael Joshua S's professional experience and skills. It summarizes over 12 years of experience in embedded systems testing and validation across various industries. Key roles included consulting test engineer, team lead, and project engineer. Technical skills include test automation using National Instruments hardware and software, system engineering, verification and validation, and embedded software development.
AdaCore Paris Tech Day 2016: Elie Richa - Integrated Unit Testing for a Trust...jamieayre
1) An automatic code generator (ACG) produces source code from a model specification but must undergo rigorous testing to be qualified and trusted.
2) Integrated unit testing is proposed to achieve the exhaustiveness of unit testing using only integration tests by instrumenting the ACG with ghost code to monitor test coverage and results during integration testing.
3) The approach generates a large set of integration tests from block specifications to thoroughly cover the many configurations, allowing unit tests to be evaluated without editing intermediate languages.
Microcontroller based Integrated Circuit TesterIJERA Editor
The digital integrated circuit (IC) tester is implemented by using the ATmega32 microcontroller . The microcontroller processes the inputs and outputs and displays the results on a Liquid Crystal Display (LCD). The basic function of the digital IC tester is to test a digital IC for correct logical functioning as described in the truth table and/or function table. The designed model can test digital ICs having 14 pins. Since it is programmable, any number of ICs can be tested . This model applies the necessary signals to the inputs of the IC, monitoring the outputs at each stage and comparing them with the outputs in the truth table. Any discrepancy in the functioning of the IC results in a fail indication, displays the faulty and good gates on the LCD. The testing procedure is accomplished with the help of keypad keys present on the main board design. The test has been accomplished with most commonly used digital IC's, mainly belonging to the 74 series. Digital IC tester tests three samples of IC's ( NAND, NOT, NOR). The design is flexible . We can add extra IC bases and subroutines to test any other IC in the 74 series.
JTAG (Joint Test Action Group) is a standard interface that allows testing and debugging of printed circuit boards and embedded systems. It enables boundary scan testing which allows control and observation of pin states without physical test probes. The JTAG standard defines a Test Access Port with four pins for control and data. This allows instructions and test data to be serially loaded to test interconnects and perform built-in self-tests of chips on the board. Boundary scan cells are included in JTAG chips to intercept pin states for testing.
The document discusses the building blocks of a SystemVerilog testbench. It describes the program block, which encapsulates test code and allows reading/writing signals and calling module routines. Interface and clocking blocks are used to connect the testbench to the design under test. Assertions, randomization, and other features help create flexible testbenches to verify design correctness.
Design, Implementation and Security Analysis of Hardware Trojan Threats in FPGAVivek Venugopalan
This document discusses hardware Trojan threats in FPGAs. It proposes a novel metric called the Hardware Trojan Threat Detectability Metric (HDM) that uses weighted physical parameters to detect Trojans. Several Trojans were designed and implemented in an FPGA testbed to compromise systems. HDM increased detection rates to 86% compared to 57% using single parameters. The document analyzes potential attack surfaces in FPGAs and discusses optimization of Trojans to avoid detection.
IEEE P1581 provides a standard method for testing interconnects of complex memory ICs without requiring additional test pins. It specifies implementation rules for simple test logic and transparent test mode entry/exit methods. Key features include fast testing with small test vectors without needing complex memory access or additional pins. Test mode is entered via a dedicated test pin, one of seven transparent test mode control methods, or optional test functions. The standard aims to improve testing of memory devices on printed circuit boards.
Introduction to Operating Systems - Part3Amir Payberah
The document discusses the structure and functions of operating systems. It describes how operating systems have two main spaces: user space for application programs and system space for the kernel. The kernel is responsible for core functions like process management, memory management, file systems, device control and security. System calls provide an interface for programs to access OS services, and are usually accessed through high-level APIs rather than direct calls. Common APIs include POSIX, Win32 and Java. Parameters are typically passed to system calls via registers, memory blocks or the stack. Major categories of system calls control processes, files, devices, system information and security.
This lab document instructs students on how to set up serial communication between a microcontroller kit and a computer using a USB-to-UART adapter. Students will write code to recognize keyboard inputs from the computer, perform operations on the microcontroller kit, and display messages back on the computer terminal. The document provides details on installing driver software for the USB adapter, connecting the kit to the adapter, and using terminal software to interface with the kit and see input/output. Students are given code templates and tasks to test interfacing with the LCD display and LEDs on the kit in response to keyboard inputs.
Introduction to Operating Systems - Part2Amir Payberah
The document discusses computer system architecture and operating system structure. It describes multiprocessor systems, multicore systems, and blade servers. It then covers operating system concepts like multiprogramming, timesharing, and dual-mode operation. It outlines the major components of an operating system including user space programs, system programs, and the kernel. Key kernel functions like process management, memory management, storage/file systems, device control, and security are also summarized.
An application specific reconfigurable architecture for fault testing and dia...eSAT Journals
This document discusses application-specific reconfigurable architectures for fault testing and diagnosis in FPGAs. It provides an overview of different types of faults that can occur in FPGAs at runtime, including logical faults, interconnect faults, and delay faults. It then reviews several previous works that proposed various techniques for application-independent and application-dependent fault diagnosis in FPGAs, focusing on methods for detecting and locating logical faults and interconnect faults. The goal is to remove faults at the application level to improve FPGA performance and reliability.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
The document discusses interrupts in the 8051 microcontroller. It introduces the different types of interrupts including timer interrupts, external hardware interrupts, and serial communication interrupts. It describes how interrupts work, from triggering an interrupt service routine to exiting the routine. Special function registers like the interrupt enable register and interrupt priority register are discussed for configuring and handling interrupts. Examples of interrupt programming in assembly language are provided.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IRJET- PCB Test, Debug & Programming Made Easy with Universal Test JigIRJET Journal
This document discusses a universal test jig that uses XJTAG technology to test printed circuit boards. XJTAG allows testing, troubleshooting, and programming of PCBs containing both JTAG and non-JTAG devices. The universal test jig includes an I/O board connected to an XJLink 2.0 adapter to interface between the computer and device under test on the PCB. XJDeveloper software is used to develop and execute test programs, while the XJLink 2.0 hardware connects to the computer via USB to drive signals to and from the device under test.
This document discusses using JTAG (Joint Test Action Group) testing to test system-on-chip (SoC) interconnects. It proposes adding boundary scan cells to interconnect wires to test for faults like opens, shorts, and crosstalk-induced signal integrity issues. An Integrity Loss Sensor Cell is described that can detect voltage and delay violations. Experimental results show these sensor cells add only modest area overhead. The approach extends standard JTAG to enable comprehensive testing of SoC interconnects.
Join this video course on Udemy. Click the below link
https://www.udemy.com/mastering-rtos-hands-on-with-freertos-arduino-and-stm32fx/?couponCode=SLIDESHARE
>> The Complete FreeRTOS Course with Programming and Debugging <<
"The Biggest objective of this course is to demystifying RTOS practically using FreeRTOS and STM32 MCUs"
STEP-by-STEP guide to port/run FreeRTOS using development setup which includes,
1) Eclipse + STM32F4xx + FreeRTOS + SEGGER SystemView
2) FreeRTOS+Simulator (For windows)
Demystifying the complete Architecture (ARM Cortex M) related code of FreeRTOS which will massively help you to put this kernel on any target hardware of your choice.
The document discusses processes and inter-process communication (IPC). It describes how processes can be independent or cooperating. Cooperating processes require an IPC mechanism to exchange data and information, which can take two forms: shared memory or message passing. Shared memory involves processes accessing the same memory region, while message passing involves processes explicitly sending and receiving messages. The document provides examples of using shared memory and message passing for a producer-consumer problem.
The document discusses input/output (I/O) systems. It describes how I/O devices connect to computers through ports, busses, and device controllers. Device drivers present a uniform interface to access devices. Common I/O hardware concepts are discussed, including polling and interrupt-driven interactions between processors and controllers. Interrupt vectors route interrupts to specific handler routines. Interrupts are also used for exceptions and system calls.
Vulnerabilities analysis of fault and Trojan attacks in FSMKurra Gopi
The security of the whole system can be compromised if there
are vulnerabilities in the FSM.
I These vulnerabilities can be created by improper designs or by the
synthesis tool which introduces additional dont care states and transitions
during the optimization and synthesis process.
I An attacker can utilize these vulnerabilities to perform fault injection
attacks or insert malicious hardware modications (Trojan) to gain
unauthorized access to some specic states.
The document provides a summary of Michael Joshua S's professional experience and skills. It summarizes over 12 years of experience in embedded systems testing and validation across various industries. Key roles included consulting test engineer, team lead, and project engineer. Technical skills include test automation using National Instruments hardware and software, system engineering, verification and validation, and embedded software development.
AdaCore Paris Tech Day 2016: Elie Richa - Integrated Unit Testing for a Trust...jamieayre
1) An automatic code generator (ACG) produces source code from a model specification but must undergo rigorous testing to be qualified and trusted.
2) Integrated unit testing is proposed to achieve the exhaustiveness of unit testing using only integration tests by instrumenting the ACG with ghost code to monitor test coverage and results during integration testing.
3) The approach generates a large set of integration tests from block specifications to thoroughly cover the many configurations, allowing unit tests to be evaluated without editing intermediate languages.
Microcontroller based Integrated Circuit TesterIJERA Editor
The digital integrated circuit (IC) tester is implemented by using the ATmega32 microcontroller . The microcontroller processes the inputs and outputs and displays the results on a Liquid Crystal Display (LCD). The basic function of the digital IC tester is to test a digital IC for correct logical functioning as described in the truth table and/or function table. The designed model can test digital ICs having 14 pins. Since it is programmable, any number of ICs can be tested . This model applies the necessary signals to the inputs of the IC, monitoring the outputs at each stage and comparing them with the outputs in the truth table. Any discrepancy in the functioning of the IC results in a fail indication, displays the faulty and good gates on the LCD. The testing procedure is accomplished with the help of keypad keys present on the main board design. The test has been accomplished with most commonly used digital IC's, mainly belonging to the 74 series. Digital IC tester tests three samples of IC's ( NAND, NOT, NOR). The design is flexible . We can add extra IC bases and subroutines to test any other IC in the 74 series.
JTAG (Joint Test Action Group) is a standard interface that allows testing and debugging of printed circuit boards and embedded systems. It enables boundary scan testing which allows control and observation of pin states without physical test probes. The JTAG standard defines a Test Access Port with four pins for control and data. This allows instructions and test data to be serially loaded to test interconnects and perform built-in self-tests of chips on the board. Boundary scan cells are included in JTAG chips to intercept pin states for testing.
The document discusses the building blocks of a SystemVerilog testbench. It describes the program block, which encapsulates test code and allows reading/writing signals and calling module routines. Interface and clocking blocks are used to connect the testbench to the design under test. Assertions, randomization, and other features help create flexible testbenches to verify design correctness.
Design, Implementation and Security Analysis of Hardware Trojan Threats in FPGAVivek Venugopalan
This document discusses hardware Trojan threats in FPGAs. It proposes a novel metric called the Hardware Trojan Threat Detectability Metric (HDM) that uses weighted physical parameters to detect Trojans. Several Trojans were designed and implemented in an FPGA testbed to compromise systems. HDM increased detection rates to 86% compared to 57% using single parameters. The document analyzes potential attack surfaces in FPGAs and discusses optimization of Trojans to avoid detection.
IEEE P1581 provides a standard method for testing interconnects of complex memory ICs without requiring additional test pins. It specifies implementation rules for simple test logic and transparent test mode entry/exit methods. Key features include fast testing with small test vectors without needing complex memory access or additional pins. Test mode is entered via a dedicated test pin, one of seven transparent test mode control methods, or optional test functions. The standard aims to improve testing of memory devices on printed circuit boards.
Introduction to Operating Systems - Part3Amir Payberah
The document discusses the structure and functions of operating systems. It describes how operating systems have two main spaces: user space for application programs and system space for the kernel. The kernel is responsible for core functions like process management, memory management, file systems, device control and security. System calls provide an interface for programs to access OS services, and are usually accessed through high-level APIs rather than direct calls. Common APIs include POSIX, Win32 and Java. Parameters are typically passed to system calls via registers, memory blocks or the stack. Major categories of system calls control processes, files, devices, system information and security.
This lab document instructs students on how to set up serial communication between a microcontroller kit and a computer using a USB-to-UART adapter. Students will write code to recognize keyboard inputs from the computer, perform operations on the microcontroller kit, and display messages back on the computer terminal. The document provides details on installing driver software for the USB adapter, connecting the kit to the adapter, and using terminal software to interface with the kit and see input/output. Students are given code templates and tasks to test interfacing with the LCD display and LEDs on the kit in response to keyboard inputs.
Introduction to Operating Systems - Part2Amir Payberah
The document discusses computer system architecture and operating system structure. It describes multiprocessor systems, multicore systems, and blade servers. It then covers operating system concepts like multiprogramming, timesharing, and dual-mode operation. It outlines the major components of an operating system including user space programs, system programs, and the kernel. Key kernel functions like process management, memory management, storage/file systems, device control, and security are also summarized.
An application specific reconfigurable architecture for fault testing and dia...eSAT Journals
This document discusses application-specific reconfigurable architectures for fault testing and diagnosis in FPGAs. It provides an overview of different types of faults that can occur in FPGAs at runtime, including logical faults, interconnect faults, and delay faults. It then reviews several previous works that proposed various techniques for application-independent and application-dependent fault diagnosis in FPGAs, focusing on methods for detecting and locating logical faults and interconnect faults. The goal is to remove faults at the application level to improve FPGA performance and reliability.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
The document discusses interrupts in the 8051 microcontroller. It introduces the different types of interrupts including timer interrupts, external hardware interrupts, and serial communication interrupts. It describes how interrupts work, from triggering an interrupt service routine to exiting the routine. Special function registers like the interrupt enable register and interrupt priority register are discussed for configuring and handling interrupts. Examples of interrupt programming in assembly language are provided.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This document summarizes a research paper on a bidirectional DC-DC converter with a Z-source network. The proposed converter aims to increase the output voltage level and regulation range compared to traditional bidirectional converters. It uses a fully bridge symmetrical circuit configuration with voltage and current sources. Simulation results using MATLAB show the converter can reduce current stress and improve efficiency for applications in hybrid electric vehicles and renewable energy systems. Key aspects analyzed include the converter's operating principles, voltage regulation model, and simulation circuit and results demonstrating operation in forward and reverse modes.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Dokumen tersebut membahas tentang pengucapan dan artikulasi huruf dalam bahasa Indonesia. Terdapat penjelasan mengenai bunyi yang dihasilkan oleh alat ucap, vokal, konsonan, dan gugus konsonan.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This lesson plan covers drawing triangles as homework, with an aim to prepare students for an exam on Friday about Module 6, Lesson 8. It directs students to complete an opening exercise on page S.40 of their textbook and do now work, in order to study for an exam on drawing triangles this coming Friday.
Practica 6 complementos del diseños de un docuementoRoberto Duarte
Este documento resume el libro "Los Hornos de Hitler" de Olga Lengyel, un testimonio de primera mano de su experiencia como prisionera en los campos de concentración nazis de Auschwitz y Birkenau. Describe su llegada al campo, la separación de su familia, las crueles condiciones de vida y la constante amenaza de ser enviada a las cámaras de gas. Más adelante, forma parte de la resistencia en el campo ayudando a distribuir cartas y mantener la esperanza entre las prisioneras. Su relato ofrece detal
Este documento proporciona información sobre una institución educativa venezolana. Se trata del Instituto Universitario de Tecnología Antonio José de Sucre en Barquisimeto, estado Falcón. Ofrece programas de estudio en administración de empresas.
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El documento presenta un proyecto de intervención educativa que utiliza las tecnologías de la información y comunicación (TIC) como herramientas de apoyo para el aprendizaje en una escuela primaria vespertina en México. El proyecto incluyó un diagnóstico previo, la implementación de un juego interactivo y el uso de videos e imágenes para reforzar los conocimientos de los alumnos. El documento también revisa marcos teóricos relacionados con el uso pedagógico de las TIC y conceptos como la brecha digital
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Design of Fuzzy PID controller to control DC motor with zero overshootIJERA Editor
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Microcontroller Based Testing of Digital IP-CoreVLSICS Design
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White paper - Robust firmware development for wind applications through HiL/S...Ingeteam Wind Energy
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DESIGN APPROACH FOR FAULT TOLERANCE IN FPGA ARCHITECTUREVLSICS Design
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Implementation of 32 Bit Binary Floating Point Adder Using IEEE 754 Single Pr...iosrjce
Field Programmable Gate Arrays (FPGA) are increasingly being used to design high- end
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Greybox fuzzing methods to find security vulnerabilities in software systems are discussed in this talk. We discuss how fuzz testing methods can be inspired by ideas from symbolic execution and model checking to go beyond conventional fuzzing methods, without sacrificing the efficiency of fuzzing.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
DOUBLE PRECISION FLOATING POINT CORE IN VERILOGIJCI JOURNAL
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IRJET- FPGA Implementation of an Improved Watchdog Timer for Safety-Critical ...IRJET Journal
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The Role Of Software And Hardware As A Common Part Of The...Sheena Crouch
This document discusses the implementation of a software-defined networking (SDN) system using Field Programmable Gate Arrays (FPGAs). It describes an SDN switch core that can modify packet headers based on flow tables and forward packets to different ports. An SDN controller programmed the flow tables and monitored packet flows. Attacker nodes, implemented with a Microblaze processor, transmitted packets to the SDN switch network at programmable rates. The system allowed observation and testing of the SDN switches and network. Hardware and software implementations are discussed to realize the SDN system on FPGAs.
IRJET - Design and Implementation of Double Precision FPU for Optimised SpeedIRJET Journal
This document describes the design and implementation of a double precision floating point unit (FPU) for optimized speed. It discusses the need for high-speed arithmetic operations in applications such as digital signal processing. It presents the architecture of the proposed FPU, which includes blocks for floating point multiplication and addition. It also discusses the implementation of pipelined 64-bit floating point multiplication and addition units using techniques like carry lookahead addition and hybrid multiplication. Simulation results on a FPGA platform show that the proposed pipelined design achieves higher throughput than existing non-pipelined approaches.
This document describes the simulation of a requester device using VHDL to enable Ethernet communication. The requester device is designed to transmit and receive data through GPIO ports to allow connection to external devices. It consists of GPIO to FIFO and FIFO to GPIO blocks to transfer data between the ports and FIFO memory. The device is simulated using ModelSim software. The simulation demonstrates the forwarding of data from GPIO input to output through the FIFO blocks, showing it can function as a mediator for data transfer required for Ethernet communication platforms.
Design of Multiplier Less 32 Tap FIR Filter using VHDLIJMER
This Paper provide the principles of Distributed Arithmetic, and introduce it into the FIR
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system speed. The implementation of FIR filters on FPGA based on traditional method costs considerable
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It is very well known that the FIR filter consists of Delay elements, Multipliers and Adders. Because of
usage of Multipliers in early design gives rise to 2 demerits that are:
(i) Increase in Area and
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So the Distributed Arithmetic for FIR Filter design and Implementation is provided in this work to solve
this problem. Distributed Arithmetic structure is used to increase the recourse usage and pipeline
structure is used to increase the system speed. Distributed Arithmetic can save considerable hardware
resources through using LUT to take the place of MAC units
This document presents a reusable test infrastructure for verifying RTL designs using a mixed-language and mixed-level integration approach based on the IP-XACT standard. The test infrastructure is implemented primarily in SystemC TLM2 with a small part in VHDL. It includes configurable components like a processor, memory, peripherals and bus. A case study is described where the infrastructure is used to verify a microcontroller design with interfaces like I2C, SPI and UART through randomized software verification. The infrastructure can be automatically generated from an IP-XACT description based on user-provided configuration values.
This document describes a chemical extraction system controlled by an FPGA programmed using VHDL. The system extracts acetone from a water/acetone solution based on the different boiling points. The FPGA controls valves and monitors temperature and concentration sensors. A VHDL program was developed and divided into four parts to control the system. The program was synthesized and downloaded to the FPGA. The system successfully extracted 99% pure acetone by opening and closing valves based on sensor readings. FPGAs provide facilities to control systems in parallel, allowing control of many elements with minimal delay.
Stepper motor movement design based on FPGA IJECEIAES
A stepper motor is an electro mechanical device that can convert electrical pulses to the axis of movement. The finding problem in the movement of a stepper motor is cannot respond to the clock signal directly because the motor windings require a clock (sequence) in the correct order. If the control signal given is not correct, the motor is not moving according to the specified precision. To answer these problems, it is necessary to move the stepper motor with a clock signal that works in real time. The research method is done by designing and testing the stepper motor movement in full step and half step with the direction of Clock Wise (CW) and Counter Clock Wise (CCW) movement. These are simulated by using FPGA Isim and implementation using a stepper motor. The results of several experiments have been carried out the stepper motor movement degree according to the input value entered, responding timely movement, and the direction of movement stepper motor.
A tale of scale & speed: How the US Navy is enabling software delivery from l...sonjaschweigert1
Rapid and secure feature delivery is a goal across every application team and every branch of the DoD. The Navy’s DevSecOps platform, Party Barge, has achieved:
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GraphSummit Singapore | The Art of the Possible with Graph - Q2 2024Neo4j
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In the rapidly evolving landscape of technologies, XML continues to play a vital role in structuring, storing, and transporting data across diverse systems. The recent advancements in artificial intelligence (AI) present new methodologies for enhancing XML development workflows, introducing efficiency, automation, and intelligent capabilities. This presentation will outline the scope and perspective of utilizing AI in XML development. The potential benefits and the possible pitfalls will be highlighted, providing a balanced view of the subject.
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LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
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End to end testing is a critical piece to ensure quality and avoid regressions. In this session, we share our journey building an E2E testing pipeline for GridMate components (LWC and Aura) using Cypress, JSForce, FakerJS…
GridMate - End to end testing is a critical piece to ensure quality and avoid...
Q369699
1. G. Gopinath Reddy et al Int. Journal of Engineering Research and Application
ISSN : 2248-9622, Vol. 3, Issue 6, Nov-Dec 2013, pp.96-99
RESEARCH ARTICLE
www.ijera.com
OPEN ACCESS
High Speed Fault Injection Tool Implemented With Verilog HDL
on FPGA for Testing Fault Tolerance Designs
G. Gopinath Reddy*, A. Rajasekhar Yadav**, Y. Mahesh***
*(Department of ECE, CREC, Tirupati)
** (Department of ECE, CREC, Tirupati)
*** (Department of ECE, CREC, Tirupati)
ABSTRACT
This paper presents an FPGA-based fault injection tool, called FITO that supports several synthesizable fault
models for dependability analysis of digital systems modeled by Verilog HDL. Using the FITO, experiments
can be performed in real-time with good controllability and observability. As a case study, an Open RISC 1200
microprocessor was evaluated using an FPGA circuit. About 4000 permanent, transient, and SEUfaults were
injected into this microprocessor. The results show that the FITO tool is more than 79 times faster than a pure
simulation-based fault injection with only 2.5% FPGA area overhead.
KEY WORDS : Fault Tolerance Design , Gate level Fault Injection, Emulation Phase.
I.
INTRODUCTION
Fault injection is mainly used to evaluate
fault-tolerant mechanisms. In the last decade, fault
injection has become a popular technique for
experimentally determining dependability parameters of
a system, such as fault latency, fault propagation and
fault coverage [1]. Within the numerous fault injection
approaches that have been proposed, there are two
classifications for fault injection methods [2] hardwarebased fault injection [3], [4], and software-based fault
injection [5-11]. Software-based fault injection
methods are divided into software-implemented fault
injections (SWIFI) and simulation-based fault
injections. In the simulation-based fault injection, faults
are injected into the simulation model of the circuits
using VHDL [1], [7], [8], [9] or Verilog[10], [11]
languages. The main advantage of simulation-based
fault injection as compared with other fault injection
methods is the high observability and controllability
[10],[2]. However, simulation-based fault injection
methods are too time-consuming [2]. One way to
provide good controllability and observability as well
as high speed in the fault injection experiments is to use
FPGA-based fault injection. An effective FPGA-based
fault injection technique should support several
properties as below:
1. High controllability and observability,
2. High speed fault injection experiments with the
target system running at full speed,
3. Capability of injecting permanent and
transient faults,
All FPGA-based fault injection techniques
that mentioned above inject faults at synthesizable
VHDL models of the systems. Because of the use
of Verilog hardware description language in
implementation of many digital systems, the lack of
FPGA-based fault injection tool which supports this
www.ijera.com
hardware description language can be felt. This paper
describes the FPGA-based fault injection tool, called,
FITO which support all of the fourth properties as
mentioned above and is based on Verilog description of
the systems. FITO supports several fault models into
RTL and Gate-level abstraction levels of the target
system which has been described by the Verilog
HDL2. For supporting high speed fault injection
experiments, the fault injector part of FITO with low
area overhead is implemented with synthesized
microprocessor core inside the FPGA.
II.
FAULT MODELS
Digital circuits which are developed by
the hardware design languages have hierarchical
modeling and can be implemented by several abstract
levels. FITO performs fault injection experiments into
the gate level and RTL3 level of the circuits Verilog
models.The fault models which are introduced in gate
level are the permanent and transient faults. In addition,
bit-flip fault is proposed for the RTL level of the
digital circuits. Fault injection process can be done by
applying some extra gates and wires to the original
design description and modifying the target Verilog
model of the system. One of these extra wires is the
Fault Injection Signal (FIS) which playing the key role
in the fault injection experiments. If a FIS takes the
value 1, fault would be activated and if it takes the
value 0, the fault would become inactive. For each FIS
there would be a path through all levels of hierarchy to
its modified circuit. After the modification, the final
synthesizable Verilog description will be produced
which is suitable to use in emulators. In the rest of the
paper the synthesizable modification into the Verilog
model of the circuit for supporting each fault model has
been described.
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ISSN : 2248-9622, Vol. 3, Issue 6, Nov-Dec 2013, pp.96-99
II.1. Gate Level Fault Injection
FITO supports permanent and transient fault
models by generating the modified Verilog source
code of the target system for each fault model. The
modified Verilog description of the circuit is
synthesizable and can be used for FPGA-based
fault injection experiments. For supporting the
permanent faults in Verilog design, FITO nominates
wires for fault injection and apply the FIS signal
with one extra gate. So, by selecting the FIS signal
high at fault injection time, the permanent fault into the
specified wire will be injected.
Figure 1 shows the Verilog source
code modification for supporting stuck-at fault
models. FITO uses one timer for determining the fault
injection time. It also uses another timer for finishing
the fault injection experiment (workload execution).
After reaching the fault injection time, the FIS signal
will be high and another timer starts to count. As
shown in figure 1 wire TX is the additional wire which
is applied to the original design and the every wire
namely X will be replaced by TX.In addition, FITO
can generate synthesizable modified Verilog source
code of the target system for supporting transient
faults. The modified circuit that is suitable for
transient fault injection is shown in figure 2. After
reaching the fault injection time, the FIS signal will be
high and the timer which have been loaded with the
duration of the transient fault injection start to
count. Therefore, the FIS will be high (at logic 1) for
the specified duration of time. As similar to the
permanent fault, the additional wire (TX) will be used
and each wire, namely X will be replaced with TX.
Note, the fault injector part of FITO which is called
Fault Injection Manager.
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synthesizable code for supporting this fault model is
shown in figure 3. The inverted input will be goes to
the flip-flop for the next clock that FIS and Bit are
1. FIS indicates the target register and the Bit will be
high for the target register's bit. The fault injection
manger part of FITO is responsible for setting and
resetting the FIS and Bit signals.
III.
THE FITO ENVIRONMENT
FITO is made of three main parts that every
part is used in different fault injection phases. These
parts are:
1. Source Code Modifier & Fault List Generator
2. Fault Injection Manager
3. Result Analyzer
Source Code Modifier & Fault List Generator
and Result Analyzer are the software parts of the
FITO which are located on the host computer. On the
other hand, Fault Injection Manager is responsible
for performing the real-time fault injection. This
hardware part is implemented on the FPGA board.
The fault injection process with FITO has been
shown in Figure 4. As shown in this figure, each
FITO's part that were mentioned before are used in
different phases of the fault injection process. In the
rest of the paper, each fault injection phases and the
main work of each FITO's part in these phases will be
described in more details.
II.2. RTL Level Fault Injection
The fault model that is used by FITO at this
level is bit-flip (or Single Event Upset). SEUs are the
random events and may flip the content of the memory
element at unpredictable times. FITO generate
modified circuit for each memory element that is
specified for fault injection.The modified circuit for
supporting bit-flip fault model is shown in figure3.
Figure 2. Fault injection process with FITO
FIS[0]
Figure 1. Synthesizable bit-Flip fault model
For supporting the bit-flip fault model,
FITO produces the additional signals such as Bit
and FIS with one multiplexer. The Verilog
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III.1. The Setup Phase
The main objectives of this phase are
achieving modified Verilog source codes of the
original model that is synthesizable and generating
correspond fault list for each fault injection
experiments.
In setup phase the Verilog models have been given to
the FITO. First, by selecting all or some of the
considered fault models, the Source Code Modifier
processes the Verilog model of the system. After user
specifies the main module, a source navigator shows
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3. G. Gopinath Reddy et al Int. Journal of Engineering Research and Application
ISSN : 2248-9622, Vol. 3, Issue 6, Nov-Dec 2013, pp.96-99
the wires and registers to user. After selecting the fault
injection properties and the observation points,
FITO generates the corresponding fault list, time list
and the synthesizable modified source code. The
synthesizable modified source code has additional
flip-flops for each observation points.
Each time list indicates the time for triggering each
fault injection experiment and the fault list is used for
indicating the fault injection location. A typical fault
list is described in figure 5. As shown in figure 5, the
first bit of fault list is used for performing the fault
injection experiment. In addition, two bits and eight
bits are the inputs to decoder A and B. Outputs of
decoder A and B are Bit[3:0] , FIS[255:0] which
together indicate the bit position of the target register
for bit-flip fault injection. The FIS[255:0] without
Bit[3:0] are used for supporting permanent and
transient fault models.
Figure 3 . Fault list format
Modified source code contains fault
injection manager with modified circuit. So, the target
system is suitable for fault injection experiments.
Decoder A and B are the main parts of the fault
injection manager.
After this step, the modified source code must
synthesize with some synthesis tool and the gate level
source code which is suitable for programming the
FPGA will be produced. By using the gate level
source code the FPGA will be programmed.
III.2. The Emulation Phase
In the emulation phase, modified codes
created by the previous phase are emulated. After
emulating each experiment, the information of the
observation points will be sent through the serial
port. So, each experiment will have one trace file.
Each trace file is created with the observation data
points of each experiment. Results of this phase are
providing 1) one fault free trace file and 2) faulty
trace files which are generated by performing faulty
experiments. During this phase, the Result analyzer
part of FITO must be run from the user. This part sends
each fault list and time list of the fault injection
experiment to the fault injection manager. Then, the
fault injection manager sends the contents of the
observation points to the result analyzer. At the start
of the fault injection experiments, the fault injection
manager reset the first bit of fault list for creating the
golden trace file. Then, each fault list and time list is
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sent to the FPGA board. After the fault injection the
contents of the observation points are sent to the host
computer for analyzing the system behavior.
III.3. The Evaluation Phase
The main objective of this phase is the fault
tolerance parameter estimation. It is done by result
analyzer software part of FITO that is located on the
host computer. Result analyzer estimates the
dependability parameters by tracing differences
between golden run and faulty trace files. Some
facilities were developed for user interactions and for
required fault tolerant parameter determination.
IV.
EXPERIMENTAL RESULTS
We developed the fault injection using the
Altera DSP development board, equipped with Strati
EP1S25F780C FPGA. An OpenRISC 1200 has been
used as benchmark for FITO evaluation. The main
reason for using OpenRISC 1200 is that it has
synthesizable Verilog Description and intended for
embedded systems, automotive, portable computer
environments. In the experiments, two common
workload programs are considered [10]. The matrix
multiplication and the bubble sort. The workloads are
coded in C and are compiled with GNU gcc compiler.
So, after this step, the suitable code for the
OpenRISC 1200 microprocessor will be generated.
After this step we connected instruction and
data memory to the processor with the workload
which is loaded into the instruction memory.
.Table 1: Available and consumed FPGA resources
(EP1S25F780C5)
#
%
Total Available LEs in the FPGA
25660 100
LEs used by the OpenRISC 1200
4769
18.58
LEs used by the OpenRISC 1200 + FI 5401
21.04
The faults are injected in different parts of
the CPU modules of the OpenRISC 1200 core
consisting of control unit, the genPC unit, the
Instruction Fetch unit and the ALU unit. The total
runtime of the matrix multiplication and bubble sort
were 990 and 5890 clocks. In this experiment total
4000 permanent and transient faults injected at 100
random locations. For each location of the every
fault, experiments were carried out 20 times with
uniform distribution during the running of the each
workload. The fault duration for transient faults
were one clock period. The OpenRISC 1200
microprocessor emulated using 80 MHZ clock. The
observation points are the address bus, data bus and
the register file.
Table 2 shows the speed-ups. As shown in
table 2, the resulted speed-up is workload dependent.
This is because bubble sort workload generates
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4. G. Gopinath Reddy et al Int. Journal of Engineering Research and Application
ISSN : 2248-9622, Vol. 3, Issue 6, Nov-Dec 2013, pp.96-99
more signal event than matrix multiplication.
Table 2: The Resulted Speed-ups
Workload Simulation Emulation Speed-up
Time (sec) Time (sec)
Matrix
Multiplication
4605
51
13770
199
69
REFERENCES
[1]
90
Bubble Sort
The fault propagation results, fault models for
each module and the number of fault injection points
have been shown in table 2.
As shown in table 2, different fault models
are considered for each module of the Open RISC
1200 microprocessor. The Control Unit plays the key
role in controlling the pipeline registers of the
microprocessor. So, the transient fault model for the
internal wires of this module was considered. The pc
register which is the most important register of the
system for controlling the flow of the workload is
considered for bit-flip fault injection. So, the bit- flip
fault model was considered for the Genpc unit that
involves pc register.
[2]
[3]
[4]
[5]
V.
C0MPARISON WITH FPGA-BASED
FAULT INJECTION TOOLS
For estimating the main properties of FITO
that were mentioned in section 1, a comparison
between FITO and other fault injection tools is
needed. FITO provides controllability over 255 wires
and registers of the target microprocessor which is
sufficient for having the control over the important
wires and registers of the target microprocessor.
Because of using the combinational logics (two
decoders) and compacted fault and time lists the area
overhead of FITO is very lower than the FIDYCO
and FIFA and it uses one flip-flop for every fault
injection location. The minimum 22% area overhead
has been reported for FIFA tool.
VI.
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[6]
[7]
[8]
CONCLUSION
This paper described the FPGA-based
fault injection tool, called, FITO for evaluating the
digital systems modeled by Verilog HDL. Fault
injection with FITO is done by applying some extra
gates and wires to the original design description and
modifying the target Verilog model of the target
system. FITO support some properties such as high
speed, good controllability,
good observability
and low area overhead. As a case study, an
OpenRISC 1200 have been evaluated on the
EP1S25F780C FPGA and 4000 faults have been
injected into this microprocessor. The effects of
faults have been classified into control flow errors,
data errors and failures activated. Results show that
the FITO is more than 79 times faster than simulationbased fault injections with only 2.5% FPGA overhead.
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