International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Python programming concepts for the Internet of things applications development. This PPT contains details about classes, list , tuples, dictionaries, packages like HTTPLib,SMTPLib, etc
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Python programming concepts for the Internet of things applications development. This PPT contains details about classes, list , tuples, dictionaries, packages like HTTPLib,SMTPLib, etc
The main objective of this paper is to design and develop an automatic vehicle, fully controlled by a
computer system. The vehicle designed in the present work can move in a pre-determined path and work
automatically without the need of any human operator and it also controlled by human operator. Such a
vehicle is capable of performing wide variety of difficult tasks in space research, domestic, scientific and
industrial fields. For this purpose, an IBM compatible PC with Pentium microprocessor has been used
which performed the function of the system controller. Its parallel printer port has been used as data
communication port to interface the vehicle. A suitable software program has been developed for the
system controller to send commands to the vehicle.
Design, Analysis and Implementation of Modified Luby Transform CodeIOSR Journals
Abstract : Bit losses in erasure channels like computer networks are of great concern. The existing methods to combat bit losses are either inefficient or time consuming due to the retransmission protocols involved. Through this paper, we propose a Modified Luby Transform (MLT) coding scheme to efficiently transmit data over live computer networks. The MLT code can combat bit losses as well as eliminate the need for retransmission. The usability and reliability of the proposed MLT code is verified by testing it on a live computer network. Keywords : Erasure channel, Fountain Codes, Luby Transform Codes , Wired Networks, Wireless Networks
In this Office Security System project, image is captured by web camera, detected image is
compared with original data base for face recognition. If recognized image is known face then open the
door, otherwise sent the unknown image through LAN for displaying a new visitor, to all over the
network in various Departments. If the new visitor is to any one of the related person of staff member
then he will give the instruction to open door for the same visitor.
The Cortex M-3 system can measure all kind of electrical and thermal parameters RTD and so on. The
measured data can be displayed on the LCD/TFT of the system and at the same time can be transmitted
through RS – 485, or Ethernet N/W to remote DAS or DCS monitoring system by using mod bus / RTU
or mod bus / TCP control, The system has N/W with long distance communication function which can
ensure the disturbance rejection capabilities and reliability of the communication network. Hardware
platform use 32 bit embedded arm microprocessor and software platform use the microcontroller and
real time multitasking operating system which is open source. By using all these different port’s
functioning parameters of the Cortex M-3, Office Security System is developed
Combating Bit Losses in Computer Networks using Modified Luby Transform CodeIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
A 16-bit microprocessor I designed during my final semester (2005) of my Bachelor of Technology program. The microprocessor circuitry design was coded in VHDL and then configured in a Xilinx XC9572 PC84 CPLD kit. Most of the design, the architecture and the instruction set were taken from Computer System Architecture (3rd ed.) by M. Morris Mano. See https://github.com/susam/mano-cpu for VHDL source code and other related files.
Design and implementation of complex floating point processor using fpgaVLSICS Design
This paper presents complete processor hardware with three arithmetic units. The first arithmetic unit can
perform 32-bit integer arithmetic operations. The second unit can perform arithmetic operations such as
addition, subtraction, multiplication, division, and square root on 32-bit floating point numbers. The third
unit can perform arithmetic operations such as addition, subtraction, multiplication on complex numbers.
The specific advancement in this processor is the new architecture introduced for complex arithmetic unit.
In general complex floating point arithmetic hardware consists of floating to fixed and fixed to floating
conversions. But using such hardware will lead to compromise between accuracy and number of bits used
to represent the fixed point equivalent of floating point numbers. The proposed architecture avoids that
compromise and it is implemented with less number of look-up tables to save around 5500 logic gates. The
complex numbers are represented using a subset of IEEE754 standard floating point format, 16-bits for
real part and 16-bits for imaginary part. The floating point arithmetic unit works on 32-bit IEEE754 single
precision numbers. The instruction set is specially designed to support integer, floating point and complex
floating point arithmetic operations. The on-chip RAM is 8kBytes and is extendable up to 64kBytes. As the
processor is designed to implement on FPGA, the embedded block RAMs are utilized as RAM.
The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit
Data and instructions need to get into the system and results out
Input/output
Temporary storage of code and results is needed
Main memory
The main objective of this paper is to design and develop an automatic vehicle, fully controlled by a
computer system. The vehicle designed in the present work can move in a pre-determined path and work
automatically without the need of any human operator and it also controlled by human operator. Such a
vehicle is capable of performing wide variety of difficult tasks in space research, domestic, scientific and
industrial fields. For this purpose, an IBM compatible PC with Pentium microprocessor has been used
which performed the function of the system controller. Its parallel printer port has been used as data
communication port to interface the vehicle. A suitable software program has been developed for the
system controller to send commands to the vehicle.
Design, Analysis and Implementation of Modified Luby Transform CodeIOSR Journals
Abstract : Bit losses in erasure channels like computer networks are of great concern. The existing methods to combat bit losses are either inefficient or time consuming due to the retransmission protocols involved. Through this paper, we propose a Modified Luby Transform (MLT) coding scheme to efficiently transmit data over live computer networks. The MLT code can combat bit losses as well as eliminate the need for retransmission. The usability and reliability of the proposed MLT code is verified by testing it on a live computer network. Keywords : Erasure channel, Fountain Codes, Luby Transform Codes , Wired Networks, Wireless Networks
In this Office Security System project, image is captured by web camera, detected image is
compared with original data base for face recognition. If recognized image is known face then open the
door, otherwise sent the unknown image through LAN for displaying a new visitor, to all over the
network in various Departments. If the new visitor is to any one of the related person of staff member
then he will give the instruction to open door for the same visitor.
The Cortex M-3 system can measure all kind of electrical and thermal parameters RTD and so on. The
measured data can be displayed on the LCD/TFT of the system and at the same time can be transmitted
through RS – 485, or Ethernet N/W to remote DAS or DCS monitoring system by using mod bus / RTU
or mod bus / TCP control, The system has N/W with long distance communication function which can
ensure the disturbance rejection capabilities and reliability of the communication network. Hardware
platform use 32 bit embedded arm microprocessor and software platform use the microcontroller and
real time multitasking operating system which is open source. By using all these different port’s
functioning parameters of the Cortex M-3, Office Security System is developed
Combating Bit Losses in Computer Networks using Modified Luby Transform CodeIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
A 16-bit microprocessor I designed during my final semester (2005) of my Bachelor of Technology program. The microprocessor circuitry design was coded in VHDL and then configured in a Xilinx XC9572 PC84 CPLD kit. Most of the design, the architecture and the instruction set were taken from Computer System Architecture (3rd ed.) by M. Morris Mano. See https://github.com/susam/mano-cpu for VHDL source code and other related files.
Design and implementation of complex floating point processor using fpgaVLSICS Design
This paper presents complete processor hardware with three arithmetic units. The first arithmetic unit can
perform 32-bit integer arithmetic operations. The second unit can perform arithmetic operations such as
addition, subtraction, multiplication, division, and square root on 32-bit floating point numbers. The third
unit can perform arithmetic operations such as addition, subtraction, multiplication on complex numbers.
The specific advancement in this processor is the new architecture introduced for complex arithmetic unit.
In general complex floating point arithmetic hardware consists of floating to fixed and fixed to floating
conversions. But using such hardware will lead to compromise between accuracy and number of bits used
to represent the fixed point equivalent of floating point numbers. The proposed architecture avoids that
compromise and it is implemented with less number of look-up tables to save around 5500 logic gates. The
complex numbers are represented using a subset of IEEE754 standard floating point format, 16-bits for
real part and 16-bits for imaginary part. The floating point arithmetic unit works on 32-bit IEEE754 single
precision numbers. The instruction set is specially designed to support integer, floating point and complex
floating point arithmetic operations. The on-chip RAM is 8kBytes and is extendable up to 64kBytes. As the
processor is designed to implement on FPGA, the embedded block RAMs are utilized as RAM.
The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit
Data and instructions need to get into the system and results out
Input/output
Temporary storage of code and results is needed
Main memory
The focus of this Paper is the actual implementation of Network Router and verifies the functionality of the four port router for network on chip using the latest verification methodologies, Hardware Verification Languages and EDA tools and qualify the IP for Synthesis an implementation. This Router design contains three output ports and one input port, it is packet based Protocol. This Design consists Registers and FIFO. For larger networks, where a direct-mapped approach is not feasible due to FPGA resource limitations, a virtualized timemultiplexed approach was used. Compared to the provided software reference implementation, our direct-mapped approach achieves three orders of magnitude speedup, while our virtualized time multiplexed approach achieves one to two orders of magnitude speedup, depending on the network and router configuration.
An Implementation and Comparison of IO Expander on Zed Board and Spartan 3E f...IJEEE
A port expander is a computer hardware that allows more than one device to connect to a single port to a computer.A port expander can be any device to which one existing or onboard port will become two or more. It allows more devices of a particular port type to be utilized at the same time .The expander will connect to a single spot, but have multiple connections for devices.This paper includes the comparison between Xilinx design suit 12.4(on Spartan 3E) and vivado 2014.4( on zedboard).The comparison is shown with the help of an IO expander.The comparison is clear with the utilization of less number of LUTs and flip flops in vivado’s design summary.We can use C,C++ in vivado unlike Xilinx[1].The parameters like efficiency and speed are high in vivado and cost is low because of utilization of less number of LUTs.
Serial interface module for ethernet based applicationseSAT Journals
Abstract The introduction of Field Programmable Gate Arrays (FPGAs) which includes thousands of logic gates has made it feasible to prove specific software function on the particular hardware. This reduces the design time and the execution time and makes the embedded system to respond faster as a real time system. This paper serial interface module for Ethernet based Applications deals with the Study and the implementation of the Tri-mode Ethernet Media access control (TEMAC) which is present in the FPGA core. The Virtex-5 FPGA supports the 10Mbps, 100Mbps as well as 1000Mbps but in this paper contains the implementation of 1000Mbps (1Gigabit bits per second) data transfer rate. This project basically deals with communication established between the FPGA core and the PC. The IP core is interfaced with its transceiver module and communicated to the PC using Ethernet medium. The communication established is verified by interfacing the FIFO and the UART VHDL codes to the TEMAC IP core present on the Virtex-5 FPGA. The result at each module is verified on the Chipscope pro analyzer and the packet transmitted from FPGA to the PC is verified on the Wireshark software. Key Words: FPGA, Ethernet, TEMAC core , and Gigabit.
A NETWORK-BASED DAC OPTIMIZATION PROTOTYPE SOFTWARE 2 (1).pdfSaiReddy794166
The International Journal of Engineering and Science and Research is online journal in English published. The aim is to publish peer review and research articles without delay in the developing in engineering and science Research.The International Journal of Engineering and Science and Research is online journal in English published. The aim is to publish peer review and research articles without delay in the developing in engineering and science Research.
IoT ( M2M) - Big Data - Analytics: Emulation and DemonstrationCHAKER ALLAOUI
Study and simulation of the systems modern IoT with examples of connected objects such as: GPS(GLOBAL POSITIONING SYSTEM), Philips Hue, Thermometer, and connected cars implemented with the technology nodeJS and Node-Red with the communication protocol of M2M ( MQTT).
As well as an analytical study based on Elasticsearch, MongoDB, Apache Hadoop, Apache Hive and Jaspersoft.
Interface method and system for accessing inner layers of a network protocolTal Lavian Ph.D.
A method of performing network communications includes receiving a datagram for transmitting information over a network, selecting a layer in a network protocol stack to establish communication over the network using an inner layer application programming interface (IL API), establishing an inner layer socket at the selected network layer using the IL API without accessing other layers in the layered network protocol stack, and transmitting the datagram packet over the selected layer using the inner layer socket.
https://www.google.com/patents/US6845397?dq=US+6845397&hl=en&sa=X&ei=zrxTVJv8C-GsmAXaoYLwCQ&ved=0CB0Q6AEwAA
A major problem in day to day life is parking of vehicles especially the car parking at an appropriate place. And this issue indirectly leads to traffic congestion. This paper presents the basic concept of using server or cloud based smart parking services in smart cities as an important application of the Internet of Things (IoT) paradigm. This system will be accessible through a mobile app or through the webpage provided and can be used to monitor or find the empty slots in that area.
We have compiled the most important slides from each speaker's presentation. This year’s compilation, available for free, captures the key insights and contributions shared during the DfMAy 2024 conference.
ACEP Magazine edition 4th launched on 05.06.2024Rahul
This document provides information about the third edition of the magazine "Sthapatya" published by the Association of Civil Engineers (Practicing) Aurangabad. It includes messages from current and past presidents of ACEP, memories and photos from past ACEP events, information on life time achievement awards given by ACEP, and a technical article on concrete maintenance, repairs and strengthening. The document highlights activities of ACEP and provides a technical educational article for members.
NUMERICAL SIMULATIONS OF HEAT AND MASS TRANSFER IN CONDENSING HEAT EXCHANGERS...ssuser7dcef0
Power plants release a large amount of water vapor into the
atmosphere through the stack. The flue gas can be a potential
source for obtaining much needed cooling water for a power
plant. If a power plant could recover and reuse a portion of this
moisture, it could reduce its total cooling water intake
requirement. One of the most practical way to recover water
from flue gas is to use a condensing heat exchanger. The power
plant could also recover latent heat due to condensation as well
as sensible heat due to lowering the flue gas exit temperature.
Additionally, harmful acids released from the stack can be
reduced in a condensing heat exchanger by acid condensation. reduced in a condensing heat exchanger by acid condensation.
Condensation of vapors in flue gas is a complicated
phenomenon since heat and mass transfer of water vapor and
various acids simultaneously occur in the presence of noncondensable
gases such as nitrogen and oxygen. Design of a
condenser depends on the knowledge and understanding of the
heat and mass transfer processes. A computer program for
numerical simulations of water (H2O) and sulfuric acid (H2SO4)
condensation in a flue gas condensing heat exchanger was
developed using MATLAB. Governing equations based on
mass and energy balances for the system were derived to
predict variables such as flue gas exit temperature, cooling
water outlet temperature, mole fraction and condensation rates
of water and sulfuric acid vapors. The equations were solved
using an iterative solution technique with calculations of heat
and mass transfer coefficients and physical properties.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsVictor Morales
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
Literature Review Basics and Understanding Reference Management.pptxDr Ramhari Poudyal
Three-day training on academic research focuses on analytical tools at United Technical College, supported by the University Grant Commission, Nepal. 24-26 May 2024
A review on techniques and modelling methodologies used for checking electrom...nooriasukmaningtyas
The proper function of the integrated circuit (IC) in an inhibiting electromagnetic environment has always been a serious concern throughout the decades of revolution in the world of electronics, from disjunct devices to today’s integrated circuit technology, where billions of transistors are combined on a single chip. The automotive industry and smart vehicles in particular, are confronting design issues such as being prone to electromagnetic interference (EMI). Electronic control devices calculate incorrect outputs because of EMI and sensors give misleading values which can prove fatal in case of automotives. In this paper, the authors have non exhaustively tried to review research work concerned with the investigation of EMI in ICs and prediction of this EMI using various modelling methodologies and measurement setups.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
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1. International Journal of Research in Advent Technology, Vol.2, No.7, July 2014
E-ISSN: 2321-9637
36
Synthesizing a Requester Device Using VHDL:
A Basic Review supporting Ethernet communication platform
Rinju Mariam Rolly1, Teena Rajan2,
Deartment of Electronics & Communication Engineering1, 2,
P G Scholar, Mar Baselios College of Engineering & Technology1,
Assistant Professor, Mar Baselios College of Engineering & Technology2
Email: rinju_mariam@yahoo.com1 ,
Abstract- A web-based user client can serve as an interface to control the applications executing on a platform,
but this would require a web interface on the multiprocessor platform under investigation. The main objective of
this project is to provide network connectivity to the electronic devices. By doing so, automatic updating can be
achieved. This helps to keep control of the performance of device. A requester device is simulated using VHDL.
Index Terms- Ethernet; FIFO; GPIO ports; Requester device
1. INTRODUCTION
As technology is varying or updating day by
day, in this modern internet world, we are interested
in real-time performance evaluation of multiple
applications executing concurrently on a
multiprocessor platform. Ethernet communication
platform [1-2] provides a way to control
programmable logic devices, as well as data
communication using a standard network. The
implementation of the communication platform
depends on the requester device, because the GPIO
ports must be configured to allow the connection of
diverse such devices (and architectures). The research
work in [1] deals with a communication platform
which helps in automation of the electronic devices.
Here, the work is about the implementation of
requester device that is a part of above specified
communication platform. For the complete operation
as a communication platform, the network layers
should be defined. Reference [3] describes about the
communication protocols for a bidirectional data
transmission. The requester device simulated is done
by VHDL programming [4]. [5-6] explains about
multi tasking platforms operating on multi-processor
systems.
2. SYSTEM DESIGN
The device that is synthesized in the FPGA is
called requester device. The requester device is
represented as a forwarder device. The device should
transmit data to far away centre, where the received
data from the device is analyzed and processed for
further applications and system development. The
device should not only transmit, but also it should
receive signals or commands or data from an external
transmission centre. Any device that takes part in
communication needs to be a bi-directional in nature.
A communication is success only if it conveys its
message error free and they both (sender and receiver)
exchanged their information and communicated each
other.
As shown in figure 1, the requester device
consists of three parts: GPIO to FIFO block, the
forwarder device and FIFO to GPIO section. GPIO to
FIFO is used to receive data transmitted by a remote
computer or by any other transmitter. The data is
received through the Ethernet physical layer and for
perfect transaction that received data block should be
read from the GPIO pins to the Data_In of requester
device.
Figure 1: Embedded system with requester device [1]
2. International Journal of Research in Advent Technology, Vol.2, No.7, July 2014
E-ISSN: 2321-9637
37
WE: Write Enable
RE: Read Enable
Clk
DataIn FullFIFO
WE_GtoF
REQUESTER DEVICE
RE_FtoG DataOut
Slide_switch_loop
Reset
Figure 2: Requester device
Din Full
RE Empty
WE Dout
nreset clk
Figure 3: Fifo1 Port Diagram
Figure 3 shows the pin diagram for fifo1, i.e.,
GPIO_to_FIFO data transfer block. The data out from
GPIO pins is read and writes to Din.
Din
F Full
RE
Empty
WE
Nreset
Dout
clk
Figure 4: fifo2 Port Diagram
Din: 8-bit Data Input
Dout: 8-bit data output
nreset: reset signal
Full: Shows ‘1’, when the FIFO is full
Empty: Shows ‘1’, when the FIFO is empty
Figure 4 shows the reverse action for figure3.
It shows the data from FIFO is given to the
GPIO(General Purpose Input Output) pins. Dout, Full
and Empty are output signals, whereas the other five
signals shown in figure 3 are inputs to the Requester
FIFO IN. It describes the port diagram of
FIFO_to_GPIO block. Here, the data is given back to
the GPIO IN pin from the FIFO OUT. The signals
have the same operational nature as for the signals in
figure 3. The FIFO’s are enabled by the clocking
pulse, which is of picoseconds range. The FPGA has a
50 MHz clock oscillator in built in it.
3. RESULT & DISCUSSIONS
The proposed device is simulated with the
help of ModelSim software. The chapter describes the
simulation in modelsim simulation and debugging
software.
Select New Project Define the
project name(rin) Add new file
Add files to existing project Save the
files with .vhd extension.
All the files saved will get attach to the
project. The files are named GPIOtoFIFO,
FIFOtoGPIO and Requester_1.The first step for the
simulation is:
· Select the VHDL files and compile
Select compile selected from the compile option.
This will cause the compilation of the selected files
from the project created. If the files are correct (error
free), then the compilation will comes out
successfully. The files GPIOtoFIFO and FIFOtoGPIO
are defined inside the file Requester_1. Hence the
Requester_1 file will compile first, during its
compilation, the other two files are called within it.
This completes the compilation of the project. Next,
we should go for simulation. Compilation is always
followed by simulation.
· Simulation
Click on start simulation. A new pop-up window
opens as shown in below. From design option, select
work library. Click on (+) sign. Fifo1, fifo2 and
requester are entities used. Entities are saved in the
work directory. Only the requester entity is selected
and simulated. Since the other two defined entities are
a part of this aforementioned entity, the fifo1 and
fifo2 will be called inside the requester and simulates
them. So for that, click on requester and select OK.
This operation completes the simulation step of
project. All the aforementioned steps are done to
configure the GPIO pins or otherwise, it is to define
the requester device.
FIFO to GPIO
(fifo2)
3. International Journal of Research in Advent Technology, Vol.2, No.7, July 2014
E-ISSN: 2321-9637
38
· Output
The values are given to the signals manually
in ModelSim simulation software, whereas in ISE
(Integrated simulation environment) the signals are
called automatically. So for that, the values each
variable should posses are programmed in ISE bench.
.
4. CONCLUSION
Figure 5: Simulation result
A simple requester device is simulated with the
help of ModelSim simulation and debugging
software. The result shows the data given to the GPIO
pin is read by FIFO and it is written back to GPIO out
pin. The simulation illustrates a forwarding device
and it finds application as a mediator between two
devices for data transfer and is base for Ethernet
communication platform.
Acknowlegements
I thank my Lord almighty for the strength he
blessed me with. I would like to extend my gratitude
to my guide, faculties, friends, to my family and to all
who supported me in this work.
4. International Journal of Research in Advent Technology, Vol.2, No.7, July 2014
E-ISSN: 2321-9637
39
REFERENCES
[1] Rodrigo Neri de Souza, Andr´e Vaz da Silva
Fidalgo, Daiana Nascimento Muniz, “Ethernet
Communication Platform for synthesized devices
in Xilinx FPGA”, IEEE Conference, September
2011
[2] Rodrigo Neri de Souza, Plataforma de
Comunicac¸ ˜ao Ethernet para dispositivos
embarcados em FPGAs da Xilinx, Undergraduate
thesis, IFSC, Brazil, 2010.
[3] Douglas L. Perry, VHDL programming by
example, 4ed. Tata McGraw Hill 2002
[4] Tanenbaum, A.S., Computer Networks, 4 ed.,
[5] M.J. Rooijakkers, “Web server controlled multi-tasking
on a FPGA based multiprocessor
platform”,
[6] Akash Kumar, Shakith Fernando, Yajun Ha, Bart
Mesman, and Henk Corporaal, "Multi-Processor
System-Level Synthesis for Multiple
Applications on Platform FPGA”, IEEE
Conference Publications, August 2007