This document discusses hardware Trojan threats in FPGAs. It proposes a novel metric called the Hardware Trojan Threat Detectability Metric (HDM) that uses weighted physical parameters to detect Trojans. Several Trojans were designed and implemented in an FPGA testbed to compromise systems. HDM increased detection rates to 86% compared to 57% using single parameters. The document analyzes potential attack surfaces in FPGAs and discusses optimization of Trojans to avoid detection.