IEEE P1581 provides a standard method for testing interconnects of complex memory ICs without requiring additional test pins. It specifies implementation rules for simple test logic and transparent test mode entry/exit methods. Key features include fast testing with small test vectors without needing complex memory access or additional pins. Test mode is entered via a dedicated test pin, one of seven transparent test mode control methods, or optional test functions. The standard aims to improve testing of memory devices on printed circuit boards.

1. IEEE P1581
Simplifying Connectivity Tests for Complex Memories
and other Non-Boundary Scan Devices
Heiko Ehrenberg, GOEPEL Electronics
Chair of IEEE P1581 working group
h.ehrenberg@ieee.org

2. IEEE P1581 - Introduction
• Scope: method for testing the interconnection of discrete,
Low-cost
complex memory integrated circuits (ICs) where additional
pins for testing are not available and implementing boundary
scan (IEEE Std 1149.1) is not feasible;
• Purpose:
Improve interconnect test for discrete memory devices by
specifying implementation
rules for test logic and test mode
entry/exit methods included in memory ICs;
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3. Basic concept
PCB
IEEE 1581 device
Optional Test Pin
Memory Test
(if no TTM)
Controller Control
TTM
(optional)
Input Memory Cells
Bus x
IEEE
1149.1
Combinational
device(s) y
Test Logic
Output Bus
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4. Key features
• Simple test logic implementation for memory
devices (and possibly other complex, slave-type components)
• No extra pins required
• Not relying on complex memory access cycles
• Fast test execution, small test vector set
• Usable with any access methodology
(Boundary scan, functional, ICT)
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5. Test mode control
• Dedicated test pin (TPN), or
• One of seven transparent test mode (TTM)
control methods:
• Non-functional stimulus (NFS) Test entry or exit is triggered
by a condition on the pins
• Designated command codes (DCC) that would otherwise never
exist under normal
• Simultaneous input/output (SIO) functional conditions
• Clock frequency (CKF)
These methods require
• Analog level (ANL) additional board-level
• Conditional power-up initiation (CPI) and/or controlling device
DFT to be implemented
• Default power-up initiation (DPI)
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6. Test mode control - NFS
To
TDO
WE WE
CS CS
From
TDI
Control IEEE 1581
Device Device
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7. Test mode control - DCC
To
TDO
CD2 CD2
CD1 CD1
STB STB
From
TDI
Control IEEE 1581
Device Device
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8. Test mode control - CPI
To
TDO
OR
WE WE
CS CS
OR
From
TDI
PCB DFT Non-Volatile
Control Control IEEE 1581
Device Device
Test mode is entered if a predetermined set of logical input states exist at a predetermined period
after device power-up.
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9. Test logic
• One of three defined test logic architectures:
• XOR (3-input XOR or XNOR gates)
• IAX (XOR, Inverters, and AND gates)
• XOR-2 (2-input XOR or XNOR gates)
• Or a custom test logic that satisfies rules in IEEE
P1581
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10. Test logic example - XOR
IEEE 1581 Memory Device
XOR O1
Inputs 1-6
XOR O2
XOR O3
XOR O4
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11. Optional test functions
• Optional test functions accessible via test
pattern partitioning
• Examples include:
• Reading a device identification (ID)
• Control line continuity test
• Built-in self test (BIST) access
• Other public or private commands
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12. Status of IEEE P1581
• Balloting completed
• Ballot group voted to accept IEEE P1581
• IEEE needs to review and finalize
acceptance
• Official adoption as IEEE Std 1581 expected
for mid 2010
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