The document presents a new method for eliminating dead time in two-level voltage source inverters, which is crucial to prevent short circuits and output distortion. By employing a novel approach that minimizes low-frequency distortion, the method has shown improved performance in both PSPICE simulations and prototype experiments. Additionally, this method offers simpler control logic and can be implemented cost-effectively compared to conventional methods.

1. International Journal of Engineering Research and Development
e-ISSN: 2278-067X, p-ISSN: 2278-800X, www.ijerd.com
Volume 6, Issue 10 (April 2013), PP. 101-106
101
A Novel Method for the Elimination of Dead Time in Two
Level Voltage Source Inverter
M.S.Sivagamasundari1
, Dr.P.Melba Mary2
1
(Assistant Professor , Department of EEE,V V College of Engineering,Tisaiyanvilai
2
(Principal , Department of EEE,V V College of Engineering,Tisaiyanvilai)
Abstract: - Dead time is a short delay introduced between the gating signals of the upper and lower
switches in an inverter leg to prevent the short circuit of dc link. Such dead time results in a change in f
undamental voltage and also causes low frequency distortion. In this paper , a novel method for the
elimination of dead time in two level voltage source inverter is proposed and implemented. This
method reduces the low frequency distortion and results in a steady fundamental voltage. The validity
of this method has been studied by the PSPICE Simulation and prototype experiment.
Keywords: - Dead-time, harmonic, phase-leg, gate drive, voltage source inverter (VSI)
I. INTRODUCTION
To avoid shoot-though in PWM controlled voltage source inverters (VSI), dead-time, a small interval
during which both the upper and lower switches in a phase leg are off, is introduced into the control of the
standard VSI phase leg. However, such a blanking time can cause problems such as output waveform distortion
and fundamental voltage loss inVSIs.[1-4].Fig. 1(a) shows the dead-time effect in a voltage source inverter.
(a) (b)
Fig.1.Effect of dead time
Fig 1 (b) shows the output voltage waveform distortion caused by dead-time effect. To overcome dead-
time effects, most solutions focus on dead-time compensation [1-4] by introducing complicated PWM controller
and expensive current detection hardware. In practice, the dead-time varies with the devices and output current,
as well as temperature, which makes the compensation less effective, especially at low output current, low
frequency, and zero current crossing. [5] proposed a new switching strategy for PWM power converters. [6]
presented an IGBT gate driver circuit to eliminate the dead-time effect. [7] proposed a phase leg configuration
topology which prevented shoot through. However, an additional diode in series in the phase leg increases
complexity and causes more loss in the inverter. Also, this phase leg configuration is not suitable for high power
inverters because the upper device gate turn off voltage is reversely clamped by a diode turn on voltage. Such a
low voltage, usually less than 2 V, is not enough to ensure that a device is in off state during the activation of its
complement device.[7]

2. A Novel Method for the Elimination of Dead Time in Two Level Voltage…
102
II. PRINCIPLE OF DEAD TIME ELIMINATION
Fig. 2. A generic phase leg of VSIs.
To explain the principle of the proposed dead-time elimination method, we refer to a generic phase leg
of VSIs, as shown in figure 2. Assuming the output current flows out of the phase leg, in each switching cycle,
the current comes out from the upper device when Kp is on and freewheels through diode Dn when Kp is off.
Here this current direction is defined as positive. Under this condition, the generic phase leg can be equivalently
expressed as a P type switching cell. Similarly when load current flows into the phase leg, defined as negative,
the current goes into the lower device when Kn is on and freewheels through diode Dp when Kn is off. Under
this condition, the generic phase leg can be equivalently expressed as a N type switching cell . Actually a
generic phase leg is a combination of one P switch cell and one N switch cell. There is no question that dead-
time is not required for either a P switch cell or a N switch cell because both cells are configured with a
controllable switch in series with a uncontrollable diode.[8].
III. TWO LEVEL VOLTAGE SOURCE INVERTER
Fig.3.Full-bridge inverter feeding an RL load
The full-bridge circuit feeding an inductive (RL) load is shown in fig.3. A simple scheme of
controlling the gating of the four switches is also shown. Although each switch is gated to be on for one-half the
time period, each switch may not conduct for one-half the time period due to the constraints imposed by the
load. The arrow-head shows the direction in which the current can flow through each switch. When a switch is
gated on but the current is in the opposite direction, the freewheeling diode placed in anti parallel with the
switch will provide the path for the current. Note that there are two intervals during which the output voltage is
zero. During the time interval between a and b, the current i(t) circulates in the top-half of the circuit through S1
and D3 and the voltage across the load is zero assuming the diode and the switch are ideal. Likewise, the current
completes it path through S4 and D2 in the bottom half of the circuit during the time interval from c to d and the
voltage across the load is zero.
Fig. 4. Waveform for the gating scheme of the 4 switches

3. A Novel Method for the Elimination of Dead Time in Two Level Voltage…
103
IV. SIMULATION RESULTS
In this paper, the simulation model is developed with PSPICE tool which contains a dc source, four
MOSFETs , inductor, capacitor and a resistive load. The MOSFET is driven by the gate signal of frequency of
50KHZ. The circuit is designed for an output of 40V with an input of 48V. The simulation circuit of the
proposed method and the output voltage waveform is shown in fig.5. and fig.6.
M6
M2N6757
TD = 10ms
TF = 1ns
PW = 10ms
PER = 20ms
V1 = 0
TR = 1ns
V2 = 5
V1
TD = 0
TF = 1ns
PW = 10ms
PER = 20ms
V1 = 0
TR = 1ns
V2 = 5
V4TD = 0
TF = 1ns
PW = 10m
PER = 20ms
V1 = 0
TR = 1ns
V2 = 5
V+
V-
C3
100u
M1
M2N6757
M2
M2N6757
D6
MUR150
V+
D5
MUR150
L1
100mH
1 2
R5
1k
V-
D4
MUR150
V7
48V
0
DEAD TIME
ELIMINATION 2
D1
MUR150
V2
TD = 10ms
TF = 1ns
PW = 10m
PER = 20ms
V1 = 0
TR = 1ns
V2 = 5
M3
M2N6757
Fig.5.Simulation circuit of the proposed method
Time
0s 10ms 20ms 30ms 40ms 50ms 60ms 70ms 80ms 90ms 100ms
V(M2:d,V2:-)
-60V
-40V
-20V
-0V
20V
40V
60V
Fig.6. Output Voltage Waveform

4. A Novel Method for the Elimination of Dead Time in Two Level Voltage…
104
In this proposed method, the dead time effect has been dramatically minimized and the output distortion
also reduces.
V. HARDWARE IMPLEMENTATION
TX2
TN33_20_11_2P90
1 2
M6
IRF840
12
12
C3
47U
R4
10K
220 TO 1K
C3
47U
U2
74HC244
10
20
1
2
4
6
8
18
16
14
12
GND
VCC
1G
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
M4
IRF840
16
220 TO 1K
33P
1 2
22
12
1000U-35V
7805
13
2
VINVOUT
GND
12
M1
IRF840
M5
IRF840
10U
10U
17
12
L1
10uH
230-15V
TX1
TN33_20_11_2P90
12
7805
13
2
VINVOUT
GND
M2
IRF840
10U
1k
7805
1 3
2
VIN VOUT
GND
U4
AT89C2051/SO
1
10
20
5
4
12
13
14
15
RST/VPP
GND
VCC
XTAL1
XTAL2
P1.0/AIN0
P1.1/AIN1
P1.2
P1.3
1000U-35V
12
22
10K
IR2110
1
710
12
13
2
6
3
9
5
LO
HOHIN
LIN
VSS
COM
VB
VCC
VDD
VS
C9
10U
M3
IRF840
1N4500
12
1000U-35V
230-15V
7805
1 3
2
VIN VOUT
GND
U8
MCT2E
C12
333P
12
10U
U7
MCT2E
22
IR2110
1
710
12
13
2
6
3
9
5
LO
HOHIN
LIN
VSS
COM
VB
VCC
VDD
VS
22
2200U-63
10U
47U
12
D7
LED
V1
30
22
D7
LED
C8
33P
47U
230-15V
X1
12.00
TX3
TN33_20_11_2P90
10K
D7
LED
220 TO 1K
12
U5
0
12
1N4500
12
Fig.7.Hardware circuit diagram
The hardware circuit for the proposed method is shown in fig.7. The hardware circuit consists of the
following major parts such as power supply unit, microcontroller circuit, buffer circuit and isolation circuit.
Fig.8. shows the power and control circuit.
Fig.8.Power and control circuit

5. A Novel Method for the Elimination of Dead Time in Two Level Voltage…
105
Fig.9.Experimental waveform of the proposed method
Fig.10.Hardware Setup
The proposed dead elimination circuit is incorporated into a single phase H-Bridge inveter as shown
in fig.10. The MOSFET’S used are IRF840.The inverter is loaded with a R-L load resistances of 1KΩ and
100mH. The dc bus voltage is 48V and the frequency of modulation is 50HZ. In addition, the proposed dead-
time elimination control scheme can be implemented, contained in the at AT89C2051microcontroller software
to reduce hardware cost.
VI. CONCLUSION
In the present work, a novel method for the elimination of dead time in two level voltage source
inverter is proposed and implemented. This method reduces the low frequency distortion and results in a steady
fundamental voltage. The validity of this method has been studied by the PSPICE Simulation and prototype
experiment. Compared to the conventional method , this method has simple control logic, low cost and flexible
implementation.
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