This document provides an introduction to MOSFET transistors. It describes the basic structure of an enhancement-type n-channel MOSFET, which consists of a lightly doped n-type substrate with two highly doped p+ regions for the source and drain separated by a channel. A thin silicon dioxide layer is grown over the structure with holes for contacts to the source and drain. A metal gate overlay covers the entire channel. Applying a negative voltage to the gate induces a conducting channel between the source and drain by creating a layer of positive charges in the semiconductor beneath the oxide. The threshold voltage is the minimum gate voltage needed to induce this conducting channel.

1. Introduction to MOSFET
Dr. Varun Kumar
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2. Outlines
1 Introduction to MOSFET
2 Enhancement type MOSFET
3 Threshold voltage
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3. Introduction to MOSFET
⇒ MSFET→ Metal-oxide-semiconductor-field-effect-transistor.
⇒ It is more commercially viable than the JFET.
⇒ Enhancement-type n-channel MOSFET.
⇒ On a lightly doped n-type substrate, two highly doped p+ regions are
diffused.
⇒ These two p+ sections are called as source and drain. Both terminals
are separated by a distance 5 − 10µm
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4. Continued–
⇒ A thin 0.1µm − 0.2µm layer of insulating silicon dioxide (SiO2) is
grown over the surface of the structure.
⇒ Holes are cut into the oxide layer, allowing contact with source and
drain.
⇒ Gate-metal area is overlaid on the oxide, covering the entire channel.
⇒ Contact metal over channel is called as gate-terminal.
⇒ Chip area is only about 5% of that required by BJT.
⇒ Metal area of the gate, in conjunction with insulating di-electric oxide
layer and semi-conductor channel form a parallel-plate capacitor.
⇒ SiO2 layer results in an extremely high input resistance (1010 − 1015Ω)
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5. Enhancement MOSFET
⇒ Ground the substrate and apply the negative voltage at the gate
terminal.
⇒ Electric field will be directed ⊥ through the oxide.
⇒ The field will end on “induces” positive charges on the semiconductor
site.
⇒ +Ve charges forms an inversion layer.
⇒ When negative gate voltage increases, the induced +Ve charge in the
semiconductor also increases.
⇒ Region beneath the oxide now has p-type carriers, the conductivity
increases, and the current flows from source to drain through the
induced channel.
⇒ Here the drain current is “enhanced” by -Ve gate voltage. Hence, this
device is called an enhancement type MOS.
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6. Continued–
(a) Drain characteristics
(b) Transfer curve (for VDS = 10 V )
Threshold Voltage
⇒ The current IDSS ∼ nA at VGS ≥ 0
⇒ VGS is made negative, the current |ID| increases slowly.
⇒
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7. Low VT
It allow
1 The use of a small power supply voltage
2 Compatible operation with bipolar device.
3 Smaller switching time due to smaller voltage swing during switching.
4 Higher packing densities.
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8. Methods for reducing the VT
1 High threshold MOSFET uses a silicon crystal with < 111 >
orientation. If orientation is < 100 > direction, it is found half that of
the < 111 > orientation.
2 Silicon nitride approach makes use of a layer of Si3N4 and SiO2.
3 Polycrystalline silicon doped with Boron is used as the gate electrode
instead of aluminum.
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