Electrostatic discharge (ESD) immunity test is one of the important electromagnetic compatibility (EMC) tests. The IEC standard IECdlOOO-4-2 is the widely used standard to test the ESD immunity for electronic equipment. Many amendments such as amendment 1 (1998), amendment 2 (2000) have been published since 1995, but there is still problems with the ESD immunity test even with the 200x version. More than six ESD generators of different bands are tested for different equipment. The results show that the failure voltages of different ESD generators are vary much from different bands for the same test equipment. This may lead to the results incomparable when test the ESD immunity test in the EMC. Further studies show that there is a good correlation between the failure voltage and the induced voltage.
ESDEMC_PB2014.08 An Ethernet Cable Discharge Event (CDE) Test and Measurement...ESDEMC Technology LLC
Abstract — A Cable Discharge Event (CDE) is an electrostatic discharge between a cable and a connector. CDEs occur on unshielded Ethernet based communication interfaces and inject currents into the pins directly [1-3]. The charging processes are in general understood; however, the discharge processes are complicated due to the number of pins involved and their connections to a system. Based on an understanding of the factors which determine the severity of a CDE, this article describes how to setup a variety of repeatable CDE tests and how to analyze the measurement results.
Keywords — Cable Discharge Event (CDE) Test; Cable ESD;
ESDEMC_PB2009.08 A Measurement Technique for ESD Current Spreading on A PCB u...ESDEMC Technology LLC
Abstract—Electrostatic discharge (ESD) can cause interference or damage in circuits in many ways e.g., by E- or Hfield coupling or via conduction paths. Although we can roughly estimate the voltage and current at the injection point during an ESD event, the real offending parameter is mostly the ESD current spreading throughout the system. Those currents can be simulated if great simplifications of the system are accepted.
However, even in moderately complex systems the ability to simulate is limited by lack of models and computational resources. Independent of the complexity, but obviously not free of its own limitations is a measurement technique that captures the current as a function of time and location through the system.
This article describes the proof on concept of ESD such a measurement technique that allows reconstructing the spreading current as a movie from magnetic field measurements. It details the technique, question of probe selection and how to process the data to present the current spread as a movie.
TN013 ESD Failure Analysis of PV Module Diodes and TLP Test MethodWei Huang
Bypass diodes inserted across the strings of the solar panel arrays are essential to ensure the efficiency of the solar power system. However, those diodes are found to be susceptible to potential Electrostatic Discharge (ESD) events in the process of solar Photovoltaic (PV) panel manufacture, transportation and on-site installation. Please refer [1], where an International PV Module Quality Assurance Forum has been setup to investigate PV Module reliability, and Task Force 4 has been setting guidelines for testing the ESD robustness of diodes used to enhance PV panel performance. This document explains the theory behind the ESD damage and the proper test and analysis methods for ESD failure of diodes. To demonstrate the proposed testing methodology that follows, we will be evaluating six different types of diode models as supplied by our customer, who manufactures solar panel arrays.
TN006 frequency compensation method for vf-tlp measurementsWei Huang
The objective of this article is to demonstrate a frequency compensation technique for measuring the current and voltage of a device under test in a Very Fast Transmission Line Pulser (VF-TLP) test environment. The current measurement utilizes Non-Overlapping Time Domain Reflectometry, which is useful for On-Wafer testing because the measurement can be made with low profile small pitch probes, such as the Picoprobe Model 10. Further, to increase the bandwidth of the current measurement over common techniques, such as current transformers with 1GHz bandwidth, the method utilizes a resistive Pick-Off. The Pick-Off can be finely tuned to have as little insertion loss as possible, thereby enhancing the bandwidth. Although this method can also yield a DUT voltage measurement, the result suffers from numerical errors for low ohmic devices. A separate, direct measurement is presented that will demonstrate an extremely accurate voltage measurement that also utilizes frequency compensation.
ESDEMC_PB2014.08 An Ethernet Cable Discharge Event (CDE) Test and Measurement...ESDEMC Technology LLC
Abstract — A Cable Discharge Event (CDE) is an electrostatic discharge between a cable and a connector. CDEs occur on unshielded Ethernet based communication interfaces and inject currents into the pins directly [1-3]. The charging processes are in general understood; however, the discharge processes are complicated due to the number of pins involved and their connections to a system. Based on an understanding of the factors which determine the severity of a CDE, this article describes how to setup a variety of repeatable CDE tests and how to analyze the measurement results.
Keywords — Cable Discharge Event (CDE) Test; Cable ESD;
ESDEMC_PB2009.08 A Measurement Technique for ESD Current Spreading on A PCB u...ESDEMC Technology LLC
Abstract—Electrostatic discharge (ESD) can cause interference or damage in circuits in many ways e.g., by E- or Hfield coupling or via conduction paths. Although we can roughly estimate the voltage and current at the injection point during an ESD event, the real offending parameter is mostly the ESD current spreading throughout the system. Those currents can be simulated if great simplifications of the system are accepted.
However, even in moderately complex systems the ability to simulate is limited by lack of models and computational resources. Independent of the complexity, but obviously not free of its own limitations is a measurement technique that captures the current as a function of time and location through the system.
This article describes the proof on concept of ESD such a measurement technique that allows reconstructing the spreading current as a movie from magnetic field measurements. It details the technique, question of probe selection and how to process the data to present the current spread as a movie.
TN013 ESD Failure Analysis of PV Module Diodes and TLP Test MethodWei Huang
Bypass diodes inserted across the strings of the solar panel arrays are essential to ensure the efficiency of the solar power system. However, those diodes are found to be susceptible to potential Electrostatic Discharge (ESD) events in the process of solar Photovoltaic (PV) panel manufacture, transportation and on-site installation. Please refer [1], where an International PV Module Quality Assurance Forum has been setup to investigate PV Module reliability, and Task Force 4 has been setting guidelines for testing the ESD robustness of diodes used to enhance PV panel performance. This document explains the theory behind the ESD damage and the proper test and analysis methods for ESD failure of diodes. To demonstrate the proposed testing methodology that follows, we will be evaluating six different types of diode models as supplied by our customer, who manufactures solar panel arrays.
TN006 frequency compensation method for vf-tlp measurementsWei Huang
The objective of this article is to demonstrate a frequency compensation technique for measuring the current and voltage of a device under test in a Very Fast Transmission Line Pulser (VF-TLP) test environment. The current measurement utilizes Non-Overlapping Time Domain Reflectometry, which is useful for On-Wafer testing because the measurement can be made with low profile small pitch probes, such as the Picoprobe Model 10. Further, to increase the bandwidth of the current measurement over common techniques, such as current transformers with 1GHz bandwidth, the method utilizes a resistive Pick-Off. The Pick-Off can be finely tuned to have as little insertion loss as possible, thereby enhancing the bandwidth. Although this method can also yield a DUT voltage measurement, the result suffers from numerical errors for low ohmic devices. A separate, direct measurement is presented that will demonstrate an extremely accurate voltage measurement that also utilizes frequency compensation.
Cable sizing to withstand short-circuit current - ExampleLeonardo ENERGY
A short circuit causes very extreme stresses in a cable which are proportional to the square of the current:
A temperature rise in the conducting components such as conductor, screen, metal sheath, armour. Indirectly the temperature of adjoining insulation and protective covers also increases,
electro-magnetic forces between the current-carrying components.
The temperature rise is important for its effect on ageing, heat pressure characteristics etc. and should be limited to a permissible short-circuit temperature. The thermo-mechanical effects of the current shall also be considered.
For the given short-circuit condition the short-circuit capacity of a cable should be investigated with respect to all these parameters. For multi-core cables in most instances the thermal effect - related to the magnitude of fault current and clearance time - is the critical parameter, since the cable will normally have enough mechanical strength. With single-core cables however the mechanical effect - related to the magnitude of the peak short-circuit current - is of such significance that, next to the thermal, the mechanical strength of both cable and its supports should be investigated.
Also accessories must be rated with respect to thermal and mechanical short-circuit stresses.
The short circuit strength of a cable system is not quantitatively defined with regard to permissible number of repeated short circuits, degree of deformation or destruction or impairment quality. It is expected, however, that a cable installation will remain safe in operation and that any deformation remains within tolerable limits even after several short circuits.
This course provides practical overview of short circuit performance of a cable.
In this paper, we propose and investigate a schottky tunneling source impact ionization MOSFET (STSIMOS)
with enhanced device performance. STS-IMOS has silicide (NiSi) source to lower the breakdown
voltage of conventional impact ionization MOS (IMOS). There is cumulative effect of both impact
ionization and source induced tunneling for the current gating mechanism of the device. The silicide source
offers immensely low parasitic resistance subsequently there is an increment in voltage drop across
intrinsic region. This leads to appreciable lowering of breakdown and threshold voltage for STS-IMOS.
Hence, it demonstrates enhanced device performance over conventional IMOS. Besides this for STS-IMOS
the location of maximum electric field has shifted towards the source and now it is quite away from gateoxide. Hence, it shows high immunity against Vth fluctuations due to hot electron damage. Consequently, itis found that device reliability is also improved significantly.
2012 Protection strategy for EOS (IEC 61000-4-5)Sofics
2012 Taiwan ESD and reliability conference
The standard IEC 61000-4-5 is used to characterize IC designs for EOS robustness. Each chip should achieve a minimum level of protection to withstand against EOS. Based on Long TLP and simulation, a strategy is developed to handle this requirement. The methodology has been applied for a T-con product in 130nm CMOS.
IRJET-Sensitivity Analysis of Maximum Overvoltage on Cables with Considering ...IRJET Journal
Hamed Touhidi ,Mehdi Shafiee, Behrooz Vahidi,Seyed Hossein Hosseinian, "Sensitivity Analysis of Maximum Overvoltage on Cables with Considering Forward and Backward Waves ", International Research Journal of Engineering and Technology (IRJET), Vol2,issue-01 April 2015. e-ISSN:2395-0056, p-ISSN:2395-0072. www.irjet.net
Abstract
lightning is known to be one of the primary sources of most surges in high keraunic areas. It is well-known fact that surge overvoltage is a significant contribution in cable failures. The other source of surge voltage is due to switching and it is pronounce on extra high voltage power transmission systems. The effect of both lightning and switching surges is weakening the cable insulation. The progressive weakening of such insulation will lead to cable deterioration and eventually its failure. Each surge impulse on the cable will contribute with other factors towards cable insulation strength deterioration and ultimately cable can fail by an overvoltage level below the cable basic impulse level (BIL). The maximum lightning overvoltage for a given cable depends on a large number of parameters. This paper presents the effect of model parameters (e.g., rise time and amplitude of surge, length of cable, resistivity of the core and sheath, tower footing resistance, number of sub conductors in the phase conductor (bundle), effect of surge arrester, length of lead, relative permittivity of the insulator material outside the core, power frequency voltage, stroke location, cable joints, shunt reactors, sheath thickness) on maximum cable voltage. The simulations show that the maximum overvoltage.
The following are the type tests recommended by the relevant IEC standard:
A) Dielectric Test.
B) Temperature Rise Test.
C) Breaking Test.
D) Tests For Time/Current Characteristics.
A POWER POINT PRESENTATION ON EMI (ELECTROMAGNETIC Interference) AND ELECTROMAGNETIC COMPATIBILITY (EMC).
Web link https://sah786.wordpress.com
http://www.Facebook.com/Sah92786
https://www.linkedin.com/in/arshad-hussain-8b0a2613b
https://www.slideshare.net/SaHussain1
This is basically a case study which is done on vehicles braking system which is effected due to emic effect which caused many accidents.
This presentation thus points out the emic effects and how it can be controlled in safety products
Cable sizing to withstand short-circuit current - ExampleLeonardo ENERGY
A short circuit causes very extreme stresses in a cable which are proportional to the square of the current:
A temperature rise in the conducting components such as conductor, screen, metal sheath, armour. Indirectly the temperature of adjoining insulation and protective covers also increases,
electro-magnetic forces between the current-carrying components.
The temperature rise is important for its effect on ageing, heat pressure characteristics etc. and should be limited to a permissible short-circuit temperature. The thermo-mechanical effects of the current shall also be considered.
For the given short-circuit condition the short-circuit capacity of a cable should be investigated with respect to all these parameters. For multi-core cables in most instances the thermal effect - related to the magnitude of fault current and clearance time - is the critical parameter, since the cable will normally have enough mechanical strength. With single-core cables however the mechanical effect - related to the magnitude of the peak short-circuit current - is of such significance that, next to the thermal, the mechanical strength of both cable and its supports should be investigated.
Also accessories must be rated with respect to thermal and mechanical short-circuit stresses.
The short circuit strength of a cable system is not quantitatively defined with regard to permissible number of repeated short circuits, degree of deformation or destruction or impairment quality. It is expected, however, that a cable installation will remain safe in operation and that any deformation remains within tolerable limits even after several short circuits.
This course provides practical overview of short circuit performance of a cable.
In this paper, we propose and investigate a schottky tunneling source impact ionization MOSFET (STSIMOS)
with enhanced device performance. STS-IMOS has silicide (NiSi) source to lower the breakdown
voltage of conventional impact ionization MOS (IMOS). There is cumulative effect of both impact
ionization and source induced tunneling for the current gating mechanism of the device. The silicide source
offers immensely low parasitic resistance subsequently there is an increment in voltage drop across
intrinsic region. This leads to appreciable lowering of breakdown and threshold voltage for STS-IMOS.
Hence, it demonstrates enhanced device performance over conventional IMOS. Besides this for STS-IMOS
the location of maximum electric field has shifted towards the source and now it is quite away from gateoxide. Hence, it shows high immunity against Vth fluctuations due to hot electron damage. Consequently, itis found that device reliability is also improved significantly.
2012 Protection strategy for EOS (IEC 61000-4-5)Sofics
2012 Taiwan ESD and reliability conference
The standard IEC 61000-4-5 is used to characterize IC designs for EOS robustness. Each chip should achieve a minimum level of protection to withstand against EOS. Based on Long TLP and simulation, a strategy is developed to handle this requirement. The methodology has been applied for a T-con product in 130nm CMOS.
IRJET-Sensitivity Analysis of Maximum Overvoltage on Cables with Considering ...IRJET Journal
Hamed Touhidi ,Mehdi Shafiee, Behrooz Vahidi,Seyed Hossein Hosseinian, "Sensitivity Analysis of Maximum Overvoltage on Cables with Considering Forward and Backward Waves ", International Research Journal of Engineering and Technology (IRJET), Vol2,issue-01 April 2015. e-ISSN:2395-0056, p-ISSN:2395-0072. www.irjet.net
Abstract
lightning is known to be one of the primary sources of most surges in high keraunic areas. It is well-known fact that surge overvoltage is a significant contribution in cable failures. The other source of surge voltage is due to switching and it is pronounce on extra high voltage power transmission systems. The effect of both lightning and switching surges is weakening the cable insulation. The progressive weakening of such insulation will lead to cable deterioration and eventually its failure. Each surge impulse on the cable will contribute with other factors towards cable insulation strength deterioration and ultimately cable can fail by an overvoltage level below the cable basic impulse level (BIL). The maximum lightning overvoltage for a given cable depends on a large number of parameters. This paper presents the effect of model parameters (e.g., rise time and amplitude of surge, length of cable, resistivity of the core and sheath, tower footing resistance, number of sub conductors in the phase conductor (bundle), effect of surge arrester, length of lead, relative permittivity of the insulator material outside the core, power frequency voltage, stroke location, cable joints, shunt reactors, sheath thickness) on maximum cable voltage. The simulations show that the maximum overvoltage.
The following are the type tests recommended by the relevant IEC standard:
A) Dielectric Test.
B) Temperature Rise Test.
C) Breaking Test.
D) Tests For Time/Current Characteristics.
A POWER POINT PRESENTATION ON EMI (ELECTROMAGNETIC Interference) AND ELECTROMAGNETIC COMPATIBILITY (EMC).
Web link https://sah786.wordpress.com
http://www.Facebook.com/Sah92786
https://www.linkedin.com/in/arshad-hussain-8b0a2613b
https://www.slideshare.net/SaHussain1
This is basically a case study which is done on vehicles braking system which is effected due to emic effect which caused many accidents.
This presentation thus points out the emic effects and how it can be controlled in safety products
Dielectric Spectroscopy in Time and Frequency DomainGirish Gupta
This presentation describes the basics and technicalities of Dielectric Spectroscopy in both time and frequency domain. IT also includes the procedure and results involved in Dielectric Spectroscopy on different dielectrics.
At the applied voltage a disc-shaped cavity with partial discharges are measured at variable frequency (0.01-50 Hz). By varying the frequency it was observed that measured PD phase, magnitude of distributions and number of PDs per voltage cycles are varied. In the cavity, sequence of Partial discharge is simulated dynamically. For that purpose a model is presented with charge consistent. Simulated results shows that cavity surface and emission properties are effected by varying the magnitude of applied frequency, mainly conductivity of surface. This paper is illustrating the frequency dependence of PD in a cavity. The paper illustrates how the applied voltage amplitude and the cavity size can influence the frequency dependence PD activity.
Lightning Characteristics and Impulse Voltage.Milton Sarker
Lightning characteristics and standard impulse
waveform are related to each other. But the lack
of realization about the relation between them
would make the solution to produce better
protection against lightning surge becomes
harder. Natural lightning surge waveform has
been compared to standard impulse waveform as
evidence that there have similarity between
them. The standard impulse waveform could be
used to test the strength of electrical equipment
against the lightning. Therefore designing and
simulating the impulse generator are the purpose
of this project beside to get better understanding
about lightning characteristics. This project aims
to develop an impulse generator circuit. The
main objectives of this work are two folds: the
first is the characterization of impulse voltages
and the second is the designing of an impulse
voltage generator. Our working purpose is to
give a concept about Impulse voltages and
impulse generator to the students and
researchers.
Modeling the Dependence of Power Diode on Temperature and RadiationIJPEDS-IAES
A theoretical study had been carried out on the effect of radiation on the
electrical properties of silicon power diodes. Computer program
"PDRAD2015" was developed to solve the diode equations and to
introduce the operating conditions and radiation effects upon its
parameters. Temperature increase interrupts the electrical properties of the
diode in the direction of drop voltage decrease across the p-n junction. The
model was analyzed under the influence of different radiation type (gammarays,
neutrons, protons and electrons) with various dose levels and
energies. The carrier’s diffusion lengths were seriously affected leading
to a large increase in the forward voltage. These effects were found to be
function of radiation type, fluence and energy.
Ultrasonic transducers are a key element that governs the performances of both generating and receiving ultrasound in an ultrasonic measurement system. Electrical impedance is a parameter sensitive to the environment of the transducer; it contains information about the transducer but also on the medium in which it is immersed. Several practical applications exploit this property. For this study, the model is implemented with the VHDL-AMS behavioral language. The simulations approaches presented in this work are based on the electrical Redwood model and its parameters are deduced from the transducer electroacoustic characteristics.
Risk in electrical work is more than any other job even using household purposes, its needs some precaution. Any slippage has no excuse. Fatal incident of a person will create a void place in his organization and family too. We can assume that working in electrical system is similar to that of work in war field. Those who are involved in electrical job they should be alert for each and every second. Mistake or failure will not be any of any excuse. Electricity is blunt and rude.In present paper we would like to enlighten some important areas which need special attention and also create awareness among the people who are working or using electrical power systems. This article is an attempt to cover most of the sub-titles of the paper.
ESDEMC’s TLP system is comparable to TLP systems from HPPI (High Power Pulse Instrument), Thermo Fisher Scientific, Barth Electronics, Grund Technical Solutions, Hanwa, etc…
A summary of TLP system comparison between ESDEMC ES620 series and few other competitors can be viewed at ESDEMC_TLP_System_Comparison .
Pb2012.01 an application of utilizing the system efficient-esd-design (seed) ...ESDEMC Technology LLC
Abstract—An LED circuit of a cell phone is analyzed using the System-Efficient-ESD-Design (SEED) methodology [1]. The method allows simulation of the ESD current path, and the interaction mechanisms between the clamp and the on-chip ESD protection circuit. The I-V curve and the non-linear behavior under high current pulses of every component including R, L, C, and ferrite beads are measured and modeled. By combining all of the component models, a complete circuit model is built for predicting the circuit behavior and damaging threshold at a given setting-voltage of a Transmission Line Pulser (TLP).
Honest Reviews of Tim Han LMA Course Program.pptxtimhan337
Personal development courses are widely available today, with each one promising life-changing outcomes. Tim Han’s Life Mastery Achievers (LMA) Course has drawn a lot of interest. In addition to offering my frank assessment of Success Insider’s LMA Course, this piece examines the course’s effects via a variety of Tim Han LMA course reviews and Success Insider comments.
June 3, 2024 Anti-Semitism Letter Sent to MIT President Kornbluth and MIT Cor...Levi Shapiro
Letter from the Congress of the United States regarding Anti-Semitism sent June 3rd to MIT President Sally Kornbluth, MIT Corp Chair, Mark Gorenberg
Dear Dr. Kornbluth and Mr. Gorenberg,
The US House of Representatives is deeply concerned by ongoing and pervasive acts of antisemitic
harassment and intimidation at the Massachusetts Institute of Technology (MIT). Failing to act decisively to ensure a safe learning environment for all students would be a grave dereliction of your responsibilities as President of MIT and Chair of the MIT Corporation.
This Congress will not stand idly by and allow an environment hostile to Jewish students to persist. The House believes that your institution is in violation of Title VI of the Civil Rights Act, and the inability or
unwillingness to rectify this violation through action requires accountability.
Postsecondary education is a unique opportunity for students to learn and have their ideas and beliefs challenged. However, universities receiving hundreds of millions of federal funds annually have denied
students that opportunity and have been hijacked to become venues for the promotion of terrorism, antisemitic harassment and intimidation, unlawful encampments, and in some cases, assaults and riots.
The House of Representatives will not countenance the use of federal funds to indoctrinate students into hateful, antisemitic, anti-American supporters of terrorism. Investigations into campus antisemitism by the Committee on Education and the Workforce and the Committee on Ways and Means have been expanded into a Congress-wide probe across all relevant jurisdictions to address this national crisis. The undersigned Committees will conduct oversight into the use of federal funds at MIT and its learning environment under authorities granted to each Committee.
• The Committee on Education and the Workforce has been investigating your institution since December 7, 2023. The Committee has broad jurisdiction over postsecondary education, including its compliance with Title VI of the Civil Rights Act, campus safety concerns over disruptions to the learning environment, and the awarding of federal student aid under the Higher Education Act.
• The Committee on Oversight and Accountability is investigating the sources of funding and other support flowing to groups espousing pro-Hamas propaganda and engaged in antisemitic harassment and intimidation of students. The Committee on Oversight and Accountability is the principal oversight committee of the US House of Representatives and has broad authority to investigate “any matter” at “any time” under House Rule X.
• The Committee on Ways and Means has been investigating several universities since November 15, 2023, when the Committee held a hearing entitled From Ivory Towers to Dark Corners: Investigating the Nexus Between Antisemitism, Tax-Exempt Universities, and Terror Financing. The Committee followed the hearing with letters to those institutions on January 10, 202
Biological screening of herbal drugs: Introduction and Need for
Phyto-Pharmacological Screening, New Strategies for evaluating
Natural Products, In vitro evaluation techniques for Antioxidants, Antimicrobial and Anticancer drugs. In vivo evaluation techniques
for Anti-inflammatory, Antiulcer, Anticancer, Wound healing, Antidiabetic, Hepatoprotective, Cardio protective, Diuretics and
Antifertility, Toxicity studies as per OECD guidelines
Model Attribute Check Company Auto PropertyCeline George
In Odoo, the multi-company feature allows you to manage multiple companies within a single Odoo database instance. Each company can have its own configurations while still sharing common resources such as products, customers, and suppliers.
Francesca Gottschalk - How can education support child empowerment.pptxEduSkills OECD
Francesca Gottschalk from the OECD’s Centre for Educational Research and Innovation presents at the Ask an Expert Webinar: How can education support child empowerment?
Synthetic Fiber Construction in lab .pptxPavel ( NSTU)
Synthetic fiber production is a fascinating and complex field that blends chemistry, engineering, and environmental science. By understanding these aspects, students can gain a comprehensive view of synthetic fiber production, its impact on society and the environment, and the potential for future innovations. Synthetic fibers play a crucial role in modern society, impacting various aspects of daily life, industry, and the environment. ynthetic fibers are integral to modern life, offering a range of benefits from cost-effectiveness and versatility to innovative applications and performance characteristics. While they pose environmental challenges, ongoing research and development aim to create more sustainable and eco-friendly alternatives. Understanding the importance of synthetic fibers helps in appreciating their role in the economy, industry, and daily life, while also emphasizing the need for sustainable practices and innovation.
Read| The latest issue of The Challenger is here! We are thrilled to announce that our school paper has qualified for the NATIONAL SCHOOLS PRESS CONFERENCE (NSPC) 2024. Thank you for your unwavering support and trust. Dive into the stories that made us stand out!
Unit 8 - Information and Communication Technology (Paper I).pdfThiyagu K
This slides describes the basic concepts of ICT, basics of Email, Emerging Technology and Digital Initiatives in Education. This presentations aligns with the UGC Paper I syllabus.
Macroeconomics- Movie Location
This will be used as part of your Personal Professional Portfolio once graded.
Objective:
Prepare a presentation or a paper using research, basic comparative analysis, data organization and application of economic information. You will make an informed assessment of an economic climate outside of the United States to accomplish an entertainment industry objective.
Pb2003.01 problems with the electrostatic discharge (esd) immunity test in electromagnetic compatibility (emc)
1. Asia-Pacific Conferenceon Environmental Electromagnetics
CEEM' 2003 Nov. 47,2003 HanPzhou.China
PROBLEMS WITH THE ELECTROSTATICDISCHARGE (ESD)
IMMUNITY TEST IN ELECTROMAGNETIC COMPATIBILITY(EMC)
Jiusheng Huang*, David Pommerenke**, Wei Huang**
*)Beijing Institute of Electromechanical Technology,Beijing, China,jshuang@ESD-China.Com
**) Electromagnetic Compatibility Laboratory,University of Missouri-Rolla, USA
***) Beijing University of Post and Telecommunication, Beijing, China
Abstract- Electrostatic discharge (ESD) immunity
test is one of the important electromagnetic
compatibility (EMC) tests. The IEC standard
IECdlOOO-4-2 is the widely used standard to test
the ESD immunity for electronic equipments.
Many amendments such as amendment 1 (1998),
amendment 2 (2000) have been published since
1995, but there is still problems with the ESD
immunity test even with the 200x version. More
than six ESD generators of different bands are
tested for different equipments. The results show
that the failure voltages of diferent ESD
generators are vary muchfrom different bandsfor
the same test equipment. This may lead to the
results incomparable when test the ESD immunity
test in the EMC. Further studies show that there is
a good correlation between thefailure voltage and
the induced voltage.
1. Introduction
The electrostatic discharge (ESD) current
waveform of the IEC61000-4-2 s&ndard[11 is
shown in figure 1. It says the rise time of the first
peak is 0.7-1 ns and the current is in the range of
3.375-4.125 A/kv. The current at 30 ns is in the
range of 1.4-2.6 A/kv and the current at 60 ns is in
the range of 0.7-1.3~kv.Many works were made
on the research of the ESD current,
electromagnetic and magnetic field radiated from
the ESD[2-51. Any ESD generator is standard if its
ESD current is per IEC61000-4-2 standard. The
failure ESD voltage for the same equipment
should be the same in certain tolerances. But the
failure voltages for the same equipment are very
large for more than six bands of ESD generators.
This paper is to investigate the main reasons and
the factors which influence the compatibility of
the results.
3.75 +I- lox I I
I
60"s
^crc
lr = 0 7 b 1 ns
Fig. 1 ESD current waveform of the IEC61000-4-2
standard
2. Test
2.1 Test setups
More than six bands of ESD simulators from
different factors were used as the test equipment
of the experiment. A high speed oscilloscope
(TekTonix TDS7404 Phosphor oscilloscope 4GHz,
20GS/s) and ESD current targets and field sensors
were used as the main equipment in our
experiment.
2.2. Test Results
7-5I
2. All the ESD generators are calibrated as the
IEC61000-4-2 standard requirements. They have
the same ESD current as the standard. The ESD
failure voltages of the same electronic equipment
for different bands of ESD generators were tested.
The failure voltage may be very much from 1kV
to even 6kV for the same equipment even if all the
ESD current are accordant with the same standard.
This may lead to the results incomparable when
test the ESD immunity test in the EMC.
._._.- - . . . - . ..... - . --- .- ... .-
0
7
6
5
4
3
2
1
n
Fig. 2 ESD susceptibility of computer by different
ESD generators with the same ESD currents
2.2.1 The influence of the ground strip to the
ESD current waveform
Many factors such as the parasitic capacitors and
inductors will influence the waveform of the ESD
current and the failure voltage in our experiments.
The rise time, the first peak of the ESD current
and the shape of waveforms of the ESD current
are easily influenced by those factors. But those
parasitic capacitors and inductors are constant in a
given ESD generator when it is made in the factor.
Other factors such as the length and shape of the
ground strip are vary in the practice experiment.
The waveform of the second segment is
influenced by the RC network and the shape and
position of the ground strip. Several tests are made
to demonstrate the effects. A ESD generator is
used to test the waveform. The results are shown
in figure 3 and figure 4. Figure 4 has some offset
in order to observe easily (Total Y offset 70%,
Total X offset 20%)
Fig. 3 The ESD current waveform influenced by the
differentshape and position of the ground strip
Fig. 4 The ESD current waveform (shown in
different offset of XY position) influenced by the
differentshape and position of the ground strip
It can be seen from figure 3 and figure 4 that when
the ground strip is in winding, that is the
inductance is very large, the waveform (Black)
vibrating during the decay period. When the
ground strip is in straight line, the waveform (Blue)
is very similar to the waveform proposed by IEC
standard. When tlhe ground strip is in other shape
and position, the waveform is also influenced by
the inductance.
2.2.2 ESD induced voltage
Voltage induced by both the electric field and
magnetic field radiated from ESD at a given
distance can be easily measured than that of the
252
3. electric field and magnetic field. It is mainly the
induced voltage which makes the electronic
equipment failure. So, more attention will be paid
to the induced voltage.
There &e two typical induced voltages which
represent the real effects of ESD. One is the
monopole induced voltage. It is mainly induced by
electric field. Another is the loop induced voltage
which may be induced by both magnetic field and
electric field if the sensor is not electric shielded.
In order to test the ESD current, monopole
induced voltage and loop induced voltage. Three
channels of the digital oscilloscope is connected to
ESD current target, monopole with 10" length
and the half circular loop with diameter of 13 mm
respectively. It will be unstable due to the lower
sampling rate when three or more channels are
used simultaneously. But the concurrent
phenomena can be easily observed.
7
'
-
4
6-
5 -
> . .._-3 4 -
s
2 3 -
n .
V I ,
0
In 2 -w
1 -
dllll dxl.3( dJ-I.E
i
n1 m v n hll TYIxSraCnlr 1a**
Ch3 Zahv a D* m m II b b o r m h v
Fig.5 ESD current, monopole induced voltage and
loop inducedvoltage r
2.3 ESD current and ESD induced voltage
In order to test the ESD current and ESD induced
voltage in the sensor. Two channels of the
oscilloscope are connected the ESD current target
and the loop sensor. The ESD current is much
varies with the ESD induced voltage in shape and
duration. The induced voltage is very short in
duration than that of the ESD current shown in
Fig.6. The induced voltage may be small just like
noise after several ns even if the ESD current is
increase.
I
i
_ - --Q1lnlwJ C Ch2 5nCral C
Fig. 6
shorttime of lOns
Figure 6 shows that the ESD current will increase
after 10 nanoseconds due to the discharge of the
capacitor in the ESD. But the induced voltage
doesn't increase any more. This further
demonstrates that the induced voltage doesn't
correlate with the ESD current.
ESD currentand ESD induced voltage in the
I 7 1
.I y=6.91881-9.71634~1
',~.. Correlation coefficientR= 4.88567
."-... Standard deviationSD= 0.86476
."
'...I'.
.'....... .'... '...
".m
a...
0.2 0.3 0.4 0.5 0.6
ESD Induced Loop Voltage Vp-p(V)
7
0.7
I '
Fig. 7
For the same equipment the failure level of
discharge may be from 1kV to 6kV. But there is
good correlation between the ESD susceptibility
and induced voltage from different simulators. The
correlation coefficient R= -0.88567, standard
deviation SD= 0.86476[2].
ESD susceptibilityand induced voltage
253
4. 3. Conclusions and Future Works
ESD current for different ESD simulators are
tested. The ESD susceptibility of computer with
different CPU and auto switch are experimentally
investigaied. ESD induced voltage are tested for
different ESD simulators. Some conclusions are
summarized [51.
1. The parasitic inductor and capacitor of the
ESD simulator are critical factors which will
influenced the both the waveform of the ESD
current and the ESD model of discharge, Different
ESD simulators have different parasitic parameters
that lead to the different ESD susceptibility.
2. The shape and position of the ground strip of
the ESD simulator will influence the inductor of
the LCR and lead to the generation of different
waveform of the ESD current. These two factors
are mainly source lead to the variation of the ESD
susceptibility of the electronic equipment.
3. ESD induced voltage doesn’t correlate with the
ESD current but it is correlated with the induced
voltage. It is generated by the process of contact of
the relay in the ESD. The duration of the ESD
voltage is about 5 nanoseconds and the typical
duration of ESD current is more than 100
nanoseconds.
The ESD susceptibility is very complicated. It
may be influenced by both the ESD current and
Electromagnetic,and magnetic field radiated from
the ESD. If the ESD current and the induced
voltage can be defined more exactly, the ESD
susceptibility test results may be more repeatable
I
Acknowledgements
Thanks go out to Dr. Thomas Van Doren of EMC
laboratory, University of Missouri-Rolla for his
warmly supports to the ESD work, Kai Wang and
all students in UMR for their supports and helps
during my stay in UMR from 2002-2003.
[I] IEC 61000-4-2 Electromagnetic Compatibility
(EMC)- Part 4-:!: Testing and measurement
techniques -Electrostatic discharge immunity test
(1995,1998,2000)
[2]Jiusheng Huang, David Pommerenke etc.
Investigation of ESD Current and Induced Voltage
from Different ESD Simulators, Proceeding of
ESA-IEEE Joint ’4nnual Meetings, Little Rock,
Arkansas,USA, June. 24-28,2003
[3] The Study of Transient Fields Generated by
Typical ESD Models, Proceedings of the Fourth
Intemational Conference on Applied Electrostatics,
The 4th Intemational Conference on Applied
Electrostatics, pp.585-588, Dalian, China,
[4]Pommerenke, D., Aidam, M., ‘ESD: Waveform
calculation, field and current of human and simulator
ESD’, Journal of Electrostatics, Vol. 38, Issues 1-2,
Oct.8-12,2001
Oct. 1996,pp. 33 - 51
[5] Jiusheng Huang, ESD Test report, EMC
Laboratory, Univers.ityof Missouri-Rolla,USA
‘References