This document describes a method for simulating electrostatic discharge (ESD) protection circuits using empirical models of ESD devices. The method combines regular SPICE models of ESD transistors with curves based on transmission line pulsing (TLP) measurements. The models trigger bipolar behavior based on simulated terminal voltages and TLP data. Simulation results matched TLP curves and demonstrated checking ESD current and voltage clamping. The method allows verifying ESD protection in complex chip designs.
The document discusses various integrated circuit packaging technologies. It describes through-hole packages, surface mount packages, chip-scale packages including wire bonded ball grid arrays and flip chip ball grid arrays. It then focuses on wafer level chip-scale packages, explaining that they are manufactured by building up interconnect structures directly on the silicon wafer before dicing. Key advantages of wafer level chip-scale packages are their small size, minimized inductance, and streamlined manufacturing process.
Introduction to FINFET, Details of FinFETJustin George
1) The document discusses FinFET, a type of non-planar transistor used in modern semiconductor fabrication. It describes the construction of FinFET which involves etching fins on an SOI substrate and wrapping gates around the fins.
2) FinFET works by having an elevated fin-shaped channel that the gate wraps around. This allows FinFET to operate at lower voltage and offer higher drive current compared to planar transistors.
3) FinFET technology is being widely adopted in integrated circuits due to advantages like suppressed short channel effect, better drive current, lower leakage power, and no random dopant fluctuation.
This document summarizes the design and performance analysis of 20nm silicon/germanium channel pentagonal and trapezoidal nanowire transistors. It presents the objectives of designing these nanowire transistors with different process parameters like diameter and height. The methodology involves using TCAD software to simulate the transfer characteristics, output characteristics, and short channel effects for different cross-sectional shapes and materials. The results show that pentagonal and trapezoidal nanowire transistors with germanium channels exhibit higher on-currents and on/off current ratios than triangular nanowire transistors. Key performance metrics like subthreshold swing and DIBL are also better for the pentagonal and trapezoidal nanowire transistors.
This document describes a method for simulating electrostatic discharge (ESD) protection circuits using empirical models of ESD devices. The method combines regular SPICE models of ESD transistors with curves based on transmission line pulsing (TLP) measurements. The models trigger bipolar behavior based on simulated terminal voltages and TLP data. Simulation results matched TLP curves and demonstrated checking ESD current and voltage clamping. The method allows verifying ESD protection in complex chip designs.
The document discusses various integrated circuit packaging technologies. It describes through-hole packages, surface mount packages, chip-scale packages including wire bonded ball grid arrays and flip chip ball grid arrays. It then focuses on wafer level chip-scale packages, explaining that they are manufactured by building up interconnect structures directly on the silicon wafer before dicing. Key advantages of wafer level chip-scale packages are their small size, minimized inductance, and streamlined manufacturing process.
Introduction to FINFET, Details of FinFETJustin George
1) The document discusses FinFET, a type of non-planar transistor used in modern semiconductor fabrication. It describes the construction of FinFET which involves etching fins on an SOI substrate and wrapping gates around the fins.
2) FinFET works by having an elevated fin-shaped channel that the gate wraps around. This allows FinFET to operate at lower voltage and offer higher drive current compared to planar transistors.
3) FinFET technology is being widely adopted in integrated circuits due to advantages like suppressed short channel effect, better drive current, lower leakage power, and no random dopant fluctuation.
This document summarizes the design and performance analysis of 20nm silicon/germanium channel pentagonal and trapezoidal nanowire transistors. It presents the objectives of designing these nanowire transistors with different process parameters like diameter and height. The methodology involves using TCAD software to simulate the transfer characteristics, output characteristics, and short channel effects for different cross-sectional shapes and materials. The results show that pentagonal and trapezoidal nanowire transistors with germanium channels exhibit higher on-currents and on/off current ratios than triangular nanowire transistors. Key performance metrics like subthreshold swing and DIBL are also better for the pentagonal and trapezoidal nanowire transistors.
Wire bonding is used to electrically interconnect integrated circuits to packages so they can be handled, tested, and used in electronic products. There are two main types of wire bonding: ball bonding and wedge bonding. Ball bonding uses a capillary tool to form a ball bond on the chip and substrate, while wedge bonding uses a wedge tool. Wire bonding allows for high-speed, economical connections and is the most common interconnection method. It enables signals and power to be distributed from the packaged IC to the rest of the system while also providing mechanical support and environmental protection.
1. The document discusses NMOS and CMOS inverter circuits. It describes the operation of an NMOS inverter using an enhancement load, depletion load, and resistor load.
2. A CMOS inverter uses both an NMOS and PMOS transistor to provide complementary output signals. It has advantages over NMOS inverters like zero static power dissipation and full voltage swing at the output.
3. The voltage transfer curve of a CMOS inverter is discussed along with the load lines showing the different operating regions of the NMOS and PMOS transistors.
The twin well process allows for separate optimization of n-type and p-type transistors. It involves depositing a lightly doped epitaxial layer on an n+ or p+ substrate, then forming n-wells and p-wells in this layer through independent doping steps. This allows the dopant concentrations to be carefully tuned to produce desired device characteristics for both transistor types. The key steps are tub formation through n-well and p-well implantation and diffusion, polysilicon gate formation, and contact definition and metallization to connect the transistors. The main advantage is obtaining balanced performance from n-type and p-type transistors through separate well optimization.
This document discusses ESD protection technology for power ICs. It begins with an introduction to ESD and ESD failure models. It then covers ESD protection design considerations for power ICs, including high voltage ESD device solutions, ESD circuit solutions, whole chip ESD protection circuit design, and low voltage ESD device solutions. The document also discusses ESD protection design flow and analysis methods like TLP testing. It concludes by addressing emerging ESD protection technology issues related to shrinking design windows, high voltage and low voltage ICs, and system-level ESD stresses.
This document discusses the CMOS inverter. It explains the switch models of the CMOS inverter and how the input signals determine whether the NMOS or PMOS transistor is on. It also discusses the properties of static CMOS inverters, including their voltage transfer characteristic curve and noise margins. The document describes how process variations and supply voltage scaling can impact the inverter's performance. Finally, it examines the dynamic behavior of the CMOS inverter and the parasitic capacitances that affect its switching speeds.
HIGH-K DEVICES BY ALD FOR SEMICONDUCTOR APPLICATIONSJonas Sundqvist
This document summarizes research on high-k dielectric devices fabricated using atomic layer deposition (ALD) for semiconductor applications presented by researchers from the Fraunhofer Institute for Photonic Microsystems. It discusses the history of ALD deposition of high-k materials like TiO2 and laminates of Ta2O5 and HfO2 for capacitor applications in the 1990s. It also summarizes the development of TiN/ZrO2-based capacitors and research on ALD HfO2 for emerging ferroelectric memory devices. Finally, it discusses the fabrication of 3D capacitor structures using ALD with densities over 250 nF/mm2 and possibilities for 3D integration of ferroelectric HfO2
This document discusses short channel effects that occur in MOSFET devices when the channel length decreases to the same order of magnitude as the source/drain junction depth. It describes five main short channel effects: drain induced barrier lowering, drain punch through, velocity saturation, impact ionization, and hot electron effects. For each effect, it provides an explanation of the physical phenomenon and how it impacts device performance as the channel length decreases. It concludes by listing three references for further reading on leakage current mechanisms and MOSFET modeling.
The document provides an overview of the history and evolution of semiconductors and integrated circuits from 1947 to present. It discusses key inventions and milestones such as the transistor in 1947, the integrated circuit in 1961, and Moore's Law predicting transistor doubling every two years. It also covers different chip design approaches including full custom, standard cell, gate arrays, and FPGAs, along with their relative costs, performance, and design complexities.
This document discusses channel length modulation in MOSFETs. It explains that in saturation, the channel length decreases with increasing drain voltage due to the depletion region extending farther into the channel. This effectively reduces the channel length and increases the drain current. The document derives an expression for drain current that includes a channel length modulation coefficient to model this effect, showing that current increases with higher drain voltages due to the reduced channel length.
This document discusses Surface Mount Technology (SMT), which involves mounting electronic components directly onto the surface of printed circuit boards rather than inserting them into holes. It provides an overview of SMT, including its advantages over traditional through-hole mounting, different types of SMT, surface mount components, the SMT assembly process, and applications. Key advantages noted are higher density packaging, improved reliability, and easier automation of the manufacturing process.
This document discusses the gradual channel approximation (GCA) MOS transistor model for strong inversion operation. It provides three equations to model the MOSFET current-voltage characteristics in the linear/triode region, saturation region, and includes channel length modulation. Diagrams and an example are provided to illustrate the transistor operation and equations in each region.
1) Parasitic elements are unavoidable in electrical components and arise from unwanted resistance, inductance, and capacitance.
2) Integrated passive elements can provide benefits like smaller size and improved performance at high frequencies by reducing parasitic effects.
3) Various integration technologies like laminate-based, LTCC-based, and thin-film-based approaches are used to integrate passive elements like inductors, capacitors, and resistors onto substrates.
The document discusses LTCC (low temperature co-fired ceramics) passive integration, including challenges. It provides an overview of LTCC materials and processes, comparing LTCC to other integration technologies. Key advantages of LTCC include its parallel layer process, ability to achieve high layer counts up to 100 layers, compatibility with RF-friendly materials, and potential for high component density and module reliability. However, challenges for LTCC include limitations on forming precise resistors and inductors. The document also reviews common LTCC dielectric materials and provides details on Motorola's high-Q T2000 LTCC dielectric composition.
A printed circuit board (PCB) is used in electronics to build electronic devices. It provides both a place to mount electronic components and the means to electrically connect them. A PCB has conducting copper layers that are typically coated with a green solder mask. Unwanted copper is removed via etching, leaving only the desired copper traces. Components, pads, traces, vias, and metal layers make up the basic structure and function of a PCB.
The document discusses input/output (I/O) circuits and packaging for integrated circuits. It begins by describing how chips are connected to the outside world via I/O circuits, bonding wires, and packages. It then discusses the main properties and requirements of packages, including electrical characteristics, number of I/O pins, and thermal properties. The document outlines different packaging technologies like wire bonding and flip chip packaging. It also discusses I/O circuit requirements and different types of I/O cells like digital I/O buffers and analog I/O cells. Finally, it briefly introduces system-in-package technologies that integrate multiple silicon chips or dies into a single package using techniques like multi-chip modules, silicon interposers,
The document discusses printed circuit boards (PCBs) and their evolution and classifications. It explains that PCBs provide electrical connections between circuit components using conductive tracks on a non-conductive substrate. Early electronic designs used point-to-point wiring but PCBs allowed for more reliable connections. Basic PCB types include single-sided, double-sided, and multilayer boards. More advanced types include rigid-flex boards, which combine rigid and flexible areas to fit devices. Proper PCB design is important to address issues like signal interference at high frequencies.
Schottky diodes operate at high frequencies because they do not have a depletion layer or stored charges. This allows them to turn on and off very quickly without a reverse recovery time. They consist of a metal and n-type semiconductor junction with a low Schottky barrier of 0.15-0.45 volts. At this junction, electrons can easily tunnel from the n-type material to the metal under forward bias. This fast operation makes Schottky diodes useful for rectification at frequencies over 300 MHz and for applications requiring low voltage and fast switching like computers.
Intel has achieved a breakthrough in transistor technology by developing high-k + metal gate transistors for its 45 nm process. These transistors significantly reduce leakage power and are the biggest advancement since polysilicon gate MOS transistors were introduced in the 1960s. Intel has made working 45 nm microprocessors using these new transistors, which will deliver higher performance and greater energy efficiency. Intel's 45 nm products are on track to begin production in late 2007 with three factories manufacturing 45 nm by early 2008.
The document discusses different types of ESD (electrostatic discharge) and EOS (electrical overstress) testing methods. It provides an overview of the Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM) test methods, including their relevant standards, test procedures, waveforms, and device classification levels. It also discusses the history and evolution of these ESD test methods over time as standards have been developed and refined by organizations like ESDA, JEDEC, AEC, and others.
Wire bonding is used to electrically interconnect integrated circuits to packages so they can be handled, tested, and used in electronic products. There are two main types of wire bonding: ball bonding and wedge bonding. Ball bonding uses a capillary tool to form a ball bond on the chip and substrate, while wedge bonding uses a wedge tool. Wire bonding allows for high-speed, economical connections and is the most common interconnection method. It enables signals and power to be distributed from the packaged IC to the rest of the system while also providing mechanical support and environmental protection.
1. The document discusses NMOS and CMOS inverter circuits. It describes the operation of an NMOS inverter using an enhancement load, depletion load, and resistor load.
2. A CMOS inverter uses both an NMOS and PMOS transistor to provide complementary output signals. It has advantages over NMOS inverters like zero static power dissipation and full voltage swing at the output.
3. The voltage transfer curve of a CMOS inverter is discussed along with the load lines showing the different operating regions of the NMOS and PMOS transistors.
The twin well process allows for separate optimization of n-type and p-type transistors. It involves depositing a lightly doped epitaxial layer on an n+ or p+ substrate, then forming n-wells and p-wells in this layer through independent doping steps. This allows the dopant concentrations to be carefully tuned to produce desired device characteristics for both transistor types. The key steps are tub formation through n-well and p-well implantation and diffusion, polysilicon gate formation, and contact definition and metallization to connect the transistors. The main advantage is obtaining balanced performance from n-type and p-type transistors through separate well optimization.
This document discusses ESD protection technology for power ICs. It begins with an introduction to ESD and ESD failure models. It then covers ESD protection design considerations for power ICs, including high voltage ESD device solutions, ESD circuit solutions, whole chip ESD protection circuit design, and low voltage ESD device solutions. The document also discusses ESD protection design flow and analysis methods like TLP testing. It concludes by addressing emerging ESD protection technology issues related to shrinking design windows, high voltage and low voltage ICs, and system-level ESD stresses.
This document discusses the CMOS inverter. It explains the switch models of the CMOS inverter and how the input signals determine whether the NMOS or PMOS transistor is on. It also discusses the properties of static CMOS inverters, including their voltage transfer characteristic curve and noise margins. The document describes how process variations and supply voltage scaling can impact the inverter's performance. Finally, it examines the dynamic behavior of the CMOS inverter and the parasitic capacitances that affect its switching speeds.
HIGH-K DEVICES BY ALD FOR SEMICONDUCTOR APPLICATIONSJonas Sundqvist
This document summarizes research on high-k dielectric devices fabricated using atomic layer deposition (ALD) for semiconductor applications presented by researchers from the Fraunhofer Institute for Photonic Microsystems. It discusses the history of ALD deposition of high-k materials like TiO2 and laminates of Ta2O5 and HfO2 for capacitor applications in the 1990s. It also summarizes the development of TiN/ZrO2-based capacitors and research on ALD HfO2 for emerging ferroelectric memory devices. Finally, it discusses the fabrication of 3D capacitor structures using ALD with densities over 250 nF/mm2 and possibilities for 3D integration of ferroelectric HfO2
This document discusses short channel effects that occur in MOSFET devices when the channel length decreases to the same order of magnitude as the source/drain junction depth. It describes five main short channel effects: drain induced barrier lowering, drain punch through, velocity saturation, impact ionization, and hot electron effects. For each effect, it provides an explanation of the physical phenomenon and how it impacts device performance as the channel length decreases. It concludes by listing three references for further reading on leakage current mechanisms and MOSFET modeling.
The document provides an overview of the history and evolution of semiconductors and integrated circuits from 1947 to present. It discusses key inventions and milestones such as the transistor in 1947, the integrated circuit in 1961, and Moore's Law predicting transistor doubling every two years. It also covers different chip design approaches including full custom, standard cell, gate arrays, and FPGAs, along with their relative costs, performance, and design complexities.
This document discusses channel length modulation in MOSFETs. It explains that in saturation, the channel length decreases with increasing drain voltage due to the depletion region extending farther into the channel. This effectively reduces the channel length and increases the drain current. The document derives an expression for drain current that includes a channel length modulation coefficient to model this effect, showing that current increases with higher drain voltages due to the reduced channel length.
This document discusses Surface Mount Technology (SMT), which involves mounting electronic components directly onto the surface of printed circuit boards rather than inserting them into holes. It provides an overview of SMT, including its advantages over traditional through-hole mounting, different types of SMT, surface mount components, the SMT assembly process, and applications. Key advantages noted are higher density packaging, improved reliability, and easier automation of the manufacturing process.
This document discusses the gradual channel approximation (GCA) MOS transistor model for strong inversion operation. It provides three equations to model the MOSFET current-voltage characteristics in the linear/triode region, saturation region, and includes channel length modulation. Diagrams and an example are provided to illustrate the transistor operation and equations in each region.
1) Parasitic elements are unavoidable in electrical components and arise from unwanted resistance, inductance, and capacitance.
2) Integrated passive elements can provide benefits like smaller size and improved performance at high frequencies by reducing parasitic effects.
3) Various integration technologies like laminate-based, LTCC-based, and thin-film-based approaches are used to integrate passive elements like inductors, capacitors, and resistors onto substrates.
The document discusses LTCC (low temperature co-fired ceramics) passive integration, including challenges. It provides an overview of LTCC materials and processes, comparing LTCC to other integration technologies. Key advantages of LTCC include its parallel layer process, ability to achieve high layer counts up to 100 layers, compatibility with RF-friendly materials, and potential for high component density and module reliability. However, challenges for LTCC include limitations on forming precise resistors and inductors. The document also reviews common LTCC dielectric materials and provides details on Motorola's high-Q T2000 LTCC dielectric composition.
A printed circuit board (PCB) is used in electronics to build electronic devices. It provides both a place to mount electronic components and the means to electrically connect them. A PCB has conducting copper layers that are typically coated with a green solder mask. Unwanted copper is removed via etching, leaving only the desired copper traces. Components, pads, traces, vias, and metal layers make up the basic structure and function of a PCB.
The document discusses input/output (I/O) circuits and packaging for integrated circuits. It begins by describing how chips are connected to the outside world via I/O circuits, bonding wires, and packages. It then discusses the main properties and requirements of packages, including electrical characteristics, number of I/O pins, and thermal properties. The document outlines different packaging technologies like wire bonding and flip chip packaging. It also discusses I/O circuit requirements and different types of I/O cells like digital I/O buffers and analog I/O cells. Finally, it briefly introduces system-in-package technologies that integrate multiple silicon chips or dies into a single package using techniques like multi-chip modules, silicon interposers,
The document discusses printed circuit boards (PCBs) and their evolution and classifications. It explains that PCBs provide electrical connections between circuit components using conductive tracks on a non-conductive substrate. Early electronic designs used point-to-point wiring but PCBs allowed for more reliable connections. Basic PCB types include single-sided, double-sided, and multilayer boards. More advanced types include rigid-flex boards, which combine rigid and flexible areas to fit devices. Proper PCB design is important to address issues like signal interference at high frequencies.
Schottky diodes operate at high frequencies because they do not have a depletion layer or stored charges. This allows them to turn on and off very quickly without a reverse recovery time. They consist of a metal and n-type semiconductor junction with a low Schottky barrier of 0.15-0.45 volts. At this junction, electrons can easily tunnel from the n-type material to the metal under forward bias. This fast operation makes Schottky diodes useful for rectification at frequencies over 300 MHz and for applications requiring low voltage and fast switching like computers.
Intel has achieved a breakthrough in transistor technology by developing high-k + metal gate transistors for its 45 nm process. These transistors significantly reduce leakage power and are the biggest advancement since polysilicon gate MOS transistors were introduced in the 1960s. Intel has made working 45 nm microprocessors using these new transistors, which will deliver higher performance and greater energy efficiency. Intel's 45 nm products are on track to begin production in late 2007 with three factories manufacturing 45 nm by early 2008.
The document discusses different types of ESD (electrostatic discharge) and EOS (electrical overstress) testing methods. It provides an overview of the Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM) test methods, including their relevant standards, test procedures, waveforms, and device classification levels. It also discusses the history and evolution of these ESD test methods over time as standards have been developed and refined by organizations like ESDA, JEDEC, AEC, and others.
This document compares ESD failure tests using different test methods: ESD gun simulator, Transmission Line Pulse (TLP), and Human Metal Model (HMM). A test IC (0531Z) was subjected to these tests. TLP and HMM tests both accurately predicted the failure levels observed in ESD gun testing. Specifically:
1. TLP testing at 100ns and 400ns pulses yielded failure levels of ±19A and ±11.5A respectively, matching the ESD gun failure levels of 10.5-13.5kV.
2. HMM testing with a 50ohm matched setup showed failure starting around 40A peak current, equivalent to 10-15kV E
This document provides an overview of electromagnetic interference (EMI) test methods and instrumentation. It defines electromagnetic compatibility (EMC) and describes the electromagnetic environment. Common EMI sources and victims are identified. Key EMI test methods are outlined, including radiated emission (RE) testing, conducted emission (CE) testing, radiated susceptibility (RS) testing, and conducted susceptibility (CS) testing. Critical EMI testing facilities and instrumentation are discussed, such as anechoic chambers, shield rooms, open area test sites (OATS), EMI test receivers, spectrum analyzers, and EMI test signal generators. EMC regulations and standards around the world are also briefly summarized.
I would like to share some knowledge of surge protection devices.
This presentation highlights some concepts of surge and surge protectors.
Presentation Index is as follows:
> Types of Surge
> Sources of Surge
> Surge Current & Voltage waveform
> Importance of Surge Protectors
> Types of Surge protectors
> Location of Surge Protectors
This document describes characterizing touch panel sensor failures from electrostatic discharge (ESD) using current-voltage (IV) curve transient line pulse (TLP) testing. It outlines different ESD damage scenarios on touch panels and challenges with current testing methods. The presentation proposes using IV-TLP probing to inject ESD locally and measure current, allowing automated testing and analysis of ESD robustness for different failure modes like trace fusing or inter-trace breakdown. Example test setups and preliminary results are shown for single-trace and differential injection IV-TLP methods.
Lightning and Surge Protection Strategy for InstrumentationRekaNext Capital
When Sensors are deployed outdoor, they need to be protected from Lightning voltage Surges. These are basic simple devices used to protect expensive sensors as voltage surges can occur anytime. This increase longivity of sensors and instruments
The document discusses various types of electrical test equipment used to test circuits and electrical components. It describes multimeters, megohmmeters, low-resistance ohmmeters, hipotential test sets, high current test sets, secondary test sets, relay test sets, power factor test sets, winding resistance test sets, current transformer test sets, ground resistance test sets, and power recorders. The document provides details on what each type of test equipment is used for and how measurements are made.
2012 Protection strategy for EOS (IEC 61000-4-5)Sofics
2012 Taiwan ESD and reliability conference
The standard IEC 61000-4-5 is used to characterize IC designs for EOS robustness. Each chip should achieve a minimum level of protection to withstand against EOS. Based on Long TLP and simulation, a strategy is developed to handle this requirement. The methodology has been applied for a T-con product in 130nm CMOS.
The document discusses electromagnetic compatibility (EMC) immunity testing standards. It focuses on electrostatic discharge (ESD), electrical fast transients (EFT), surge, radiated immunity, and conducted immunity tests. For each test, it describes the purpose, needed equipment, test setup, procedures, performance criteria, standards, and other test considerations. The performance criteria classify immunity test results into four categories based on the equipment's performance.
TN013 ESD Failure Analysis of PV Module Diodes and TLP Test MethodWei Huang
Bypass diodes inserted across the strings of the solar panel arrays are essential to ensure the efficiency of the solar power system. However, those diodes are found to be susceptible to potential Electrostatic Discharge (ESD) events in the process of solar Photovoltaic (PV) panel manufacture, transportation and on-site installation. Please refer [1], where an International PV Module Quality Assurance Forum has been setup to investigate PV Module reliability, and Task Force 4 has been setting guidelines for testing the ESD robustness of diodes used to enhance PV panel performance. This document explains the theory behind the ESD damage and the proper test and analysis methods for ESD failure of diodes. To demonstrate the proposed testing methodology that follows, we will be evaluating six different types of diode models as supplied by our customer, who manufactures solar panel arrays.
This document provides an overview of surge protection and power quality. It discusses how voltage surges can damage electronic equipment and outlines the basics of AC power and types of voltage disturbances. The progression of increasingly sensitive electronic devices is described. Common surge protection devices are explained, particularly metal oxide varistors, how they work to suppress voltage surges, and their failure modes from high energy or repetitive overvoltages. The goal is to describe surge risks and various protection technologies.
LVDT stands for Linear Variable Differential Transformer. It is an electromechanical transducer that converts linear motion to an electrical signal. LVDTs have advantages like friction-free operation, infinite resolution, and single axis sensitivity. They are used in applications like automation machinery, civil engineering, manufacturing, and testing. LVDTs work using electromagnetic induction - a ferrous core inside alters the magnetic flux in two coils, producing an output voltage proportional to displacement. Common manufacturers include RDP, Macro Sensors, and Honeywell, with LVDTs typically costing a few hundred dollars.
Industrial Surge Protection: Why Use Mersen Surge Protection Devices?AutomationDirect.com
In this Slideshare you may gain a better understanding of what a power surge is, what may cause a power surge, and why using Mersen surge protection devices to protect your equipment is an easy and cost-effective solution that will save you money and downtime.
DC Electrical Safety Standards presentationakhilesh682519
This document discusses electrical safety hazards from direct current (DC) systems. It begins by stating the objectives of recognizing and classifying DC electrical hazards, presenting current and evolving safety standards, and proposing a hazard classification approach for all arc flash hazards. It then provides an overview of current safety standards which have historically only covered 60 Hz alternating current hazards. The document discusses how DC systems are used in research and development and describes some effects of different current waveforms. It presents examples of energies involved in arc flashes from different voltage facility systems. The document proposes a classification system for different electrical hazards and reviews shock and arc flash thresholds. It discusses the evolution of national electrical safety standards and calls for a complete approach to classifying all types of arc hazards
This document provides an overview of surge protection and transient surges. It defines a transient surge as a brief high-voltage spike lasting millionths of a second. The document discusses how surges can damage equipment and cost businesses billions annually. It describes how surge protective devices (SPDs) work by diverting damaging currents away from equipment. The document emphasizes that proper SPD location and installation is important for effective protection. It provides guidance on selecting appropriate protection levels based on surge risk and discusses relevant industry codes and standards.
The document discusses the importance of protecting critical electrical equipment from transient voltage surges and temporary overvoltages (TOVs). It recommends using a hybrid surge protection device (SPD) that combines metal oxide varistors (MOVs) and selenium cells to effectively clamp voltages and survive TOVs, where an MOV-only SPD would fail. A hybrid SPD provides a "best in class" solution that can protect itself and downstream equipment from damaging voltage events.
1. The document describes an Ethernet Cable Discharge Event (CDE) test and measurement system.
2. The system aims to simulate and analyze ESD events from charged Ethernet cables. It includes modules to charge different cable types and arrangements and control the discharge sequence.
3. Key features allow testing of various cable setups, controlling the status of each wire, monitoring discharge waveforms, and remote control integration. Calibration components and procedures are also described.
How to protect electronic systems against esdMohamed Saadna
Electronic systems are subjected to electrostatic discharges (ESD). PCB designers must ensure their PCB is ESD-proof by adding TVS close to the connectors exposed to ESD. This presentation is an introduction on why and how to protect electronic systems. Advanced informations on IEC61000-4-2 and ISO10605 standards are also mentioned. Finally application examples from STMicroelectronics boards are shown as examples with ESD product recommendation for interfaces commonly used around MCUs like USB, RS-232, RS-485, USB-C, microphone, speakers, SWD, JTAG, memory card, ethernet, MIPI, Display port, HDMI, PLC inputs, CAN bus, KNX, DC barrel, SIM cards, etc.
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Introduction of Transmission Line Pulse (TLP) Testing for ESD Analysis - Device Level
1. Version 2015.04.17
Wei Huang, Jerry Tichenor
Web: www.esdemc.com Email: info@esdemc.com Tel: (+1) 573-202-6411 Fax: (+1) 877-641-9358
Address: 4000 Enterprise Drive, Suite 103, Rolla, MO, 65401
Introduction of
Transmission Line Pulse (TLP) Testing
for ESD Analysis
- Device Level
2. AGENDA
What is ESD?
Why do we care about ESD?
How can we protect against ESD?
How do we test for ESD robustness?
What is TLP testing?
ESD robustness tests vs. TLP testing (Pulse Shape Parameters)
Benefits of TLP testing vs. other ESD tests
Testing Procedure
Purchasing Considerations
TLP Standard Requirements
TLP Systems Comparison
TLP FAQ
References
2
3. WHATISESD?
What is ESD ?
• Electrostatic Discharge (ESD) is an exchange of charge between two objects, It
occurs when contact is established or if the dielectric breakdown of the material
between the two objects is exceeded
3
Note: The voltages are relatively high, some of them may occur under some extreme cases.
4. WHYDOWECAREABOUTESD?
Why do we care about ESD?
• Potential damage to circuit designs, leading to:
• Poor product quality
• Angry customers
• Increased costs for repair and rework
• Components permanent damage by breakdown, or oxide punch through,
excessive local heating as components may not be able to dissipate the energy
fast enough
4
Source: 2005 ESD/EOS
Symposium paper
8. HOWCANWEPROTECTAGAINSTESD?
How can we protect against ESD?
1. Controlled Environment 1
• Reduce the potential for charge build up
• Grounded equipment and furniture
• Clean Room - Controlled humidity and particles
• Does not help when system is shipped to End-User, such as Consumer Electronics.
Picture 8 ESD Friendly Workspace
8
9. HOWCANWEPROTECTAGAINSTESD?CONT’D
How can we protect against ESD? Cont’d
2. Improve System ESD Robustness
• Understand system working environment and potential ESD risks
• Design your system with careful ESD protection strategy !
(Please refer to System Level ESD - White Paper 1,2,3 - Industry Council on ESD Target Levels,
http://esda.org/IndustryCouncil.html)
• Understand ESD sensitivities of critical components
• Test and choose best ESD protection solutions for weakness
• Test and further improve system level ESD robustness
Design engineers need critical data from different types of ESD tests.
TLP test is a very powerful tool that provides many important data for ESD design !
Graph 1 Graph 2 9
10. HOWDOWETESTFORESDROBUSTNESS?
How do we test for ESD robustness?
• Human Body Model (HBM) 2
• Charged human body contact with device under test (DUT)
• ANSI/ANSI/ESDA/JEDEC JS-001-2010
• Test to 4000V, < 3A into a short (8000V optional)
• Discharge from the skin (IEC 61000-4-2 is a discharge from a metal part)
10
Rise Time (tr) for short – 2 to 10ns Decay Time (td) for short – 130 to 170ns
Picture 9
11. HOWDOWETESTFORESDROBUSTNESS?CONT’D
How do we test for ESD robustness? Cont’d
• Machine Model (MM) 3 (MM model is used very little)
• Charged machine discharge to devices, such as during production
• ESD STM5.2-2012
• Test to 400V
• < 7A into a short
11
Major Pulse Period (tpm) for short – 66 to 90ns
Graph 3
12. HOWDOWETESTFORESDROBUSTNESS?CONT’D
How do we test for ESD robustness? Cont’d
• Charged Device Model (CDM) 4
• Charged device discharge to other metal parts or ground plane, such as an integrated
circuit during assembly
• ESD S5.3.1-2009
• Device is charged via a charging plate
• Non-contact discharge as grounded object approaches a charged pin
• Test to 2000V
• 30A (4pF verification module, 260ps rise time)
12
Rise Time (tr) – ~200ps, Full Width Half Height (td) - ~400ps
Graph 4
CDM Test Setup
13. HOWDOWETESTFORESDROBUSTNESS?CONT’D
How do we test for ESD robustness? Cont’d
• IEC 61000-4-2:2008 5
• Charged human body contacting a DUT with a metal, discharging to a system
• System level test
13Ideal contact discharge waveform (4kV)
Contact discharge current waveform parameters
IEC Test Configuration
EUT
14. HOWDOWETESTFORESDROBUSTNESS?CONT’D
How do we test for ESD robustness? Cont’d
• Human Metal Model (HMM) 6
• Charged human discharging through a metal tool
• ANSI/ESD SP5.6-2009
• Component level test similar to IEC 61000-4-2
• Current waveform parameters same as IEC 61000-4-2
• Can use TLP and the 50W arrangement for more reliable and automatic failure
detection testing
14
50W Coaxial Source Setup
Setup A Setup B
15. WHATISTLPTESTING?
What is TLP Measurement ?
• Transmission-Line Pulse (TLP) Measurement is a methodology to test and study
integrated circuit technologies and circuit behavior in the time domain of
transient events, such as Electrostatic-Discharge (ESD), Cable Discharge Event
(CDE) .
• History:
• Due to interest in Electromagnetic Pulse environments, Wunsch and Bell
studied pulsed power failures in semiconductor junctions in the 1960’s. 7
• Also developed in the 1960’s, by Bradley, Higgins et.al., was the use of
charged transmission lines to generate rectangular pulses 8
• In the 1980’s the idea of using Transmission Line Pulsing for modeling of ESD
phenomena was introduced by Maloney and Khurana 9
• The first commercial TLP system was introduced by Barth Electronics in the
mid-1990’s 10
15
16. TLPSTANDARDREQUIREMENTS
What is TLP Testing?
TLP Standard Requirements
• Standard TLP (STM5.5.1-2014)
• Typically 0.2 to 10 ns rise time
• 10ns to > ms pulse width (100ns typical)
• Minimum of 200MHz BW oscilloscope
• Minimum of 200MHz BW voltage probe
• Minimum of 200MHz BW current probe
• Very Fast TLP (SP5.5.2-2007)
• Typically <= 200 ps rise time
• 1 to 10ns pulse width
• Minimum of 2.5GHz BW oscilloscope with 5GSa/s sampling
• Minimum of 1GHz BW voltage probe
• Minimum of 2GHz BW current probe
16
17. WHATISTLPTESTING?CONT’D
What is TLP Testing? Cont’d
• A basic pulse generator consists of a charge line (TL1) of length L, a switch (S1), and a High
Voltage power supply (Vo)
• The length of the charge line determines the pulse width
• Standard TLP typically uses 100ns pulse width, and a 1ns rise time
• Pulses are incrementally increased until
failure, or the maximum voltage is reached
• Failure typically determined by DC leakage
current measurement
• Measurement window is typically between
the 70 to 90% region to obtain a point of
the I-V curve
17
t
I(t)
t
V(t)
IDUT
VDUT
I
V
I
V
Measurement Window
Graph 5
18. WHATISTLPTESTING?CONT’D
What is TLP Testing? Cont’d
• I-V Characterization of TVS diode (70% to 90% window) measurement
18
Measurement Window (70 to 90% of Pulse)
19. WHATISTLPTESTING?CONT’D
What is TLP Testing? Cont’d
• I-V Characterization of TVS diode (70% to 90% window) measurement
• 100ns Pulse
19
Semtech uClamp0541Z Datasheet ESDEMC TLP Measurement
20. WHATISTLPTESTING?CONT’D
What is TLP Testing? Cont’d
• VF-TLP Measurement: turn on behavior of a TVS diode (first few nano-seconds of pulse)
20
RDUT vs. Time vs. Pulse Voltage Waterfall
6 V
TLP Pulse
Upper RDUT value limited
for plotting purposes
21. WHATISTLPTESTING?CONT’D
Typical Standard TLP Applications
1. Use TLP to obtain pulsed I-V curve, e.g. Get Protection Device Dynamic Resistance
(Dynamic Resistance is defined as dV/dI of the I-V curve)
Dynamic resistance is a very important specification for ESD protection device.
The lower the Rdyn, the more ESD current flows through the protection device and less
current flows through protected device.
• Transient Voltage Suppressor – 100’s of milli W’s to W’s
• Multi-Layer Varistor – W’s or more for low capacitance devices
21
Rdyn = (Vt2 – Vt1)/(It2 – It1)
0
5
10
15
20
25
0 5 10 15 20 25
TLP Voltage (V)
TLPCurrent(A)
RDYN = dV/dI =
Vt2 - Vt1 / It2 - It1
22. WHATISTLPTESTING?CONT’D
Typical Standard TLP Applications
2. Use TLP and auto failure check setup to test device ESD robustness / sensitivity
ESD Robustness of System / IC / Module are often evaluated with different ESD test setups. Some failure
types due to transient high energy damage can be simulated with controlled rise-time / pulse-width
rectangle TLP pulses or RC circuit discharging into matched 50 Ohm system waveform. TLP test results has
been used to estimate HBM, IEC 61000-4-2, HMM failure level. n
Eg, ESD thermal failure correlations*(Note): TVS IEC 1 kV level = 2 A , 100 ns TLP pulse level
IC HBM 1 kV level = 1.5 A, 100 ns TLP pulse level
Please refer to publications for to TLP test correlations usage, different device has different sensitivities !
Correlation between transmission-line-pulsing I-V curve and human-body-model, Jon Barth, John Richner
ESD Relations between system level ESD and (vf-)TLP, T. Smedes, J. van Zwol, G. de Raad, T. Brodbeck, H. Wolf
A TLP-based Human Metal Model ESD-Generator for Device Qualification according to IEC 61000-4-2
Yiqun Cao 1, David Johnsson 1, Bastian Arndt 2 and Matthias Stecher
Pitfalls when correlating TLP, HBM and MM testing, Guido Notermans, Peter de Jong and Fred Kuper
A Failure Levels Study of Non-Snapback ESD Devices for Automotive Applications, Yiqun Cao , Ulrich Glaser ,
Stephan Frei and Matthias Stecher
Correlation Between TLP, HMM, and System-Level ESD Pulses for Cu Metallization, Y. Xi, S. Malobabic, V.
Vashchenko, and J. Liou
Capacitive Coupled TLP (CC-TLP) and the Correlation with the CDM, Heinrich Wolf, Horst Gieser, Karlheinz Bock ,
Agha Jahanzeb, Charvaka Duvvury, Yen-Yi Lin
….. (please check for your device and applications)
Note: 1. Standard TLP doesn’t give first peak kind of pulse as IEC61000-4-2, so device failures during first peak can not
repeat TLP tests. VF-TLP can provide fast rise-time and short pulse to approach the event.
2. Standard TLP are based on 50 Ohm impedance, while other ESD model are based on different impedance
system so the voltage applied before device fully turn-on could be very different and cause different failure types.
22
23. Snapback Measurement of N-channel MOSFET
100ns TLP with <=200ps rise time, Overlap TDR measurement method was used
The snapback is due to Rdut has changed during the 100 ns pulse stressing
Typical TLP Applications
3. Test device TLP I-V curve to determine Safe Operation Area of Device
Snapback
24. Electrical Safe Operating Area of N-ch MOSFET
Safe operating area (SOA) is an important electrical property to understand the
ESD/EOS transient limitation of a component.
25. WHATISTLPTESTING?CONT’D
Typical Standard TLP Applications
4. Characterize device turn-on/off transient characteristic (the 3D waterfall plots)
e.g. ESD protection device react speed
5. Characterize device Charge recovery effects
e.g. reverse and forward recovery of diodes
6. Characterize device linearity under pulsed transient
e.g. capacitance changes over high voltage
7. Characterize device break down effects
e.g. Touch panel sensor traces sparking / fuse effect during ESD
8. Characterize saturation effects on common mode chokes and Ethernet magnetics
9. Measure the non linearity of capacitance of Multi-Layer capacitors
....
• Note, there are more system level applications of TLP will be covered in another PPT release in 2015 Q2,
please contact us if you needed it.
25
26. WHATISTLPTESTING?CONT’D
What is TLP Testing? Cont’d
• Very Fast TLP (VF-TLP)
• Commonly used for characterizing device Clamping Speed and Gate Oxide Punch Thru
• Pulse widths are very narrow (< 10ns)
• Rise times are at least 15% of Pulse Widths (100 ps to 500ps) at least? Or less than?
• A VF-TLP measurement setup (typically a low loss delay line with wide-bandwidth
voltage pick-up T, or a wide-bandwidth directional coupler or a pair of wide-
bandwidth direct I and V probes very closely positioned DUT, etc… ) is build so that the
incident and reflected pulses can be measured separately and precisely
• De-embedding of the cable loss is necessary and performed using frequency domain
techniques
26
Graph 6
A Typical VF-TLP Measurement Setup with Delay Line
27. ESDEMCTECHNOLOGYLLC
Ultra Fast VF-TLP Pulse
ESDEMC ES621 VF-TLP Waveform with 60 ps rise-time, 1ns pulse width
Measured with 18GHz Cable/ATT + 23 GHz/100Gs Scope Tek MSO 72304DX
28. • Use TLP to Check ESD Protection Circuit Peak Pass Through Voltage and
Clamping Voltage
• Peak voltage is the initial response to the pulse edge rate
• Clamping voltage is the output voltage when protection device fully turns
on and clamps
• Some sensitive device are sensitive to short time peak voltage (high E-field
strength), therefore both parameters are important to understand the
device sensitivity and design best ESD protection solution.
Peak
Clamping
What is TLP Testing? Cont’d
29. ESDROBUSTNESSTESTSVS.TLPTESTING
ESD Robustness Tests vs. TLP Testing (Pulse Shape Parameters)
29
HBM MM IEC (2nd Peak) IEC (1st Peak) CDM
Typical max
Peak V*
4000V 400V 8kV (contact) 2000V
Typical max
Peak I*
< 3A (short) < 7A (short) 16A (@30ns) 30A 30A
Rise Time* 2 – 10ns ~ns – 10ns ~ns 800ps < 200ps
Pulse Width* 130 – 170ns 66 – 90ns ~100ns ~5ns < 400ps
Pulse shape
compatible
with
Standard TLP Standard TLP Standard TLP VF-TLP VF-TLP
Typical
Failure
Modes
Junction
damage, metal
penetration,
melting of
metal layers,
contact spiking,
gate-oxide
damage 11
Junction
damage,
melting, gate-
oxide damage
11
Melting failure
Oxide punch
through
Gate-oxide
damage, charge
trapping,
junction
damage 11
* Typical values noted in each respective standard.
30. BENEFITSOFTLPTESTINGVS.OTHERESDTESTS
Benefits of TLP testing vs. other ESD tests
• Well Defined Consistent Waveform Shape
• Both circuit and waveform defined in ESD simulator standards are too
flexible (no impedance control for test path, 30% tolerance at only certain
time …) This cause ESD simulators to provide very different ESD test results
between different test sites. TLP pulse is very clean and consistent.
• Highly Repeatable Test Setup
• Fatigue from holding ESD simulator with hand leads to inconsistency setup,
vs TLP test with Jigs for mounting components give a more controlled test.
• Fast Automatic Test, Measurement and Report !
• Usually TLP test is done with full automation control of Pulsing, DC Leakage,
I-V Curve real-time update and automatic failure detection
• Important Device Behavior is recorded for ESD analysis and design !
• Many useful parameters can be extracted from TLP tests for device transient
behavior analysis, modeling and System-Efficient ESD Design (SEED).
However traditional ESD tests only generate pulse for P/F results.
30
31. TESTINGPROCEDURE
General Testing Procedure
• SOZL (Short – Open – Zener – Load) Calibration (only if change setup)
• Short and Open measurements provide Series and Shunt resistances,
respectively
• Zener and Load measurements provide Voltage and Current correction
factors, respectively
• This calibration should be performed every few months or if equipment is
changed
• Test standard for comparison
• Measure a well known device for comparison
• Reporting
• Pulse width
• Rise time
• Failure type, and level (DC Leakage, Fusing, Snapback)
• Pulse Level, DUT Voltage, and DUT Current at failure
• Dynamic Resistance if applicable
• Snapback (eSOA)
31
32. PURCHASINGCONSIDERATIONS
TLP System Configuration Considerations
• What applications you want to test with TLP ?
• Evaluate ESD protection devices performance (Compare Rdyn and Clamping speed)
• Evaluate ESD failure level of device and module
• Different pulse shape (TLP, HMM, HBM etc…) or pulse-width, rise-time might
needed, and wide range of current injection level (40A, 90A, 160A etc…)
• Evaluate Safe Operation Area
• A wide range of different pulse-width selection and injection level is needed.
• Touch panels breakdown and fuse sensitivity
• Differential Pulse injection and measurement
• What equipment will you need to configure ?
• Pulse generator – TLP / VF-TLP / HMM / HBM etc…
• Device probing method ? – PCB with SMA connector, IC test jig, probe station
• Single-end or differential Injection ? --- HV wideband splitter & Inverter
• Current and Voltage measurement method – direct probes
• Transient data capture – Oscilloscope (bandwidth depends on application)
• Bias and DC measurement -- SMU / Power Source / Picoammeter
32
33. TLPSYSTEMSCOMPARISON
TLP Systems Specification on Market
• Standard TLP System
• Recommend spec: 2 kV open voltage / 40A short current
• ESDEMC Standard TLP Solution currently provides up to 7kV / 140A, the highest
pulse injection and IV measurement specification in the world )
• Nearest competitors: 4kV / 80A, Others 2kV / 40A
• VF-TLP System
• Recommend spec: Injection level up to 1kV / 20A, with clean, fast and stable rise-time
(<=100 ps), very wide analogue measurement bandwidth (2.5 ~ 4 GHz) and advanced
digital frequency compensation
• ESDEMC VF-TLP Solution currently provides
TLP Pulse up to 1kV / 20A with 60 ps rise-time and up to 5 kV / 100 A with
200 ps rise-time
Measurement with up to 6 GHz analogue bandwidth measurement
capability plus all port frequency compensation algorithm using Network
Analyzer S-parameters
33
34. ESDEMCTECHNOLOGYLLC
World’s Top Specification TLP Dynamic IV-Curve Solution
2011 Beginner in IV-TLP Solutions
2013 Matching Top Spec System
2014 One of the best IV-TLP System
Specifications/Functions ESDEMC ES620/ES621 Other Brand Systems
Fastest Rise-time About 60 ps (World’s fastest) 100 ps, 200 ps
Longest Pulse-width 2000 us (1ms under development) 1600 us, 400 ns
Maximum Current Injection Level 160 A 80 A, 40A, 30A…
Standard 2D IV Curve Analysis Yes Yes
Advanced 3D IVT Curve Analysis Yes, currently unique No, need additional work
Voltage Measurement Methods Resistive Direct, Overlap TDR,
Non Overlap TDR,
Usually only 1 or 2 types
Current Measurement Methods Resistive Direct, Resistive Equation, Inductive
Direct, Overlap TDR, Non Overlap TDR
Usually only 1 or 2 types
Error Correction Methods SOLZ Correction, All ports S-parameters
compensation, Trigger timing alignment
SOLZ Correction
Differential TLP Pulsing and IV Test Yes, unique No
35. TLPSYSTEMSCOMPARISON
General FAQ for TLP testing ?
• How much does TLP system cost ?
• Most TLP system in the market current cost about 80 ~ 250 K USD
• ESDEMC provides ES620 Ultra-portable and low cost version system cost
about 40 – 100K from 2015 Q2 (only 1/2 of same specification system
from other vendors)
• ESDEMC guarantee to provide better capability TLP system at same cost
of other competitors
• Can customer use their equipment for TLP system configuration ?
• Most TLP system in the market doesn’t support wide range of instruments,
but ESDEMC TLP software designed with great compatibility in mind, you can
choose most equivalent instruments you had (Agilent, Tek, Lecroy, Rigol,
Keithley, etc…). You change instrument settings in few clicks or contact us if
you need support !
35
36. TLPSYSTEMSCOMPARISON
General FAQ for TLP testing ?
• What bandwidth is really needed for TLP testing ?
• This really depends on the IV measurement window you want to measure,
for most applications with standard 100 ns TLP, 200+ MHz bandwidth is fine
if you only check the 70-90% of 100 ns pulse window for Rdyn and pulse
failure level, even ESDA TLP standard require higher bandwidth.
• However if customer want to measure the device characteristic from the first
ns of the pulse injection, VF-TLP generator with very clean and stable edge
and 4~ 8 GHz oscilloscope is recommended.
36
37. TLPSYSTEMSCOMPARISON
Thank you !
• Please feel free to contact info@esdemc.com for questions about general ESD
test and applications, we are expert in this field and we like to help !
• We will keep updating this ppt and we offer FREE application consulting. We
also send out latest technical notes and sales promotion each quarter, please
email us if you like to subscribe.
• If you are interested, below are few slides about ESDEMC Technology LLC
37
38. A Start-up Business Specializing in the Development of ESD/EMC Solutions
and Customized HV/RF Designs from 2011, Located in Rolla, MO, USA.
ES/ESD
Solution
EMC Test
Solution
HV System
Design
RF System
Design
To be one of the best Commercial Solution Providers in the field,
by ESD/EMC Engineers, for ESD/EMC Engineers
39. ESDEMCTECHNOLOGYLLC
Development Achievements (2011.03 to present)
ESD/Transient
• World’s top spec Transmission Line Pulse System (TLP/VFTLP)
• World’s first Commercial Cable Discharge Event (CDE) System
• ESD Simulator, ESD Targets, Adapter Line
• Plus additional features…
EMC/ RF
• Microwave Material Characterization System (5-22 GHz)
• IC Strip TEM Cell (4kV/ DC-5.5 GHz)
• Wideband RF Amplifiers (Up to 40 GHz)
• Wideband Power Amplifier (4GHz/25W )
• Plus additional features…
Other Key Products
• Wideband HV Pulse Attenuator (Symmetric, 4kV / 3.5GHz)
• Oscilloscope ESD Protector (up to 6 GHz)
• HV Pulse Differential Splitter (1MHz to 2GHz)
• See website ESDEMC.COM for more products
41. Company Growth (2011 to 2013)
ESDEMCTECHNOLOGYLLC
Niche: Solutions by ESD/EMC experts, innovative & flexible, focused
on ESD/EMC design, analysis and debugging
Growth: 2010.09 Business setup in Founder’s home
2011.03 to now Group of 5 professionals
ESDEMC is strategically located in the same facility with the world’s largest
academia EMC research group MS&T-EMCLAB
About 40% each year
42. ESDEMC Group @ 2012 IEEE EMC Symposium
Oh, I have a
new idea ...
We are
growing … I can do
it …
We can
improvise…
Fredric Stevenson
Business/Technical
Development
Wei Huang
Founder/Owner
Chief Design Engineer
David Pommerenke
Chief Technology
Consultant
Jerry Tichenor
Design Application
Engineer
43. REFERENCES
References
1. Martin Rodgaard, 2007, ESD – Electrostatic Discharge, Retrieved Jan 13, 2015 from:
http://hibp.ecse.rpi.edu/~connor/education/Surge/Presentations/ESD_mr.pdf
2. ESDA/JEDEC Joint Standard for Electrostatic Discharge Sensitivity Testing - Human Body Model (HBM) – Component Level,
ANSI/ANSI/ESDA/JEDEC JS-001-2010, April 2010.
3. ESD Association Standard Test Method for Electrostatic Discharge Sensitivity Testing - Machine Model – Component Level, ESD
STM5.2-2012, July 2013.
4. ESD Association Standard for Electrostatic Discharge Sensitivity Testing - Charge Device Model (CDM) – Component Level, ESD S5.3.1-
2009, December 2009.
5. International Electrotechnical Commission, Electromagnetic Compatibility (EMC) – Part 4-2: Testing and measurement techniques –
Electrostatic discharge immunity test, IEC 61000-4-2:2008, 2008.
6. ESD Association Standard Practice for Electrostatic Discharge Sensitivity Testing - Human Metal Model (HMM) – Component Level,
ANSI/ESD SP5.6-2009, September 2009.
7. D.C. Wunsch and R.R. Bell, “Determination of Threshold Failure Levels of Semiconductor Diodes and Transistors due to Pulse
Voltages,” IEEE Trans. Nuc. Sci., NS-15, pp. 244-259, 1968.
8. D.J. Bradley, J.F. Higgins, M.H. Key and S. Majumdar, “A Simple Laser-triggered Spark Gap for Kilovolt Pulses of Accurately Variable
Timing,” Opto-Electronics Letters, vol. 1, pp. 62-64, 1969.
9. T.J. Maloney and N. Khurana, “Transmission Line Pulsing Techniques for Circuit Modeling of ESD Phenomena,” 1985 EOS/ESD
Symposium Conference Proceedings, pp. 49 -54, 1985.
10. W. Simburger, “AN 210 Effective ESD Protection Design at System Level Using VF-TLP Characterization Methodology,” Infineon
Application Note 210, Revision 1.3, December 2012.
11. D. Byrd, T. Kugelstadt, 2011, Understanding and Comparing the Differences in ESD Testing, Retrieved Jan 14 2015 from:
http://www.edn.com/design/test-and-measurement/4368466/Understanding-and-comparing-the-differences-in-ESD-testing
43
44. REFERENCESCONT’D
References Cont’d
Graph 1 & 2: (n.a.), 2013, How to Select Transient Voltage Suppressors (TVS Diode)?, Retrieved Jan 13 2015 from:
http://www.completepowerelectronics.com/tvs-diode-selection-tutorial/
Graph 3 & 4: D. Byrd, T. Kugelstadt, 2011, Understanding and Comparing the Differences in ESD Testing, Retrieved Jan 14 2015 from:
http://www.edn.com/design/test-and-measurement/4368466/Understanding-and-comparing-the-differences-in-ESD-testing
Graph 5 & 6: Reference 10
Picture 1: Eric Puszczewicz, 2011, Electrostatic Discharge - ESD Basics and Protection, Retrieved Jan 13 2015 from:
http://www.slideshare.net/ericpuszczewicz/esd-basics-by-transforming-technologies
Picture 2: Ron Kurtus, 2015, Static Electricity Sparks, Retrieved Jan 13 2015 from: http://www.school-for-
champions.com/science/static_sparks.htm#.VLU51yvF9MY
Picture 3: K. Vermeer, 2011, Static dissipative ESD footware, Retrieved Jan 15 2015 from:
http://electronics.stackexchange.com/questions/23107/static-dissipative-esd-footware
Picture 4: (n.a.), (n.d.), Anti-Static Design – ESD Protection, Retrieved Jan 15 2015 from:
http://www.ecs.com.tw/ECSWebSite/Product/Product_Detail.aspx?DetailID=1446&MenuID=17&LanID=0
Picture 5: (n.a), 2000, Maxim Leads the Way in ESD Protection, Retrieved Jan 15 2015 from: http://www.maximintegrated.com/en/app-
notes/index.mvp/id/639
Picture 6: T. G. Nagy, (n.d.), Effective ESD Transient Voltage Surge Suppression in New, High Speed Circuits, Retrieved Jan 15 2015 from:
http://www.compliance-club.com/archive/old_archive/020930.htm
Picture 7: P. Yu, 2010, Component Failure Analysis – Hermetic Packaging, Retrieved Jan 15 2015 from:
http://www.empf.org/empfasis/2010/Apr10/help-410.html
Picture 8: P. Corr, 2014, Laser Diodes: Laser diode operation 101: A user’s guide, Retrieved Jan 15 2015 from:
http://www.laserfocusworld.com/articles/print/volume-50/issue-03/features/laser-diodes-laser-diode-operation-101-a-user-s-
guide.html
Picture 9: S. Pefhany, 2014, FET Electrostatic Damage, Retrieved Jan 15 2015 from:
http://electronics.stackexchange.com/questions/97605/fet-electrostatic-damage
44
Editor's Notes
GOAL: To introduce what ESD.
David:
This numbers have never been verified. They are used by many people.
We tried a lot of times to identify the source, but it was not possible.
I suggset not to use it. The voltages are too high, some of them may occur under some
Extreme cases. Atieh can give you data and the references of the publications.
We do not have carpet walking data, but we have other good data.
GOAL: Consumer Electronics can suffer damage, leading to poor reputation for a company that manufactures Consumer Electronics.
GOAL: Consumer Electronics can suffer damage, leading to poor reputation for a company that manufactures Consumer Electronics.
GOAL: Consumer Electronics can suffer damage, leading to poor reputation for a company that manufactures Consumer Electronics.
GOAL: Consumer Electronics can suffer damage, leading to poor reputation for a company that manufactures Consumer Electronics.
GOAL: Manufacturers can help protect their environment with an ESD Friendly Workspace, but that does not help Consumer Electronics. Protection devices/circuits can!
TVS Diodes turn ON during the pulse voltage. Once ON they are effectively a resistor that channels the transient current to ground. They also clamp the voltage.
GOAL: Manufacturers can help protect their environment with an ESD Friendly Workspace, but that does not help Consumer Electronics. Protection devices/circuits can!
TVS Diodes turn ON during the pulse voltage. Once ON they are effectively a resistor that channels the transient current to ground. They also clamp the voltage.
GOAL: Discuss Rise Time and Pulse Width and Max V & I – all according to the Standard listed.
GOAL: Discuss Rise Time and Pulse Width and Max V & I – all according to the Standard listed.
GOAL: Discuss Rise Time and Pulse Width and Max V & I – all according to the Standard listed.
GOAL: Discuss Rise Time and Pulse Width and Max V & I – all according to the Standard listed.
GOAL: Discuss Rise Time and Pulse Width and Max V & I – all according to the Standard listed.
ALSO INTRODUCE TLP
TLP with an HMM module can be used with 47ohm resistor to pulse a TVS diode. The TVS diode has an on-state resistance of a few ohms. This on-state value plus the 47ohms gives a termination of approximately 50ohms, and therefore minimal reflections.
GOAL: Introduce TLP. Can be a destructive test, but does not have to be. Typically used for characterizing protection devices.
GOAL: Minimum requirements.
GOAL: Introduce the basic structure, a charge line and a switch.
A typical test run consists of:
1) Setting the TLP Voltage, 2) Pulsing the DUT, 3) Capturing the measured I&V, 4) Calculating the average I&V over the 70 to 90% window of the measured I&V, 5) Measure DC Leakage and check if acceptable level, 6) Pass - Repeat by increasing TLP Voltage, Fail - Stop
The Pulse Voltage Slice demonstrates how the RDUT changes as the pulse propagates across the device
GOAL: Introduce the basic structure, a charge line and a switch.
A typical test run consists of:
1) Setting the TLP Voltage, 2) Pulsing the DUT, 3) Capturing the measured I&V, 4) Calculating the average I&V over the 70 to 90% window of the measured I&V, 5) Measure DC Leakage and check if acceptable level, 6) Pass - Repeat by increasing TLP Voltage, Fail - Stop
GOAL: Introduce the basic structure, a charge line and a switch.
A typical test run consists of:
1) Setting the TLP Voltage, 2) Pulsing the DUT, 3) Capturing the measured I&V, 4) Calculating the average I&V over the 70 to 90% window of the measured I&V, 5) Measure DC Leakage and check if acceptable level, 6) Pass - Repeat by increasing TLP Voltage, Fail - Stop
The Pulse Voltage Slice demonstrates how the RDUT changes as the pulse propagates across the device
GOAL: Introduce Dynamic Resistance. ESD protection devices channel transient current to ground. The devices Dynamic or On-State Resistance provides this path to ground. TVS are the most common protection device, and they are silicone based technology that utilize avalanche breakdown to protect circuits. MLVs are a ceramic technology and typically has a larger On-State Resistance and higher Leakage current. A high leakage current means faster battery drain in cell phones for example.
GOAL: Introduce Dynamic Resistance. ESD protection devices channel transient current to ground. The devices Dynamic or On-State Resistance provides this path to ground. TVS are the most common protection device, and they are silicone based technology that utilize avalanche breakdown to protect circuits. MLVs are a ceramic technology and typically has a larger On-State Resistance and higher Leakage current. A high leakage current means faster battery drain in cell phones for example.
Need to add what setup was used, simplified sch
NX3008NBKS 30V, 350mA dual N-channel Trench MOSFET
Need to add :
What is SOA
Why should we measure it ?
GOAL: Introduce Dynamic Resistance. ESD protection devices channel transient current to ground. The devices Dynamic or On-State Resistance provides this path to ground. TVS are the most common protection device, and they are silicone based technology that utilize avalanche breakdown to protect circuits. MLVs are a ceramic technology and typically has a larger On-State Resistance and higher Leakage current. A high leakage current means faster battery drain in cell phones for example.
GOAL: Briefly introduce VF-TLP. Difficult to go into detail as this is a more complicated measurement method. Use Transmission line theory to calculate VDUT and IDUT from the incident and reflected pulses. This is why the incident and reflected pulses must be separate, so that they can be mathematically manipulated in processing. S-parameters (S21) of the system are used and the calculations are done in the frequency domain with the final result transformed back to the time domain.
Our group consists of…
Leading this group is Dr. David Pommerenke who is development consultant
IEC Standard 61000-4-2: for ESD target, gun, table, etc.
iNARTE certified engineers
GOAL: To compare Rise Times of the different Standard Tests, To compare Pulse Widths of the different Standard Tests, To compare applied V&I of the different Standard Tests, and how these can all be Compatible with TLP. TLP systems can be designed with each of the different rise times and pulse widths to get similar pulse waveforms as each of the Standard Tests.
GOAL: List the Benefits of TLP vs. the Standard Tests.
I-V Curve trends: Snapback is a large decrease in voltage, Fuse is a large decrease in current
GOAL: Introduce what calibrations are performed, and what values are typically reported.
What do you want to test with TLP ? Special Requirements/Thoughts
Evaluate ESD Protection devices (TVS) Rdyn, Failure level to
ESD sensitive devices
Components expose to ESD How to connect (Pogo probes?)
Touch Panels Differential Probe
On-Wafer Pico probes, Probe Station
How do you want to test?
Characterize Transient IV Curve Probe style
Characterize eSOA Bias Supply
Test to Failure Leakage SMU
Clamping voltage speed Fast rise time
Device turn on behavior VF-TLP
What equipment do you already have?
Oscilloscope Enough BW
SMU
GOAL:
Our group consists of…
Leading this group is Dr. David Pommerenke who is development consultant
IEC Standard 61000-4-2: for ESD target, gun, table, etc.
iNARTE certified engineers
GOAL:
GOAL:
GOAL:
We are a group of …
A significant part of our operations is focused on design and testing
IN FOUR AREAS namely…
However, our current top solutions are focused in the area of
Operations divided into TWO main cats namely:
Design and consulting and product manufacturing
Again the areas of focus are…
Under ES/ESD testing, we tackle solutions related to …
Explosion proof: EXIAII CT6
For EMC/SI/PI testing, we use ESD and EMI Probing, PDN Noise Inj, Pulse Generation...
In HV/RF Testing, we develop modular and system type HV supplies, HV Apps, …
Operations divided into TWO main cats namely:
Design and consulting and product manufacturing
Again the areas of focus are…
Under ES/ESD testing, we tackle solutions related to …
Explosion proof: EXIAII CT6
For EMC/SI/PI testing, we use ESD and EMI Probing, PDN Noise Inj, Pulse Generation...
In HV/RF Testing, we develop modular and system type HV supplies, HV Apps, …
ESDEMC Tech is among the best in the industry because…