In this paper, design of two different arraymultipliers are presented, one by using conditional sum (COSA) logic for addition of partial product terms and another by introducing Carry Save Adder (CSA) in partial product lines. The multipliers presented in this paper were all modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. The comparison is done on the basis of three performanceparameters i.e. Area, Speed and Power consumption. To design an efficient integrated circuit in terms of area, power and speed, has become a challenging task in modern VLSI design field. Previously in the literature, performance analysis was carried out between multiplier using Ripple carry adder (RCA) and by using CLA. In this work, same multiplier is designed by using CSA logic and compare it's performance with the multiplier designed by using CSLA logic. Multiplier with CSA gives better result in terms of speed (78.3% improvement), area (reduced by 4.2%) and power consumption (decreased by 1.4%).
Adders are one of the most widely digital
components in the digital integrated circuit design and are the
necessary part of Digital Signal Processing (DSP) applications.
With the advances in technology, researchers have tried and are
trying to design adders which offer either high speed, low power
consumption, less area or the combination of them. The addition
of the two bits is very Based on the various speed-up schemes for
binary addition, a comprehensive overview and a qualitative
evaluation of the different existing basic adder architectures are
given in this paper. In addition, their comparison is performed in
the thesis for the performance analysis. We will synthesize the
adders - Ripple Carry adder, Carry look- ahead Adder, Carry
Save Adder in ISE XIILINX 10.1 by using HDL - Verilog and
will simulate them in Modelsim 6.4a. We will Compare above
mentioned adders in terms of Delay, Slices Used and Look up
tables used by the adder architecture.
In this project 31 % area delay product reduction is possible with the use of the CSLA based 32 bit unsigned parallel multiplier than CLAA based 32 bit unsigned parallel multiplier
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Adders are one of the most widely digital
components in the digital integrated circuit design and are the
necessary part of Digital Signal Processing (DSP) applications.
With the advances in technology, researchers have tried and are
trying to design adders which offer either high speed, low power
consumption, less area or the combination of them. The addition
of the two bits is very Based on the various speed-up schemes for
binary addition, a comprehensive overview and a qualitative
evaluation of the different existing basic adder architectures are
given in this paper. In addition, their comparison is performed in
the thesis for the performance analysis. We will synthesize the
adders - Ripple Carry adder, Carry look- ahead Adder, Carry
Save Adder in ISE XIILINX 10.1 by using HDL - Verilog and
will simulate them in Modelsim 6.4a. We will Compare above
mentioned adders in terms of Delay, Slices Used and Look up
tables used by the adder architecture.
In this project 31 % area delay product reduction is possible with the use of the CSLA based 32 bit unsigned parallel multiplier than CLAA based 32 bit unsigned parallel multiplier
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...IJERA Editor
The addition of two binary numbers is the important and most frequently used arithmetic process on
microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits
(ASIC). Therefore, binary adders are critical structure blocks in very large-scale integrated (VLSI) circuits.
Their effective application is not trivial because a costly carry spread operation involving all operand bits has to
be achieved. Many different circuit constructions for binary addition have been planned over the last decades,
covering a wide range of presentation characteristics. In today era, reversibility has become essential part of
digital world to make digital circuits more efficient. In this paper, we have proposed a new method to reduce
quantum cost for ripple carry adder and carry skip adder. The results are simulated in Xilinx by using VHDL
language.
128-Bit Area Efficient Reconfigurable Carry Select Adder ijcisjournal
Adders are one of the most critical arithmetic circuits in a system and their throughput affects the overall
performance of the system. Carry Select Adder (CSLA) is one of the fastest adders used in many dataprocessing
processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that
there is scope for reducing the area and power consumption in the CSLA. In this paper, we proposed an
area-efficient carry select adder by sharing the common Boolean logic term. After logic optimization and
sharing partial circuit, we only need one XOR gate and one inverter gate for sum generation. Through the
multiplexer, we can select the final-sum only and for carry selection we need only one AND gate and one
OR gate. Based on this modification 16-, 32-, 64-, and 128-bit CSLA architecture have been developed and
compared with the conventional CSLA architecture. The proposed design greatly reduces the area
compared to other CSLAs. From this improvement, the gate count of a 128-bit carry select adder can be
reduced from 3320 to 1664. The proposed structure is implemented in Artix-7 FPGA. Compared with the
proposed design, the conventional CSLA has 65.80% less area.
Duet advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. Due to which high speed adder architecture become important. Sever a ladder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed modified carry select adder using boot hen coder (BEC) Technique. Booth encoder, Mathematics is an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family.
FPGA Implementation of High Speed Architecture of CSLA using D-LatchesEditor IJMTER
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing
processors to perform fast arithmetic functions. The CSLA is used in many systems to overcome the
problem of carry propagation delay by independently generating multiple carries and then select a
carry to generate the sum. But the CSLA is not area efficient because it uses multiple pairs of Ripple
Carry Adders (RCA). Due to the rapidly growing mobile industry not only the faster arithmetic unit
but also less area and low power arithmetic units are needed. The modified CSLA architecture has
developed using Binary to Excess-1 converter (BEC). This paper proposes an efficient method which
replaces the BEC using D latch. Designs were developed using structural VHDL and synthesized in
Xilinx 13.2 with reference to FPGA device XC3S500E.
Implementation of Low Power and Area-Efficient Carry Select AdderIJMTST Journal
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform
fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area
and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to
significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-,-b square-root
CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA
architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA
with only a slight increase in the delay. This work evaluates the performance of the proposed designs in
terms of delay, area, power, and their products by hand with logical effort and through custom design and
layout in 0.18-m CMOS process technology. The results analysis shows that the proposed CSLA structure is
better than the regular SQRT CSLA.
Design of 8-Bit Comparator Using 45nm CMOS TechnologyIJMER
In this paper design of 8- bit binary comparator using 45nm CMOS technology is discussed.
This design needs less area and less number of transistors, also discussed about power and execution time. The
circuit has three output X, Y and Z. X is active high, when A>B, Y is active high when A=B and Z is active high
when both X and Y are active low. Design 1- bit comparator with the help of precharge gate.The design of 1-bit
comparator has been extended to implement an 8-bit comparator by connecting in series with pass
transistor between them. The design has been implemented in Microwind3.1, is tested successfully and
has been validated using Pspice for different measurable parameter.
Design and Verification of Area Efficient Carry Select Adderijsrd.com
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 16, 32 square - root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Highly -increasing requirement for mobile and several electronic devices want the use of VLSI circuits which are highly power efficient. The most primitive arithmetic operation in processors is addition and the adder is the most highly used arithmetic component of the processor. Carry Select Adder (CSA) is one of the fastest adders and the structure of the CSA shows that there is a possibility for increasing its efficiency by reducing the power dissipation and area in the CSA. This research paper presents power and delay analysis of various adders and proposed a 32-bit CSA that is implemented using variable size of the combination of adders, thus the proposed Carry select Adder (CSA) which has minimum Delay, and less power consumption hence improving the efficiency and speed of the Carry Select Adder.
Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...IJTET Journal
Abstract: In VLSI Technology, Carry Propagation Delay is the most important concern for the Adders. Adder is the most unavoidable component for the arithmetic performances. This paper is Modified Square Root-Carry Select Adder (SQRT-CSLA) design reduces the delay with 16 bit adder. Carry select adder have two units for Carry Generation (CG) and Carry Selection (CS). The modified SQRT-CSLA design can gives parallel path for carry propagation. So the overall adder delay has reduced. Modified design is obtained using Ripple Carry Adder (RCA) with Boolean Excess-1 Converter (BEC). BEC produces an output i.e., is an excess one result for given input bits. Then input bits and BEC output is given to multiplexer for carry selection. Use of BEC instead of dual RCA gives efficient carry propagation delay and it consumes the lower power and overall gates using in design is reduced with compared to carry select adder with dual RCA. The final sum is calculated using final sum generation.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
VLSI Implementation of 32-Bit Unsigned Multiplier Using CSLA & CLAAIJMTST Journal
In this project we are going to compare the performance of different adders implemented to the multipliers based on area and time needed for calculation. The CLAA based multiplier uses the delay time of 99ns for performing multiplication operation where as in CSLA based multiplier also uses nearly the same delay time for multiplication operation. But the area needed for CLAA multiplier is reduced to 31 % by the CSLA based multiplier to complete the multiplication operation.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...IJERA Editor
The addition of two binary numbers is the important and most frequently used arithmetic process on
microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits
(ASIC). Therefore, binary adders are critical structure blocks in very large-scale integrated (VLSI) circuits.
Their effective application is not trivial because a costly carry spread operation involving all operand bits has to
be achieved. Many different circuit constructions for binary addition have been planned over the last decades,
covering a wide range of presentation characteristics. In today era, reversibility has become essential part of
digital world to make digital circuits more efficient. In this paper, we have proposed a new method to reduce
quantum cost for ripple carry adder and carry skip adder. The results are simulated in Xilinx by using VHDL
language.
128-Bit Area Efficient Reconfigurable Carry Select Adder ijcisjournal
Adders are one of the most critical arithmetic circuits in a system and their throughput affects the overall
performance of the system. Carry Select Adder (CSLA) is one of the fastest adders used in many dataprocessing
processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that
there is scope for reducing the area and power consumption in the CSLA. In this paper, we proposed an
area-efficient carry select adder by sharing the common Boolean logic term. After logic optimization and
sharing partial circuit, we only need one XOR gate and one inverter gate for sum generation. Through the
multiplexer, we can select the final-sum only and for carry selection we need only one AND gate and one
OR gate. Based on this modification 16-, 32-, 64-, and 128-bit CSLA architecture have been developed and
compared with the conventional CSLA architecture. The proposed design greatly reduces the area
compared to other CSLAs. From this improvement, the gate count of a 128-bit carry select adder can be
reduced from 3320 to 1664. The proposed structure is implemented in Artix-7 FPGA. Compared with the
proposed design, the conventional CSLA has 65.80% less area.
Duet advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. Due to which high speed adder architecture become important. Sever a ladder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed modified carry select adder using boot hen coder (BEC) Technique. Booth encoder, Mathematics is an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family.
FPGA Implementation of High Speed Architecture of CSLA using D-LatchesEditor IJMTER
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing
processors to perform fast arithmetic functions. The CSLA is used in many systems to overcome the
problem of carry propagation delay by independently generating multiple carries and then select a
carry to generate the sum. But the CSLA is not area efficient because it uses multiple pairs of Ripple
Carry Adders (RCA). Due to the rapidly growing mobile industry not only the faster arithmetic unit
but also less area and low power arithmetic units are needed. The modified CSLA architecture has
developed using Binary to Excess-1 converter (BEC). This paper proposes an efficient method which
replaces the BEC using D latch. Designs were developed using structural VHDL and synthesized in
Xilinx 13.2 with reference to FPGA device XC3S500E.
Implementation of Low Power and Area-Efficient Carry Select AdderIJMTST Journal
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform
fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area
and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to
significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-,-b square-root
CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA
architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA
with only a slight increase in the delay. This work evaluates the performance of the proposed designs in
terms of delay, area, power, and their products by hand with logical effort and through custom design and
layout in 0.18-m CMOS process technology. The results analysis shows that the proposed CSLA structure is
better than the regular SQRT CSLA.
Design of 8-Bit Comparator Using 45nm CMOS TechnologyIJMER
In this paper design of 8- bit binary comparator using 45nm CMOS technology is discussed.
This design needs less area and less number of transistors, also discussed about power and execution time. The
circuit has three output X, Y and Z. X is active high, when A>B, Y is active high when A=B and Z is active high
when both X and Y are active low. Design 1- bit comparator with the help of precharge gate.The design of 1-bit
comparator has been extended to implement an 8-bit comparator by connecting in series with pass
transistor between them. The design has been implemented in Microwind3.1, is tested successfully and
has been validated using Pspice for different measurable parameter.
Design and Verification of Area Efficient Carry Select Adderijsrd.com
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 16, 32 square - root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Highly -increasing requirement for mobile and several electronic devices want the use of VLSI circuits which are highly power efficient. The most primitive arithmetic operation in processors is addition and the adder is the most highly used arithmetic component of the processor. Carry Select Adder (CSA) is one of the fastest adders and the structure of the CSA shows that there is a possibility for increasing its efficiency by reducing the power dissipation and area in the CSA. This research paper presents power and delay analysis of various adders and proposed a 32-bit CSA that is implemented using variable size of the combination of adders, thus the proposed Carry select Adder (CSA) which has minimum Delay, and less power consumption hence improving the efficiency and speed of the Carry Select Adder.
Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...IJTET Journal
Abstract: In VLSI Technology, Carry Propagation Delay is the most important concern for the Adders. Adder is the most unavoidable component for the arithmetic performances. This paper is Modified Square Root-Carry Select Adder (SQRT-CSLA) design reduces the delay with 16 bit adder. Carry select adder have two units for Carry Generation (CG) and Carry Selection (CS). The modified SQRT-CSLA design can gives parallel path for carry propagation. So the overall adder delay has reduced. Modified design is obtained using Ripple Carry Adder (RCA) with Boolean Excess-1 Converter (BEC). BEC produces an output i.e., is an excess one result for given input bits. Then input bits and BEC output is given to multiplexer for carry selection. Use of BEC instead of dual RCA gives efficient carry propagation delay and it consumes the lower power and overall gates using in design is reduced with compared to carry select adder with dual RCA. The final sum is calculated using final sum generation.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
VLSI Implementation of 32-Bit Unsigned Multiplier Using CSLA & CLAAIJMTST Journal
In this project we are going to compare the performance of different adders implemented to the multipliers based on area and time needed for calculation. The CLAA based multiplier uses the delay time of 99ns for performing multiplication operation where as in CSLA based multiplier also uses nearly the same delay time for multiplication operation. But the area needed for CLAA multiplier is reduced to 31 % by the CSLA based multiplier to complete the multiplication operation.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
DESIGN OF RADIX-8 BOOTH MULTIPLIER USING KOGGESTONE ADDER FOR HIGH SPEED ARIT...eeiej_journal
This paper presents the design and implementation of radix-8 booth Multiplier .The number of partial
products are reduced to n/2 in radix-4We can reduce the number of partial products even further to n/3 by
using a higher radix-8 in the multiplier encoding, thereby obtaining a simpler CSA tree .This implies less
delay and a smaller area size .Since this multiplication operation is for both signed and unsigned
numbers,cost of the system can also be reduced.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation of Area & Power Optimized VLSI Circuits Using Logic TechniquesIOSRJVSP
To achieve the reduction of power consumption, optimizations are required at various levels of the design steps such as algorithm, architecture, logic and circuit & process techniques. This paper considers the two logic level approaches for low power digital design. Optimization techniques are carried to reduce switching activity power of individual logic-gates. we can reduce the power by using either circuit level optimization or logical level optimization. In this paper, the circuit level optimization process is followed to reduce the area and power. In the first approach, Modified gate diffusion input (GDI) logic is used in the proposed parallel asynchronous self time adder (PASTA) technique. Similarly, the structure of XOR gate and half adder is reduced to achieve the low area and low power. In second approach, Multi value logic based digital circuit is designed by increasing the representation domain from the two level (N=2) switching algebra to N > 2 levels. The main advantage of this approach is to compensate the inefficiency of existing integrated circuits that are used to implement the universal set of MVL gates. From the results, the proposed GDL logic based Adder offers less number of transistors (area) and low power consumption than the existing technique. And proposed MVL technique allows designing MVL digital circuit that is set to obtain the values from the binary circuits. Also this technique offers low power and small wiring delay, when compared to binary and three value logic. The simulation process is carried out by tanner toolv14.11 to check the functionality of the PASTA & MVL circuits.
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...IJERA Editor
Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing
demand of high speed and low power consumption processor. Speed of processor greatly depends on its
multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its
implementation is increasing day by day. Due to which high speed adder architecture become important. Several
adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we
introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry
select adder (CSA). Modified CSA depend on booth encoder (BEC) Technique. Booth encoder, Mathematics is
an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs
are implementation Xilinx Vertex device family.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
An Optimal Design of UP-DOWN Counter as SAR Logic Based ADC using CMOS 45nm T...IJERA Editor
In this paper an analog to digital converter architecture is introduced. The proposed design is based on Up-Down counter approach SAR type ADC. This design offers less design complexity which leads to low power consumption. Based on the proposed idea, a 4-bit ADC is simulated in Microwind 3.5 environment using 45nm CMOS technology with supply voltage of 1 V. The ADC is designed with control signal like Start of conversion (SOC) and End of conversion (EOC). The ADC design consumes 3.2mW of power. The proposed ADC design is optimized to area of 829.6µm2.
Design Of 64-Bit Parallel Prefix VLSI Adder For High Speed Arithmetic CircuitsIJRES Journal
Parallel prefix adder is a kind of process for speeding up the addition of the system of writing and calculating with numbers which use only two digits. Parallel prefix adders are also known as carry-tree adders and they are known to have the best performance in VLSI designs. Due to constraints on logic blog configurations a routing overhead, this performance advantage does not translate directly into FPGA implementations. Identifying the absolutely accurate area-delay tradeoff curve of the parallel prefix is an interesting problem that has received more attention in research because parallel prefix adder on the other hand represents a type of general adder structure that displays publically in flexible area-time tradeoffs for the design of adder. Many different types of parallel prefix adders are made to increase for optimizing area, fan out, speed and performance. For high speed performance tree like structure is must which helps in greater way. There are many different method used for designing parallel prefix adder based on their speed, size and performance. For area optimization we use Brent-Kung method. If our main purpose is to get the least timing then we have to use Kogg-Stone adder method.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implemenation of Vedic Multiplier Using Reversible Gates csandit
With DSP applications evolving continuously, there is continuous need for improved multipliers which are faster and power efficient. Reversible logic is a new and promising field which addresses the problem of power dissipation. It has been shown to consume zero power theoretically. Vedic mathematics techniques have always proven to be fast and efficient for solving various problems. Therefore, in this paper we implement Urdhva Tiryagbhyam algorithm using reversible logic thereby addressing two important issues – speed and power consumption of implementation of multipliers. In this work, the design of 4x4 Vedic multiplier is optimized by reducing the number of logic gates, constant inputs, and garbage outputs. This multiplier can find its application in various fields like convolution, filter applications, cryptography, and communication.
An Efficient High Speed Design of 16-Bit Sparse-Tree RSFQ AdderIJERA Editor
In this paper, we propse 16-bit sparse tree RSFQ adder (Rapid single flux quantam), kogge-stone adder, carry lookahead adder. In general N-bit adders like Ripple carry adder s(slow adders compare to other adders), and carry lookahead adders(area consuming adders) are used in earlier days. But now the most of industries are using parallel prefix adders because of their advantages compare to kogge-stone adder, carry lookahead adder, Our prefix sparse tree adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing addition. We simulate and synthesis different types of 16-bit sparse tree RSFQ adders using Xilinx ISE10.1i tool, By using these synthesis results, We noted the performance parameters like number of LUT’s and delay. We compare these three adders interms of LUT’s represents area) and delay values.
Area, Delay and Power Comparison of Adder TopologiesVLSICS Design
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry lookahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder and carry bypass adder. The module functionality and performance issues like area, power dissipation and propagation delay are analyzed at 0.12µm 6metal layer CMOS technology using microwind tool.
Similar to COSA and CSA based 32 -bit unsigned multipler (20)
Experimental Investigation of a Household Refrigerator Using Evaporative-Cool...inventy
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Comparative Study of the Quality of Life, Quality of Work Life and Organisati...inventy
People’s lives are increasingly centred on work; they spend at least one-third of their time within the organisations that employ them. Investigating the factors that interfere with employees’ well-being and the organisational environment is becoming an increasing concern in organisations. This article identifies the criteria of the quality of life (QoL), quality of working life (QWL) and organisational climate instruments to point out their similarities. For bibliographic construction and data research, articles were sought in national and international journals, books and dissertations/articles in SciELO, Science Direct, Medline and Pub Med databases. The results show direct relationships amongst QoL, QWL and organisational climate instruments. The relationship between QoL and QWL instruments is based on fair compensation, social interaction, organisational communication, working conditions and functional capacity. QWL and organisational climate instruments are related through social interaction and interfaces. QoL and organisational climate instruments are related based on social interaction, organisational communication, and work conditions.
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The decision making process of many operations are dependent on analysing very large data sets, previous decisions and their results. The information generated from the large data sets are used as an input for making decisions. Since the decisions to be taken in day to day operations are expanding, the time taken for manual decision making is also expanding. In order to reduce the time, cost and to increase the efficiency and accuracy, which are the most important things for customer satisfaction, many organisations are adopting the automated decision making systems. This paper is about the technologies used for automated decision making systems and the areas in which automated decisions systems works more efficiently and accurately.
Crystallization of L-Glutamic Acid: Mechanism of Heterogeneous β -Form Nuclea...inventy
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Evaluation of Damage by the Reliability of the Traction Test on Polymer Test ...inventy
In recent decades, polymers have undergone a remarkable historical development and their use has been greatly imposed by gradually dethroning most of the secular materials. These polymer materials have always distinguished themselves by their simple shaping and inexpensive price, their versatility, lightness, and chemical stability but despite their massive use in everyday life as well as in advanced technologies. Generally, these materials still not understood which requires a thorough knowledge of their chemical, physical, rheological and mechanical properties. This paper, we study the mechanical behavior of an amorphous polymer: Acrylonitrile Butadiene Styrene “ABS” by means of uniaxial tensile testing on pierced test pieces with different notch lengths ranging between 1 to 14mm.The proposed approach consists in analyzing the evolution of the global geometry of the obtained strain curves by taking into account the zones and characteristic points of these curves as well as the effect of the damage on the mechanical behavior of the polymer ABS, in order to visualize the evolution of the damage by a static model
Application of Kennelly’model of Running Performances to Elite Endurance Runn...inventy
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Development and Application of a Failure Monitoring System by Using the Vibra...inventy
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The Management of Protected Areas in Serengeti Ecosystem: A Case Study of Iko...inventy
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Size distribution and biometric relationships of little tunny Euthynnus allet...inventy
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Removal of Chromium (VI) From Aqueous Solutions Using Discarded Solanum Tuber...inventy
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Effect of Various External and Internal Factors on the Carrier Mobility in n-...inventy
The effect of various external (temperature, electric field, light) and intracrystalline (doping, initial resistivity) factors on the mobility of carriers in layered n-InSe semiconductor experimentally have been investigated. Scientific explanations of the results are proposed
Transient flow analysis for horizontal axial upper-wind turbineinventy
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Choice of Numerical Integration Method for Wind Time History Analysis of Tall...inventy
Wind tunnel tests are being performed routinely around the world for designing tall buildings but the advent of powerful computational tools will make time-history analysis for wind more common in near future. As the duration of wind storms ranges from tens of minutes to hours while earthquake durations are typically less than a three to four minutes, the choice of a time step size (Δt) for wind studies needs to be much larger both to reduce the computational time and to save disk space. As the error in any numerical solution of the equation of motion is dependent on step size (Δt), careful investigations on the choice of numerical integration methods for wind analyses are necessary. From a wide variety of integration methods available, it was decided to investigate three methods that seem appropriate for 3D-time history analysis of tall buildings for wind. These are modal time history analysis, the Hilber-Hughes-Taylor (HHT) method or α-method with α=- 0.1, and the Newmark method with β=0.25 and γ=0.5 ( i.e., trapezoidal rule). SAP2000, a common structural analysis software tool, and a 64-story structure are used to conduct all the analyses in this paper. A boundary layer wind tunnel (BLWT) pressure time history measured at 120 locations around the building envelope of a similar structure is used for the analyses. Analyses performed with both the HHT and Newmark-method considering P-delta effects show that second order effects have a considerable impact on both displacement and acceleration response. This result shows that it is necessary to account P-delta effect for wind analysis of tall buildings. As the direct integration time history analysis required very large computation times and very large computer physical memory for a wind duration of hours, a modal analysis with reduced stiffness is considered as a good alternative. For that purpose, a non-linear static analysis of the structure with a load combination of 1.0D + 1.0L is performed in SAP2000 and the reduced stiffness of the structure after the analysis is used to conduct an eigenvalue analysis to extract the mode shapes and frequencies of this structure. Then the first 20- modes are used to perform a modal time history analysis for wind load. The result shows that the responses from modal analysis with “20-mode (reduced stiffness)” are comparable with that from the P-Δ analyses of Newmark-method
Impacts of Demand Side Management on System Reliability Evaluationinventy
Electricity demand in Saudi Arabia is steadily increasing as electrical loads grows at a rate of about 7% per year, this represents a high rate by all standards, and largely due to population growth, as well as due to government subsidies which may lead to prices much lower than actual production cost. This growth represents a challenge that requires Saudi Electricity Company (SEC) to invest huge amounts of money every year, for the construction of additional generation capacity along with the reinforcement of transmission network to meet the consumption growth.Also the demand varies frequently throughout the day, causing a waste of a large part of the energy. SEC believes the optimum solution lies in altering the load shape in order to have a better balance between customer’s consumption and SEC’s generation, This paper describes the method for improving the power system reliability by shifting the portion of peak load to off-peak periods This load management scheme can be achieved by lifting the generation during off peak periods and utilizing the stored energy during peak periods. A hybrid set up involving solar and wind energy along with batteries can also be used to store energy and utilize it during peak periods.
Reliability Evaluation of Riyadh System Incorporating Renewable Generationinventy
In this paper, the experience of Saudi Electricity Company (SEC) in analyzing the generation adequacy for Year 2013 is presented. This analysis is conducted by calculating several reliability indices for Riyadh system hourly load during all four seasonal periods. The reliability indices are gauged against the international utility practice. SEC also plans to introduce renewable energy into the network in order to secure the environmental standards and reduce fuel costs of conventional generation. Thus, the reliability improvement due to different integration levels of Solar and Wind generating sources has also been investigated. The capacity value provided by these variable renewable energy sources (VERs) to reliably meet the system load has been calculated using effective load carrying capability (ELCC) technique with a loss of load expectancy metric.
The effect of reduced pressure acetylene plasma treatment on physical charact...inventy
The capacitors are increasingly being used as energy storage devicesin various power systems. The scientists of the world are tryingto maximize the electrical capacity of the supercapacitors. To achieve this purpose, numerous method sare used: the surface activation of electrodes, the surface etching using the electronbeam, the electrode etching with variousgasplasma, etc. The purpose of this work is toresearch how the properties of carbon electrodes depend on the plasma parameters at whichtheywere formed. The largest surface area ofcarbonelectrodeof47.25m2 /gis obtainedat 15 ofAr/C2H2gasratio. Meanwhile, theSEMimages show that the disruption of structures with low bond energies and the formation of new onesare taking place when the carbon electrodes are etched at acetylene plasma and placed on carbon electrode. The measurements of capacitance showthat capacitors with affectedelectrodes have about10-15% highercapacity than those not treated with acetyleneplasma.
Experimental Investigation of Mini Cooler cum Freezerinventy
In general cases the refrigerator could be converted into an air conditioner by attaching a fan. Thus a cooler as well as freezer is obtained in a single set up. The freezer can be converted to an air conditioner when the outside air is allowed to flow beside the cooling coil and is forced outside by an exhaust fan. In this case a mini scale cooler cum freezer using R134a as refrigerant was fabricated and tested In our mini project work we had designed, fabricated and experimentally analysed a mini cooler cum freezer. From the observations and calculations, the results of mini cooler cum freezer are obtained and are compared.
Growth and Magnetic properties of MnGeP2 thin filmsinventy
We have successfully grown MnGeP2 thin films on GaAs (100) substrate. A ferromagnetic transition near 320 K has been observed by temperature dependent magnetization and resistance measurements. Field dependent magnetization experiments have shown that the coercive fields at 5, 250, and 300 K are 3870, 1380 and 155 Oe, respectively. Magnetoresistance and Hall measurements have displayed that hole conduction is dominant in MnGeP2. PACS: 75.50.Pp, 75.70.-i, 85.70.-w, 73.50.-h
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024Albert Hoitingh
In this session I delve into the encryption technology used in Microsoft 365 and Microsoft Purview. Including the concepts of Customer Key and Double Key Encryption.
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
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COSA and CSA based 32 -bit unsigned multipler
1. Research Inventy: International Journal Of Engineering And Science
Vol.4, Issue 12 (December 2014), PP 12-16
Issn (e): 2278-4721, Issn (p):2319-6483, www.researchinventy.com
12
COSA and CSA based 32 -bit unsigned multipler
Lekshmi Suresh
Electronics and Communication MCET,Pathanamthitta
Pathanamthitta,India
ABSTRACT: In this paper, design of two different arraymultipliers are presented, one by using conditional
sum (COSA) logic for addition of partial product terms and another by introducing Carry Save Adder (CSA) in
partial product lines. The multipliers presented in this paper were all modeled using VHDL (Very High Speed
Integration Hardware Description Language) for 32-bit unsigned data. The comparison is done on the basis of
three performanceparameters i.e. Area, Speed and Power consumption. To design an efficient integrated circuit
in terms of area, power and speed, has become a challenging task in modern VLSI design field. Previously in
the literature, performance analysis was carried out between multiplier using Ripple carry adder (RCA) and by
using CLA. In this work, same multiplier is designed by using CSA logic and compare it’s performance with the
multiplier designed by using CSLA logic. Multiplier with CSA gives better result in terms of speed (78.3%
improvement), area (reduced by 4.2%) and power consumption (decreased by 1.4%).
INDEX TERMS: Multiplier, Carry Save Adder, Conditional Sum Adder, VHDL Simulation
I. INTRODUCTION
Addition is the most common and often used arithmetic operation on microprocessor, digital signal
processor, especially digital computers. Also, it serves as a building block for synthesis all other arithmetic
operations. Therefore, regarding the efficient implementation of an arithmetic unit, the binary adder structures
become a very critical hardware unit. Multipliers are most commonly used in various electronic applications e.g.
Digital signal processing in which multipliers are used to perform various algorithms like FIR, IIR etc. Earlier,
the major challenge for VLSI designer was to reduce area of chip by using efficient optimization techniques to
satisfy MOORE‟S law. Then the next phase is to increase the speed of operation to achieve fast calculations
like, in today‟s microprocessors millions of instructions are performed per second. Speed of operation is one of
the major constraints in designing DSP processors and today‟s general-purpose processors. However area and
speed are two conflicting constraints. So improving speed results always in larger areas. Now, as most of
today‟s commercial electronic products areportable like Mobile, Laptops etc. that require more battery back up.
Therefore, lot of research is going on to reduce power consumption. So, in this paper it is tried to find out the
best solution to achieve low power consumption, less area required and high speed for multiplier operation.
In this project we are going to compare the performance of different adders implemented to the multipliers
based on area and time needed for calculation.On comparison with the conditional sum (COSA) based
multiplier the area of calculation of the carry save adder (CSA) based multiplier is smaller and better with nearly
same delay time. Here we are dealing with the comparison in the bit range of n*n (32*32) as input and 2n (64)
bit output.
II. CONDITIONAL SUM ADDER
A conditional-sum adder is actually a (log2 k)-level carry-select adder. Consider that we need to add
ai and bi which are the ith bits of operands A and B,respectively.In the conditional sum algorithm ,instead of
waiting for the arrival of carry value,instead of waiting for the arrival of carry, conditional carry and conditional
sum are generated by considering both possible values of the carry-in bit.The result of adding ai,bi, and either a
0 or 1 carry-in bit is a two bit number.
In general, the algorithm is given by:
If Carry in =1, then the sum and carry out are given by,
Sum (i) =a (i) xor b (i) xor '1'. (1)
Carry (i+ 1) = (a (i) and b (i)) or (b (i) or a (i)). (2)
If Carry in =0, then the sum and carry out are given by,
The sum function:
Sum (i) = a (i) xor b (i).
Carry (i+ 1) = (a (i) and b (i)).
Consider the following example,
2. COSA and CSA based 32 –bit…
13
Fig.1.Conditional sum and Conditional carries
The conditional sum adder of 8-bit is given by,
Fig.2. Carry Select Adder with 8-bit
III. CARRY SAVE ADDER
Basically, carry save adder is used to compute sum of three or more n-bit binary numbers. Carry save
adder is same as a full adder. The full adder is usually implemented with a reduced delay from Cin to Cout
because the carry chain is the critical delay path in adders. Unfortunately, there is no single carry chain in the
carry save adder trees in multipliers. Here we are computing sum of two 32-bit binary numbers, so we take 32
full adders at first stage. Carry save unit consists of 32 full adders, each of which computes single sum and carry
bit based only on the corresponding bits of the two input numbers. Let X and Y are two 32-bit numbers and
produces partial sum and carry as S and C :
Si = Xi xor Yi (3)
Ci = Xi and Yi (4)
The final addition is then computed as:
1. Shifting the carry sequence C left by one place.
2. Placing a 0 to the front (MSB) of the partial sum
sequence S.
3. Finally, a ripple carry adder is used to add these two together and computing the resulting sum.
This can be represented in figure 3.
3. COSA and CSA based 32 –bit…
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Fig.3. Computational flow of Carry Save Adder
IV. IMULTIPLTER FOR UNSIGNED DATA
In Array multiplier, almost identical calls array is used for generation of the bit-products and
accumulation. All bit-products are generated in parallel and collected through an array of full adders or any
other type of adders and final adder. Array multiplier has a regular structure that simplifies the wiring and the
layout. Therefore, among other multiplier structures, array multiplier takes up the least amount of area but it is
also the slowest with the latency proportional to O (Wd) where Wd is the word length of the operand.
Instead of using Ripple carry adder (RCA), here we use Carry lookahead logic and Carry save adder for adding
each group of partial product terms because RCA is slowest adder among all other fast adders available.Figure
3& 4 shows architecture of 32-bit Array multiplier using CSLA and CSA respectively to add each group of
partial products in parallel.
Fig.4. Multiplier logic using COSA
Fig.5. Multiplier implemented using CSA logic
4. COSA and CSA based 32 –bit…
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V. MULTIPLICATION ALGORITHM
There are product registers , multiplier and multiplicand registers. They are of 64, 32 and 32-bits
respectively .The algorithm used for the multiplication is given as follows,
[1] Clear the product register and the half MSB of the product register
[2] Check the last bit of the multiplier, if it is „1‟ then add with the product register
[3] Shift the product register once
[4] If the lsb of multiplier is „0‟,then only shift the product register only once
[5] Add all the partial products
This algorithm can be represented below:
Fig 6. Algorithm
VI. SIMULATION RESULTS
The VHDL simulation of the two multiplier is presented in this section. For simulation Modelsim SE
6.2c tool is used. The multipliers use 32-bit values as shown in simulation waveforms.
Fig.7 Simulation of COSA based multiplier
Fig.8 Simulation of CSA based multiplier
5. COSA and CSA based 32 –bit…
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VII. CONCLUSION
From the above analysis,the 32-bit unsigned multiplier implemented using COSA and CSA provide great
result as compared to the other high speed adder based multipler like ripple cary based multiplier etc.By analysis,
the area consumed by carry save adder based multiplier is less than that of conditional sum adder based
multiplier.
REFERENNCES
[1] V. Vijayalakshmi , R.Seshadri, Dr.S.Ramakrishnan, “Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and
CSLA”,IEEEProceedings on Circuits,Devices and Systems,2013
[2] Raminder Preet Pal Singh, Parveen Kumar, Balwinder Singh, “Performance Analysis of 32-Bit Array Multiplier with a Carry Save
Adder and with a Carry-Look-Ahead Adder”, International Journal of Recent Trends in Engineering, Vol 2, No. 6, November 2009
[3] P. S. Mohanty, "Design and Implementation of Faster and Low PowernMultipliers", Bachelor Thesis. National Institute of
Technology, Rourkela, 2009
[4] Ahmet SERTBAS, R.Selami OZBEY,” A performance analysis of classified binary adder architectures and the vhdl
simulations”,Journal of electrical & electronics engineering,Vol.4,2004‟