Addition is one of the common and widely used fundamental arithmetic operation in many VLSI systems. The critical elements in general purpose and digital-signal processing processors are High performance VLSI integer adders as they are employed in the design of Arithmetic-Logic Units, in floating-point arithmetic data paths and in address generation units. The performance parameters for any adder are area, speed and delay. By using Square Root Carry Select Adder (SQRT CSLA), speed can be achieved. In designing new architecture, the Tradeoff between those parameters plays the major role. We can reduce area by using Zero Finding Logic (ZFC) technique, from the structure of SQRT CSLA. By using the Modified architecture we can reduce area. We can implement Booth multiplier by using the CSLA and SQRT CSLA with Zero finding logic. Implementation of Booth multiplier by using CSLA and SQRT CSLA with Zero finding logic is proposed for better speed applications and efficient area applications.
Area, Delay and Power Comparison of Adder TopologiesVLSICS Design
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry lookahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder and carry bypass adder. The module functionality and performance issues like area, power dissipation and propagation delay are analyzed at 0.12µm 6metal layer CMOS technology using microwind tool.
128-Bit Area Efficient Reconfigurable Carry Select Adder ijcisjournal
Adders are one of the most critical arithmetic circuits in a system and their throughput affects the overall
performance of the system. Carry Select Adder (CSLA) is one of the fastest adders used in many dataprocessing
processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that
there is scope for reducing the area and power consumption in the CSLA. In this paper, we proposed an
area-efficient carry select adder by sharing the common Boolean logic term. After logic optimization and
sharing partial circuit, we only need one XOR gate and one inverter gate for sum generation. Through the
multiplexer, we can select the final-sum only and for carry selection we need only one AND gate and one
OR gate. Based on this modification 16-, 32-, 64-, and 128-bit CSLA architecture have been developed and
compared with the conventional CSLA architecture. The proposed design greatly reduces the area
compared to other CSLAs. From this improvement, the gate count of a 128-bit carry select adder can be
reduced from 3320 to 1664. The proposed structure is implemented in Artix-7 FPGA. Compared with the
proposed design, the conventional CSLA has 65.80% less area.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and implementation of Closed Loop Control of Three Phase Interleaved P...IJMTST Journal
A single-phase, three-level, single-stage power-factor corrected AC/DC converter operated under closed
loop manner is presented. That operates with a single controller to regulate the output voltage and the input
inductor act as a boost inductor to have a single stage power factor correction with good output response. The
paper deals with a new single stage three level ac-dc converter which performs both power factor correction
and voltage regulation in a single stage. The proposed converter has two separate controllers, one for power
factor correction and the other for regulating the output voltage. A comprehensive review of the existing single
stage topologies has been carried out. Then the operating principle, control scheme and the design of the new
converter are presented. The proposed converter is having an input power factor close to unity and better
voltage regulation compared to the conventional ac-dc converter topologies. Proposed topology is evaluated
through Matlab/Simulink platform and simulation results are conferred.
Highly -increasing requirement for mobile and several electronic devices want the use of VLSI circuits which are highly power efficient. The most primitive arithmetic operation in processors is addition and the adder is the most highly used arithmetic component of the processor. Carry Select Adder (CSA) is one of the fastest adders and the structure of the CSA shows that there is a possibility for increasing its efficiency by reducing the power dissipation and area in the CSA. This research paper presents power and delay analysis of various adders and proposed a 32-bit CSA that is implemented using variable size of the combination of adders, thus the proposed Carry select Adder (CSA) which has minimum Delay, and less power consumption hence improving the efficiency and speed of the Carry Select Adder.
Area, Delay and Power Comparison of Adder TopologiesVLSICS Design
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry lookahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder and carry bypass adder. The module functionality and performance issues like area, power dissipation and propagation delay are analyzed at 0.12µm 6metal layer CMOS technology using microwind tool.
128-Bit Area Efficient Reconfigurable Carry Select Adder ijcisjournal
Adders are one of the most critical arithmetic circuits in a system and their throughput affects the overall
performance of the system. Carry Select Adder (CSLA) is one of the fastest adders used in many dataprocessing
processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that
there is scope for reducing the area and power consumption in the CSLA. In this paper, we proposed an
area-efficient carry select adder by sharing the common Boolean logic term. After logic optimization and
sharing partial circuit, we only need one XOR gate and one inverter gate for sum generation. Through the
multiplexer, we can select the final-sum only and for carry selection we need only one AND gate and one
OR gate. Based on this modification 16-, 32-, 64-, and 128-bit CSLA architecture have been developed and
compared with the conventional CSLA architecture. The proposed design greatly reduces the area
compared to other CSLAs. From this improvement, the gate count of a 128-bit carry select adder can be
reduced from 3320 to 1664. The proposed structure is implemented in Artix-7 FPGA. Compared with the
proposed design, the conventional CSLA has 65.80% less area.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and implementation of Closed Loop Control of Three Phase Interleaved P...IJMTST Journal
A single-phase, three-level, single-stage power-factor corrected AC/DC converter operated under closed
loop manner is presented. That operates with a single controller to regulate the output voltage and the input
inductor act as a boost inductor to have a single stage power factor correction with good output response. The
paper deals with a new single stage three level ac-dc converter which performs both power factor correction
and voltage regulation in a single stage. The proposed converter has two separate controllers, one for power
factor correction and the other for regulating the output voltage. A comprehensive review of the existing single
stage topologies has been carried out. Then the operating principle, control scheme and the design of the new
converter are presented. The proposed converter is having an input power factor close to unity and better
voltage regulation compared to the conventional ac-dc converter topologies. Proposed topology is evaluated
through Matlab/Simulink platform and simulation results are conferred.
Highly -increasing requirement for mobile and several electronic devices want the use of VLSI circuits which are highly power efficient. The most primitive arithmetic operation in processors is addition and the adder is the most highly used arithmetic component of the processor. Carry Select Adder (CSA) is one of the fastest adders and the structure of the CSA shows that there is a possibility for increasing its efficiency by reducing the power dissipation and area in the CSA. This research paper presents power and delay analysis of various adders and proposed a 32-bit CSA that is implemented using variable size of the combination of adders, thus the proposed Carry select Adder (CSA) which has minimum Delay, and less power consumption hence improving the efficiency and speed of the Carry Select Adder.
Design and Verification of Area Efficient Carry Select Adderijsrd.com
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 16, 32 square - root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area.
Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...IJTET Journal
Abstract: In VLSI Technology, Carry Propagation Delay is the most important concern for the Adders. Adder is the most unavoidable component for the arithmetic performances. This paper is Modified Square Root-Carry Select Adder (SQRT-CSLA) design reduces the delay with 16 bit adder. Carry select adder have two units for Carry Generation (CG) and Carry Selection (CS). The modified SQRT-CSLA design can gives parallel path for carry propagation. So the overall adder delay has reduced. Modified design is obtained using Ripple Carry Adder (RCA) with Boolean Excess-1 Converter (BEC). BEC produces an output i.e., is an excess one result for given input bits. Then input bits and BEC output is given to multiplexer for carry selection. Use of BEC instead of dual RCA gives efficient carry propagation delay and it consumes the lower power and overall gates using in design is reduced with compared to carry select adder with dual RCA. The final sum is calculated using final sum generation.
Design of High Speed 128 bit Parallel Prefix AddersIJERA Editor
In this paper, we propose 128-bit Kogge-Stone, Ladner-Fischer, Spanning tree parallel prefix adders and
compared with Ripple carry adder. In general N-bit adders like Ripple Carry Adders (slow adders compare to
other adders), and Carry Look Ahead adders (area consuming adders) are used in earlier days. But now the most
Industries are using parallel prefix adders because of their advantages compare to other adders. Parallel prefix
adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor
while performing addition. While when we want to design any 128-bit operating systems and processors we can
use these adders in place of regular adders. We simulate and synthesis different types of 128-bit prefix adders
using Xilinx ISE 12.3 tool. By using these synthesis results, we noted the performance parameters like number
of LUTs and delay. We compare these three adders in terms of LUTs (represents area) and delay values.
A Computers Architecture project on Barrel shifterssvrohith 9
A Barrel Shifter is a logic component that perform shift or rotate operations. Barrel shifters are applicable for digital signal processors and processors, here we designed 16-bit barrel shifter using 2X1 MUXs in Logisim simulation
FPGA Implementation of High Speed Architecture of CSLA using D-LatchesEditor IJMTER
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing
processors to perform fast arithmetic functions. The CSLA is used in many systems to overcome the
problem of carry propagation delay by independently generating multiple carries and then select a
carry to generate the sum. But the CSLA is not area efficient because it uses multiple pairs of Ripple
Carry Adders (RCA). Due to the rapidly growing mobile industry not only the faster arithmetic unit
but also less area and low power arithmetic units are needed. The modified CSLA architecture has
developed using Binary to Excess-1 converter (BEC). This paper proposes an efficient method which
replaces the BEC using D latch. Designs were developed using structural VHDL and synthesized in
Xilinx 13.2 with reference to FPGA device XC3S500E.
An Efficient High Speed Design of 16-Bit Sparse-Tree RSFQ AdderIJERA Editor
In this paper, we propse 16-bit sparse tree RSFQ adder (Rapid single flux quantam), kogge-stone adder, carry lookahead adder. In general N-bit adders like Ripple carry adder s(slow adders compare to other adders), and carry lookahead adders(area consuming adders) are used in earlier days. But now the most of industries are using parallel prefix adders because of their advantages compare to kogge-stone adder, carry lookahead adder, Our prefix sparse tree adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing addition. We simulate and synthesis different types of 16-bit sparse tree RSFQ adders using Xilinx ISE10.1i tool, By using these synthesis results, We noted the performance parameters like number of LUT’s and delay. We compare these three adders interms of LUT’s represents area) and delay values.
Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are
well-suited for VLSI implementations. In this paper, a novel framework is introduced, which allows
the design of parallel-prefix Ling adders. The proposed approach saves one-logic level of
implementation compared to the parallel-prefix structures proposed for the traditional definition of
carry look ahead equations and reduces the fan out requirements of the design. Experimental results
reveal that the proposed adders achieve delay reductions of up to 14 percent when compared to the
fastest parallel-prefix architectures presented for the traditional definition of carry equations
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Verification of Area Efficient Carry Select Adderijsrd.com
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 16, 32 square - root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area.
Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...IJTET Journal
Abstract: In VLSI Technology, Carry Propagation Delay is the most important concern for the Adders. Adder is the most unavoidable component for the arithmetic performances. This paper is Modified Square Root-Carry Select Adder (SQRT-CSLA) design reduces the delay with 16 bit adder. Carry select adder have two units for Carry Generation (CG) and Carry Selection (CS). The modified SQRT-CSLA design can gives parallel path for carry propagation. So the overall adder delay has reduced. Modified design is obtained using Ripple Carry Adder (RCA) with Boolean Excess-1 Converter (BEC). BEC produces an output i.e., is an excess one result for given input bits. Then input bits and BEC output is given to multiplexer for carry selection. Use of BEC instead of dual RCA gives efficient carry propagation delay and it consumes the lower power and overall gates using in design is reduced with compared to carry select adder with dual RCA. The final sum is calculated using final sum generation.
Design of High Speed 128 bit Parallel Prefix AddersIJERA Editor
In this paper, we propose 128-bit Kogge-Stone, Ladner-Fischer, Spanning tree parallel prefix adders and
compared with Ripple carry adder. In general N-bit adders like Ripple Carry Adders (slow adders compare to
other adders), and Carry Look Ahead adders (area consuming adders) are used in earlier days. But now the most
Industries are using parallel prefix adders because of their advantages compare to other adders. Parallel prefix
adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor
while performing addition. While when we want to design any 128-bit operating systems and processors we can
use these adders in place of regular adders. We simulate and synthesis different types of 128-bit prefix adders
using Xilinx ISE 12.3 tool. By using these synthesis results, we noted the performance parameters like number
of LUTs and delay. We compare these three adders in terms of LUTs (represents area) and delay values.
A Computers Architecture project on Barrel shifterssvrohith 9
A Barrel Shifter is a logic component that perform shift or rotate operations. Barrel shifters are applicable for digital signal processors and processors, here we designed 16-bit barrel shifter using 2X1 MUXs in Logisim simulation
FPGA Implementation of High Speed Architecture of CSLA using D-LatchesEditor IJMTER
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing
processors to perform fast arithmetic functions. The CSLA is used in many systems to overcome the
problem of carry propagation delay by independently generating multiple carries and then select a
carry to generate the sum. But the CSLA is not area efficient because it uses multiple pairs of Ripple
Carry Adders (RCA). Due to the rapidly growing mobile industry not only the faster arithmetic unit
but also less area and low power arithmetic units are needed. The modified CSLA architecture has
developed using Binary to Excess-1 converter (BEC). This paper proposes an efficient method which
replaces the BEC using D latch. Designs were developed using structural VHDL and synthesized in
Xilinx 13.2 with reference to FPGA device XC3S500E.
An Efficient High Speed Design of 16-Bit Sparse-Tree RSFQ AdderIJERA Editor
In this paper, we propse 16-bit sparse tree RSFQ adder (Rapid single flux quantam), kogge-stone adder, carry lookahead adder. In general N-bit adders like Ripple carry adder s(slow adders compare to other adders), and carry lookahead adders(area consuming adders) are used in earlier days. But now the most of industries are using parallel prefix adders because of their advantages compare to kogge-stone adder, carry lookahead adder, Our prefix sparse tree adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing addition. We simulate and synthesis different types of 16-bit sparse tree RSFQ adders using Xilinx ISE10.1i tool, By using these synthesis results, We noted the performance parameters like number of LUT’s and delay. We compare these three adders interms of LUT’s represents area) and delay values.
Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are
well-suited for VLSI implementations. In this paper, a novel framework is introduced, which allows
the design of parallel-prefix Ling adders. The proposed approach saves one-logic level of
implementation compared to the parallel-prefix structures proposed for the traditional definition of
carry look ahead equations and reduces the fan out requirements of the design. Experimental results
reveal that the proposed adders achieve delay reductions of up to 14 percent when compared to the
fastest parallel-prefix architectures presented for the traditional definition of carry equations
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation of Area & Power Optimized VLSI Circuits Using Logic TechniquesIOSRJVSP
To achieve the reduction of power consumption, optimizations are required at various levels of the design steps such as algorithm, architecture, logic and circuit & process techniques. This paper considers the two logic level approaches for low power digital design. Optimization techniques are carried to reduce switching activity power of individual logic-gates. we can reduce the power by using either circuit level optimization or logical level optimization. In this paper, the circuit level optimization process is followed to reduce the area and power. In the first approach, Modified gate diffusion input (GDI) logic is used in the proposed parallel asynchronous self time adder (PASTA) technique. Similarly, the structure of XOR gate and half adder is reduced to achieve the low area and low power. In second approach, Multi value logic based digital circuit is designed by increasing the representation domain from the two level (N=2) switching algebra to N > 2 levels. The main advantage of this approach is to compensate the inefficiency of existing integrated circuits that are used to implement the universal set of MVL gates. From the results, the proposed GDL logic based Adder offers less number of transistors (area) and low power consumption than the existing technique. And proposed MVL technique allows designing MVL digital circuit that is set to obtain the values from the binary circuits. Also this technique offers low power and small wiring delay, when compared to binary and three value logic. The simulation process is carried out by tanner toolv14.11 to check the functionality of the PASTA & MVL circuits.
DESIGN AND IMPLEMENTATION OF AN IMPROVED CARRY INCREMENT ADDERVLSICS Design
A complex digital circuit comprises of adder as a basic unit. The performance of the circuit depends on the
design of this basic adder unit. The speed of operation of a circuit is one of the important performance
criteria of many digital circuits which ultimately depends on the delay of the basic adder unit. Many
research works have been devoted in improving the delay of the adder circuit. In this paper we have
proposed an improved carry increment adder (CIA) that improves the delay performance of the circuit. The
improvement is achieved by incorporating carry look adder (CLA) in the design of CIA contrary to the
previous design of CIA that employs ripple carry adder (RCA). A simulation study is carried out for
comparative analysis. The coding is done in Verilog hardware description language (HDL) and the
simulation is carried out in Xilinx ISE 13.1 environment.
VLSI Implementation of 32-Bit Unsigned Multiplier Using CSLA & CLAAIJMTST Journal
In this project we are going to compare the performance of different adders implemented to the multipliers based on area and time needed for calculation. The CLAA based multiplier uses the delay time of 99ns for performing multiplication operation where as in CSLA based multiplier also uses nearly the same delay time for multiplication operation. But the area needed for CLAA multiplier is reduced to 31 % by the CSLA based multiplier to complete the multiplication operation.
DESIGN AND IMPLEMENTATION OF AN IMPROVED CARRY INCREMENT ADDERVLSICS Design
A complex digital circuit comprises of adder as a basic unit. The performance of the circuit depends on the design of this basic adder unit. The speed of operation of a circuit is one of the important performance criteria of many digital circuits which ultimately depends on the delay of the basic adder unit. Many research works have been devoted in improving the delay of the adder circuit. In this paper we have
proposed an improved carry increment adder (CIA) that improves the delay performance of the circuit. The improvement is achieved by incorporating carry look adder (CLA) in the design of CIA contrary to the previous design of CIA that employs ripple carry adder (RCA). A simulation study is carried out for comparative analysis. The coding is done in Verilog hardware description language (HDL) and the simulation is carried out in Xilinx ISE 13.1 environment.
Here we describe the design details and performance of proposed Carry Propagate Adder based on GDI
technique. GDI technique is power efficient technique for designing digital circuit that consumes less
power as compare to most commonly used CMOS technique. GDI also has an advantage of minimum
propagation delay, minimum area required and less complexity for designing any digital circuit. We
designed Carry Propagate Adder using GDI technique and compared its performance with CMOS
technique in terms of area, delay and power dissipation. Circuit designed using CADENCE EDA tool and
simulated using SPECTRE VIRTUOSO tool at 0.18m technology. Comparative performance result shows
that Carry Propagate Adder using GDI technique dissipated 55.6% less power as compare to Carry
Propagate Adder using CMOS technique.
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONSVLSICS Design
This report examines the subject of sub threshold leakage on carry save adder. When the gate to source voltage reduces to the threshold voltage at that place is yet some amount of current flow in the circuit and that is undesired. As the process technology advancing much rapidly the threshold voltage of MOS devices reduces very drastically, and it must be applied in lower power devices since it contributes to low amount of leakage current which confine increases the power consumption of the devices. Adders are the basic building blocks for any digital circuit design and used in almost all arithmetic’s. The CSA proves efficient adders due to its quick and precise computations. Hence this paper performs sub threshold analysis on CSA and the scrutinize results that the total average power is around 4.93µW, the propagation delay for complete operation is 16.3ns and since this design uses GDI cell so there is a reduction in area with 37%.
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONSVLSICS Design
This report examines the subject of sub threshold leakage on carry save adder. When the gate to source voltage reduces to the threshold voltage at that place is yet some amount of current flow in the circuit and that is undesired. As the process technology advancing much rapidly the threshold voltage of MOS devices reduces very drastically, and it must be applied in lower power devices since it contributes to low amount
of leakage current which confine increases the power consumption of the devices. Adders are the basic
building blocks for any digital circuit design and used in almost all arithmetic’s. The CSA proves efficient adders due to its quick and precise computations. Hence this paper performs sub threshold analysis on CSA and the scrutinize results that the total average power is around 4.93µW, the propagation delay for complete operation is 16.3ns and since this design uses GDI cell so there is a reduction in area with 37%.
PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONSVLSICS Design
This report examines the subject of sub threshold leakage on carry save adder. When the gate to source voltage reduces to the threshold voltage at that place is yet some amount of current flow in the circuit and that is undesired. As the process technology advancing much rapidly the threshold voltage of MOS devices reduces very drastically, and it must be applied in lower power devices since it contributes to low amount of leakage current which confine increases the power consumption of the devices. Adders are the basic building blocks for any digital circuit design and used in almost all arithmetic’s. The CSA proves efficient adders due to its quick and precise computations. Hence this paper performs sub threshold analysis on CSA and the scrutinize results that the total average power is around 4.93µW, the propagation delay for complete operation is 16.3ns and since this design uses GDI cell so there is a reduction in area with 37%
Efficient implementation of full adder for power analysis in cmos technologyIJARIIT
In recent days, the real-time application and fast arithmetic operations require highly efficient arithmetic hardware
architecture to improve the system performances. The adder plays a vital role in digital circuits, the earlier hardware
architecture using conventional CMOS and transmission logic gate based full adder design. Moreover, the techniques using
more number of transistors and consume larger power and delay so we proposed the techniques pass-transistor logic and
transmission gate based hybrid pass logic. The hybrid technique is used to reduce the number of the transistor, so the delay
and power consumption will be reduced when compared with the earlier techniques. The proposed technique design was
implemented using 16 transistors in 180nm CMOS technology and it consumes 8.2075nW power and the delay reduced to
5.0146ns.
LOGIC OPTIMIZATION USING TECHNOLOGY INDEPENDENT MUX BASED ADDERS IN FPGAVLSICS Design
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. Therefore, careful optimization of the adder is of the greatest importance. This optimization can be attained
in two levels; it can be circuit or logic optimization. In circuit optimization the size of transistors are manipulated, where as in logic optimization the Boolean equations are rearranged (or manipulated) to optimize speed, area and power consumption. This paper focuses the optimization of adder through technology independent mapping. The work presents 20 different logical construction of 1-bit adder cell in CMOS logic and its performance is analyzed in terms of transistor count, delay and power dissipation. These performance issues are analyzed through Tanner EDA with TSMC MOSIS 250nm technology. From this analysis the optimized equation is chosen to construct a full adder circuit in terms of multiplexer. This logic optimized multiplexer based adders are incorporated in selected existing adders like ripple carry
adder, carry look-ahead adder, carry skip adder, carry select adder, carry increment adder and carry save adder and its performance is analyzed in terms of area (slices used) and maximum combinational path delay as a function of size. The target FPGA device chosen for the implementation of these adders was Xilinx ISE 12.1 Spartan3E XC3S500-5FG320. Each adder type was implemented with bit sizes of: 8, 16, 32, 64 bits. This variety of sizes will provide with more insight about the performance of each adder in terms of area and delay as a function of size.
In present day MAC unit is demanded in most of the Digital signal processing. Function of addition and multiplication is performed by the MAC unit. MAC operates in two stages. Firstly, multiplier computes the given number output and the result is forwarded to second stage i.e. addition/accumulation operates. Speed of multiplier is important in MAC unit which determines critical path as well as area is also of great importance in designing of MAC unit. Multiplier plays an important roles in many digital signal processing (DSP) applications such as in convolution, digital filters and other data processing unit. Many research has been performed on MAC implementation. This paper provides analysis of the research and investigations held till now.
High –Speed Implementation of Design and Analysis by Using Parallel Prefix Ad...IOSRJECE
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High Speed and Area Efficient Booth Multiplier Using SQRT CSLA with Zero Finding Logic
1. P.Pavani Sushma et al. Int. Journal of Engineering Research and Application www.ijera.com
ISSN : 2248-9622, Vol. 7, Issue 4, ( Part -1) April 2017, pp.75-80
www.ijera.com DOI: 10.9790/9622-0704017580 75 | P a g e
High Speed and Area Efficient Booth Multiplier Using SQRT
CSLA with Zero Finding Logic
P.Pavani Sushma1
, J.Priyanka2
,R.Lalitha3
,K.Manoj4
,N.Divya5
,V.Suma6
Department Of Electronics And Communication Engineering,Liet,Jonnada,Jntuk,Vizianagaram
ABSTRACT
Addition is one of the common and widely used fundamental arithmetic operation in many VLSI systems. The
critical elements in general purpose and digital-signal processing processors are High performance VLSI integer
adders as they are employed in the design of Arithmetic-Logic Units, in floating-point arithmetic data paths and
in address generation units. The performance parameters for any adder are area, speed and delay. By using
Square Root Carry Select Adder (SQRT CSLA), speed can be achieved. In designing new architecture, the
Tradeoff between those parameters plays the major role. We can reduce area by using Zero Finding Logic
(ZFC) technique, from the structure of SQRT CSLA. By using the Modified architecture we can reduce area.
We can implement Booth multiplier by using the CSLA and SQRT CSLA with Zero finding logic.
Implementation of Booth multiplier by using CSLA and SQRT CSLA with Zero finding logic is proposed for
better speed applications and efficient area applications.
Keywords: And Or Inverter (AOI); Binary to Excess-one Converter (BEC); Carry Select Adder(CSLA);FPGA
(FieldProgrammable Gate Array); Half Adder (HA); Look up Table (LUT); Ripple Carry Adder(RCA); Square
Root Carry Select Adder(SQRT CSLA); Very Large Scale Integrated Circuits(VLSI); Zero Finding Logic
(ZFC).
I. INTRODUCTION
In Advanced digital processors, Low Power,
Area efficient and high performance VLSI designs
plays an important role . In rapidly growing mobile
industry, for design of digital circuits, not only faster
units are concerned but also smaller area and less
power become major concerns. Reducing area and
power consumption are key factors in mobile
electronics for increasing portability and battery life.
power dissipation is an important design constraint
even in servers and desktop computers. The heart of
computer arithmetic is Addition and the work horse
of a computational circuit is arithmetic unit. They are
the necessary components of a data path, e.g. in
microprocessors or a signal processor. An adder can
be designed in many ways. The Ripple delay is
linearly proportional to N, if there is N-bit RCA.
Thus the RCA gives highest delay of all adders for
large values of N. The Carry Look-Ahead Adder
(CLA) gives fast results but it consumes large area.
Speed of addition is limited by carry in digital adders
that plays a major role in computations. Carry select
adder (CSLA) is used in many computational systems
as it is one of the fastest adders to improve the carry
propagation delay by independently generating
multiple carries and then it selects a carry to generate
the sum. But the area of CSLA increases with the use
of dual RCAs. A CSLA with Binary to Excess-1
Converter (BEC) is designed. It
is used to reduce the area of the CSLA, but the delay
overhead is increasing. An add one circuit can be
used to design a CSLA to further decrease the area
and to keep the delay constant or equal as basic
CSLA.
It proposes the design of 8-bit, 16-bit, 32-bit,
64-bit and 128-bit square root CSLA (SQRT CSLA)
using add one circuit with significant reduction in
area. Using add one circuit, the performance in terms
of area and delay are evaluated for SQRT CSLA and
are compared with the existing SQRT CSLA and
SQRT CSLA using Binary to Execess-1 Converter
(BEC). Using Verilog, the proposed design is
developed and by using ISIM simulator functional
simulation is performed.
By using square root carry select adder
using Zero Finding Logic, we can reduce area and
delay and increase the speed.
Implementation of ALU by using modified Square
Root Carry Select Adder(SQRTCSLA) is proposed
for Low power and area-efficient applications and
for better speed applications. The paper delivers the
design and implementation of 8-Bit ALU by using
modified SQRT CSLA and also compares it with the
design of SQRT CSLA using Zero finding logic in
terms of total number of basic gates. The design entry
is done by using Verilog Hardware Description
Language (HDL) and simulated by using ISIM
Simulator. By using Xilinx ISE 12.1, it is synthesized
and implemented.
RESEARCH ARTICLE OPEN ACCESS
2. P.Pavani Sushma et al. Int. Journal of Engineering Research and Application www.ijera.com
ISSN : 2248-9622, Vol. 7, Issue 4, ( Part -1) April 2017, pp.75-80
www.ijera.com DOI: 10.9790/9622-0704017580 76 | P a g e
II. CARRY SELECT ADDER:
The ripple carry adder consists of many
single bit full-adders in cascaded form. The circuit is
simple and area-efficient architecture. But, each full-
adder can start operation only when the previous
carry-out signal is ready . So, the computation speed
is slow. N bits adder is divided into M parts in the
carry select adder. Here, Each part of adder consists
of two ripple carry adders with Cin=0 and Cin=1,
respectively as shown in fig1. By using the
multiplexer, the correct output result according to the
logic state of carry-in signal can be selected In carry
select adder, the current adder stage does not need to
wait the previous stage’s carry-out signal. So, the
carry-select adder can compute faster. Before the
arrival of carry-in signal, the summation result is
ready. So, the correct computation result can be
obtained only by waiting for one multiplexer delay in
each single bit adder. The carry propagation delay
can be reduced by M times in the carry select adder,
when compared with the carry ripple adder. When
compared with other adders, the carry select adder is
faster and intermediate.
Fig.1 Four-bit carry-select module
Fig 2. 4- Bit carry select adder
III. LINEAR CARRY SELECT ADDER:
By chaining a number of equal length adder
stages, a linear carry select adder can be constructed
as shown in fig 2. We can derive the propagation
delay of the module in worst case.
The propagation delay of the adder is
linearly proportional to N. The block select signal
that selects between the 0 and 1solution still has to
ripple through all stages in the worst case. This is the
reason for the linear behavior.
Fig 3. 16-Bit linear carry select adder
3. P.Pavani Sushma et al. Int. Journal of Engineering Research and Application www.ijera.com
ISSN : 2248-9622, Vol. 7, Issue 4, ( Part -1) April 2017, pp.75-80
www.ijera.com DOI: 10.9790/9622-0704017580 77 | P a g e
IV. SQRT CARRY SELECT ADDER:
The structure of the 16-bit regular SQRT
CSLA is shown in Fig. 3. It has five groups which
consists of different sizes of RCA. it is essential to
locate the critical timing path first, in order to
optimize a design. If we Consider the case of a 16-bit
linear carry-select adder, assume that the full-adder
and multiplexer cells have identical propagation
delays equalto a normalized value of 1 in order to
simplify the discussion the critical path of the adder
ripples through the multiplexer networks of the
subsequent stages can be determined by this analysis.
In the last adder stage, consider the
multiplexer gate. The two carry chains of the block
and the block-multiplexer signal from the previous
stage are the inputs to this multiplexer. between the
arrival times of the signals, a major mismatch can be
observed. Long before the multiplexer signal arrives,
the results of the carry chain are stable. The delay
through both paths must be equilized.
By adding more bits to the subsequent stage
in the adder, this can be achieved by progressively. It
requires more time for the generation of the carry
signals. For example ,the first stage can add 2 bits,
the second has 3, the third contains 4, and so forth.
This type of adder is called square root carry select
adder.
Fig 4. 16 - Bit square root carry select adder
V. SQRT CSLA USING ZERO
FINDING LOGIC
Instead of RCA with Cin=l, this adder uses
add one circuit. if the results for Cin = 0 is known the
result for Cin=l can be found by adding one to the
result for Cin=0. This is the main principle used in
this adder. Thus, the ripple carry adder for Cin=l in a
block can be replaced by an Add one circuit. The
area of SQRT CSLA can be further reduced with an
efficient design of an add one circuit for designing
add one circuit, Complement scheme is used. The
Complement scheme states that by adding one is just
inverting each So bit starting from the least
significant bit until the first zero is found. using an
add one circuit instead of a RCA with Cin=1, the 16-
bit SQRT CSLA is designed as shown in fig. 4
4. P.Pavani Sushma et al. Int. Journal of Engineering Research and Application www.ijera.com
ISSN : 2248-9622, Vol. 7, Issue 4, ( Part -1) April 2017, pp.75-80
www.ijera.com DOI: 10.9790/9622-0704017580 78 | P a g e
The complex logics can be alternatively
implemented usingCPL (complementary pass
transistor logic). CPL is extremely fast and efficient.
Some of the examples of CPL circuits are shown in
figure 5.
Fig5.16-Bit SQRT CSLA with ZFC circuit.
Here, in this architecture, it consists of five
carry select stages (CSS). only adders are present in
first CSS and the remaining stages consist of adders,
add one circuit, first zero finding circuit and
multiplexers. Mirror adders are the adders that are
used in the construction of RCAs. Until it doesn’t
find zero in the input number, the first zero finding
circuit generates 0. After finding the 0 in the input
number it generates 1. Nmos and Pmos chain is the
first zero finding circuit. A multiplexer based on add
one circuit is proposed. In order to choose in between
sum and complement of sum, a multiplexer is needed
for each bit.
VI. BOOTH’S MULTIPLIER USING
CSLA:
Booth’s multiplier algorithm is impelemented by
using carry select adder. Here , the area and delay can
be reduced.
VII. BOOTH’S MULTIPLIER USING
SQRT CSLA WITH ZERO FINDING
LOGIC:
Booth's multiplication algorithm is
multiplies two signed binary numbers in two's
complement notation. It is a multiplication algorithm.
by repeatedly adding (with ordinary unsigned binary
addition) one of two predetermined values A and S to
a product P, and then by performing a
rightward arithmetic shift on P, Booth's algorithm
can be implemented. Let us consider that
m and r are the multiplicand and multiplier,
5. P.Pavani Sushma et al. Int. Journal of Engineering Research and Application www.ijera.com
ISSN : 2248-9622, Vol. 7, Issue 4, ( Part -1) April 2017, pp.75-80
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respectively; and let the number of bits in m and r
are represented by x and y respectively.
The rules to implement the Booth’s multiplier are:
1. The initial value is represented by P. Determine
the values of A and S. The length should be equal
to (x + y + 1) to all of these numbers.
a. A: most significant (leftmost) bits must be filled
with the value of m. remaining (y + 1) bits must
be filled with zeros.
b. S: The most significant bits must be filled with
the value of (−m) in the two's complement
notation. The remaining (y + 1) bits must be
filled with zeros.
c. P: The most significant bits of x must be filled
with zeros. Append the value of r to the right of
this value. The least significant (rightmost) bit
must be filled with a zero.
2. Now, the two least significant (rightmost) bits
of P must be determined.
a. If the two least significant (rightmost) bits are
01, then we need to find the value of P + A. Any
overflow can be Ignored.
b. If the two least significant (rightmost) bits are
10, then we need to find the value of P + S. Any
overflow can be Ignored.
c. If the two least significant (rightmost) bits are
00, do not perform any addition or subtraction
operation. We can use the value of P directly in
the next step.
d. If the two least significant (rightmost) bits are
11, do not perform any addition or subtraction
operation. We can use the value of P directly in
the next step.
3. Shift the value that was obtained in the 2nd step
arithmetically to the right by a single place.
Now, Let P be equal to this new value.
4. Repeat the steps of 2 and 3 until they have been
done y times.
5. Now, the least significant (rightmost) bit from P
must be Dropped. This is the product value
of m and r.
Now, replace the Arithmetic logical unit adder
with the SQRT CSLA Zero finding logic. By
replacing the Arithmetic logical unit with SQRT
CSLA Zero finding logic, we are going to reduce
the number of gates used in the implementation
of Booth’s multiplier.
VIII. CONCLUSION
By the implementation of Booth’s
Multiplier using Square root carry select adder with
Zero Finding Logic, we can reduce the number of
gates that are used in the design implementation of
Booth’s Multiplier. We can also reduce the area and
delay as the number of gates decreases in Booth’s
Multiplier using Square root carry select adder with
Zero Finding Logic when compared with Booth’s
Multiplier using carry select adder.
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www.ijera.com DOI: 10.9790/9622-0704017580 80 | P a g e
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