This document describes the design of a 1.8V operational amplifier in 180nm CMOS technology intended to compete with the μA741 model. A two-stage amplifier topology is proposed using a differential input stage followed by an inverting output stage. The input stage employs a PMOS differential pair with cascoded MOSFETs to increase gain, while a Miller compensation capacitor is used between stages for stability. The design aims to meet specifications for gain, bandwidth, output resistance, slew rate, voltage swing, supply voltage, and common mode rejection ratio similar to the μA741 model operational amplifier.

1. Design of 1.8V μA741­type Operational
Amplifier in 180nm CMOS
EECE 5698­ ST: Design of Analog CMOS Integrated
Circuits
Brandon Aston
Ran Tao
Utsav Khandelwal
Date: December, 05, 2014

2. Table of Contents
Abstract
Objective
Target Specifications
Introduction
Features
Specifications/Design Requirements
Applications of the Op amp
Ideal Operation Amplifier
Two Stage Op Amp
Proposed Solution
Simulation Results
Summary
References
Appendix

3. Abstract
This project presents a CMOS operational transconductance amplifier meant to compete
with the μA741 model operational amplifier. The amplifier is designed with a supply voltage of
1.8 V using the 180nm design kit in cadence. A cascode architecture is utilized in order to
provide adequate gain for the first stage, while a miller feedback capacitor maintains stability of
a second stage inverting amplifier.
Objective
The main goal of this project is to build an amplifier which should be similar to the
specifications of μA741 Op Amp. The amplifier should be stable and have a low frequency gain
of at least 100 dB . The simulation has to be performed on the amplifier when it is connected as a
unity gain buffer driving a 20pF load capacitor.
Target Specifications
Low Frequency Gain
>100 dB
Gain Bandwidth Product
1 MHz
Output Resistance <100 ohms
Slew Rate >0.5 μ V/s with load
Output Voltage Swing >800 mV
Supply Voltage
<1.8 V
CMRR
70 dB minimum, 90dB typical (For UA 741)
Load Capacitor
20pF
Input Signal Frequency
100KHz
Input Signal Amplitude 100mV

4. Introduction
The μA741 is constructed on a silicon chip and is a high performance monolithic op amp.
It is perhaps one of the most versatile integrated circuits available in the market.
Operational Amplifiers are a fundamental component of modern electronics. They have
various applications in many different circuits, and see primary usage in signal conditioning
circuits. Configurations such as the inverting, non­inverting, summing and differential amplifiers
enable the realization of simple conditioning circuits, and vastly reduce the complexity of
otherwise complex tasks. The instrumentation amplifier is another useful implementation of
operational amplifiers, commonly used for measurement and test. By including buffered inputs,
and end user does not have to worry about impedance matching a unit under test, which leads to
more simplified interface circuitry.
At it's very core, the operational amplifier is a macro model for a much more complex
system. By masking the internal complexity of the system and conforming to known standards
for this type of device, end users can utilize operational amplifiers as a near drop­in solution. The
ideal operational amplifier exhibits zero output impedance, infinite input impedance, infinite
voltage gain, infinite bandwidth, and zero input offset voltage. Although exact realization of
these specifications is not possible, many modern devices push the boundary of these
specifications, creating devices which behave in a very predictable and stable manner.

5.
Features of the Op­Amp
● Offset Voltage null Capability
● Short Circuit and Overload Protection
● Low Power Consumption
● Large Common Mode and Differential Voltage Ranges
● No Latch­Up
● No Frequency Compensation required
Specifications/Design Requirements
Low Frequency gain
Response of the amplifier to signals at the input, in terms of the ratio of output voltage to input
voltage. In our design we need to have a minimum of 100dB open loop voltage gain.
Gain Bandwidth Product
The Gain Bandwidth product (abbreviated as GBP) of an amplifier is the product of amplifier
bandwidth and unity gain. An ideal Op amp is assumed to have an infinite bandwidth, as it has
an infinite frequency response which can amplify a signal from DC to highest AC frequencies.
With real op amps, bandwidth is limited by the gain bandwidth product.
GBP = gain * bandwidth
GBP= 1M Hz (requirement)
Output Resistance
Output resistance is defined as the equivalent resistance that is measured between the output
terminal and ground. According to the required specifications we should have less than 100
ohms as an output resistance.
Slew rate:
Slew rate is defined as the maximum rate of change of output voltage per unit time, and is
expressed in volts per microseconds. It is one of the most important parameters for selecting op
amps for high frequencies. As our requirement for slew rate is very small, it is not suitable for
high frequency applications, such as oscillators, comparators, or filters.

6. Slew Rate = dVO / dt
Output voltage swing
The op amp voltage swing value will not be greater than the supply voltage. Practically, it is the
range that shows the value of positive and negative saturation voltages of the op amp.
Supply Voltage
The value of supply voltage should be less than 1.8 Volts.
Common Mode rejection ratio
CMRR is the ratio of differential voltage gain to the common mode voltage gain. If there is
proper matching between the two input terminals, the CMRR will be large. For the modern 741
amplifier the minimum value is 70 dB, and the typical value is 90 dB.
CMRR = AD / ACM
where AD is differential voltage gain, ACM is common mode voltage gain.
Applications of the Op amp:
● Simple Electrocardiogram Amplification – Uses differential amplifier to cancel common
mode signal and amplify differential mode signal.
● Piezoelectric Transducer­ Used to measure force, pressure, acceleration
● PID Controller
● Summing amplifier
● Voltage follower
● Integrator
● Active filter
● Function generator

7.
Ideal Operational Amplifier
The ideal op amp is a three terminal circuit element that is modeled as a
voltage­controlled voltage source. Op amp’s output voltage is a gain multiplied by its input
voltage. The input voltage is the difference voltage between the two input terminals. The output
voltage is measured with respect to the circuit ground node. The model equation for the output
voltage is
Vo = A (V+ − V−)
where A is the voltage gain, V+ is the voltage at the non­inverting input, and V− is the voltage at
the inverting input. The circuit symbol for the ideal op amp and controlled source model of the
ideal op amp is shown.
Circuit Symbol Controlled Source model
Equivalent Circuit of an Ideal Operational Amplifier

8. This project proposes an alternative solution to the classic bipolar junction transistor
implementation of a μA741 operational amplifier.
Characteristics of an Ideal op Amp:
● The input impedance is infinite ­ i.e. no current overflows into either input of the op­amp.
● The output impedance is zero ­ i.e. the op­amp can drive any load impedance to any
voltage.
● The open­loop gain (A) is infinite.
● The bandwidth is infinite.
● The output voltage is zero when the input voltage difference is zero.
● Infinite Common Mode Rejection Ratio (CMRR)
Two Golden Rules:
● No current flows into the input pins (i.e. infinite input impedance)
● The output tries to adjust and bring the input pins to the same voltage
Basic Outputs of Op Amp Design:
● The topology
● The dc currents
● The W and L values of transistors
● The values of components

9.
Basic Outputs of Operation Amplifier
Two Stage Op Amp
If pure telescopic, it will suffer from low output swing and medium gain. If folded, it will have
medium gain and medium output swing. For gain boost, medium output swing and better gain
than folded. Multi stage has high gain as well as high high output swing. So, Multi Stage
Topology seems more suitable for our design. In designing an op­amp, numerous electrical
characteristics, e.g., DC gain, gain­band width, slew rate, common­mode range, output swing,
offset, all have to be taken into consideration [1].
In the two stage op amp, first stage provides the gain and the consecutive second stage provides
the large swings. The first stage incorporates various amplifier topologies, but the second stage is
typically configured as a simple common­ source stage to allow maximum output swings.
Furthermore,since op­amps are designed to be operated with negative­feedback connection,
frequency compensation is necessary for closed­loop stability. The simplest frequency
compensation technique employs the Miller effect by connecting a compensation capacitor
across the high­gain stage [2].

10. This op­amp architecture has many advantages: high open­loop voltage gain, high output swing,
large common­mode input range, only one frequency compensation capacitor, and a small
number of transistors. This op­amp is a widely used general purpose op­amp; it finds
applications for example in switched capacitor filters, analog to digital converters, and sensing
circuits [3]. But the disadvantage of multi stage topology is the stability if it has more than two
op amps but we are designing for Two stage.
Proposed Solution and Design
As seen in the table below [4], the various operational amplifier topologies have their
strengths and weaknesses.
Based on the specifications given in our project assignment, we have chosen to go with a
two stage topology, as both the gain and output swing requirements are attainable. Considering
the medium power consumption and low noise performance, the chosen topology makes a
suitable fit for our desired goals. Many attempts were made at addressing proper gain

11. requirements, including altered topology and a gain­boosting transistor. The schematics and brief
discussion is provided in the appendix. In the end, we settled on a two stage topology consisting
of a differential input and a current source used as an inverting amplifier for the output stage.
The input stage is a PMOS differential pair coupled with cascoded MOSFETS in order to
increase gain. A feedback coupling capacitor connects to the output inverting amplifier stage,
and increases functional performance. The coupling capacitor takes advantage of the miller
effect by shifting the systems’ low frequency pole to a higher frequency, thus improving the 3dB
compression point.
Although there is a requirement for minimal output impedance, we did not include an
output buffer due to simulation issues. As a result, the output impedance of the circuit is fairly
high. The final schematic was realized in a paper discussing low voltage operational amplifier
design [5], and is presented as our simulation model in the following figure:
Proposed Architecture

12.
Using equations found in both [4] and [5], and using the low voltage op amp paper as a basis for
redesign, a suitable solution has been realized. Following the presented equations from [5]:
We can observe that the transconductance of the input PMOS transistor, as well as the
resistance of the cascode load dominate the gain of the first stage. The load resistance in the
cascode is proportional to the transconductance and the drain­source resistance of the transistors.
Further, the gain of the inverting amplifier stage is directly influenced by the output resistance of
the second stage, as well as the transconductance of the driving transistor. During the design
process it was noted that the transistor dimension and bias currents would directly affect the
transconductance values, thus influencing our gain. This relation is given by:
As the bias current increases we can theoretically boost our gain, at the cost of power
consumption and potential stability. The low power operational amplifier presents an equation
for the gain bandwidth product in relation to the stability capacitor and the transconductance, as
well as an equation to calculate the slew rate. During the design process these equations were
kept in mind, and are given as follows:
It can be seen by the gain bandwidth product equation that by decreasing the size of the
coupling capacitor we achieve a larger gain bandwidth product. This translates to a larger 3dB
roll­off frequency, and thus the minimal value for capacitance was used. Using the gpdk180
CMOS library in cadence, we’ve implemented this capacitor as a mimcap model with a
capacitance of 17.6 pF. Additionally, it can be seen that the slew rate is influenced by the
coupling capacitor and the bias current. Using these two equations we can predict the influence
of altering the coupling capacitors size.
Additional design equations have been presented in [5], but are omitted for brevity. The
final design was based on the initial transistor sizing found in the low power, large swing

13. operational amplifier paper. The power supply is lower in the paper, thus our bias voltages and
operation current would all change. Our first design goal was to implement the proposed design
using a 1.8V single rail supply with the initial design values in place. A large challenge in this
process was finding the proper bias voltages and current. Through a series of parametric sweeps,
we optimized biasing such that our gain was maximized. Upon measuring our other
specifications, it was found that larger gain led to a lower 3dB cutoff frequency, and thus trade
offs had to be made to find an optimal operating point. In order to correct for the decreased
frequency response, we minimized the coupling capacitance value. Our next steps were to alter
the transconductance of the output inverting amplifier, in an attempt to further increase our gain.
By increasing the channel width of transistor 12 we were able to boost our gain without taking
too much of a loss in our frequency response. After re­biasing the amplifier to a new operating
point, we settled on the simulation results given in the following section. The finalized
dimensions and parameters are:
Once the design process was completed, a layout of the gpdk180 components was
performed. The layout is as follows, with screenshots of supporting verification. Parasitic
extraction was performed before simulations were carried out. The total layout area was
1061.17315 µm2

14.
Layout of Proposed Architecture

15.
Simulation Results
The schematic was simulated using the testbench schematic given below. The pre layout
simulation was tested in both open and closed loop configurations, while the post layout was

16. tested only for gian, 3dB cutoff, and transient response, due to simulation netlisting issues. The
results are presented and discussed below.
Testbench Schematic
Pre­Layout Results:
1. Open Loop Simulation
Gain

17. 3dB Frequency
DC Operating Point

18. Transient Max Transient Min
Gain Bandwidth Product Output Impedance

19. 2. Closed Loop Simulation
DC Operating Point
HD2 HD3

20. 3. Post Layout Simulation
Gain/3dB Cutoff Transient

21. Comaparison Results
Specifications/Parameter (Open
Loop)
Actual Design UA 741 Op Amp
Low Frequency Gain 76.68436 dB > 100 dB
3dB Frequency 506.5934 kHz
Gain Bandwidth Product (GBP) 233.9106 MHz 1 MHz
Output Resistance 12.4 kΩ < 100 Ω
Slew Rate 53.7 V/us >0.5 V/us
Output Voltage Swing 1.6886 V > 800 mW
Supply Voltage 1.8 V
CMRR
simulation issue > 70 dB, typical: 90 dB
Load Capacitor 20pF
Frequency 100KHz 100 KHz
Amplitude 100mV 100 mV
Power Dissipation 1.933 mW <85 mW, typical: 50 mW
Minimum Output Voltage 1.765781 V
Maximum Output Voltage 76.44189 mV
Parameters (Closed Loop: Unity
Gain Buffer Connection)
Minimum Output Voltage 900 mV
Maximum Output Voltage 1.0999 V
Output Impedance (low
frequency)
796.7883 mΩ
HD2 in dB 6.75246 dB
HD3 in dB 13.5049 dB

22. Summary
A design for a low power 1.8V CMOS operational amplifier is presented. Various design
topologies are attempted, finalizing with a two stage amplifier implementing a cascode on the
input. Several design decisions are explained, and trade offs are discusses. The pre and post
layout simulation results are presented and compared in tabulated format with a modern 741
operational amplifier, the specifications presented in the project prompt, and specifications from
a research paper. Despite not meeting the given gain requirements, performance post simulation
is acceptable given the project prompt.
References
[1] P.R. Gray, P.J. Hurst, S.H. Lewis and R.G. Meyer, “Analysis and Design of Analog
Integrated Circuits”, Forth Edition. John Wiley &Sons, Inc., 2001.
[2] B. Ahuja, “An improved frequency compensation technique for CMOS operational
amplifiers”, IEEE J. Solid­State Circuits, vol. SC­18, pp. 629­633, Dec, 1983.
[3] Anshu Gupta, D.K. Mishra and R. Khatri, “A Two Stage and Three Stage CMOS OPAMP
with Fast Settling, High DC Gain and Low Power Designed in 180nmTechnology” International
Conference on Computer Information Systems and Industrial Management Applications
(CISIM) pp 448­453, 2010.
[4] Razavi, Behzad, “Design of Analog CMOS Integrated Circuits”, First Edition. McGraw­Hill,
2000.
[5] Ehsan Kargaran, et. al. “A 1.5v High Swing Ultra­Low Power Two Stage CMOS OP­AMP in
0.18 um Technology”. 2nd International Conference on Mechanical and Electronics Engineering.
Volume 1. pp 68­71, 2010

23.
Appendix
Before stepping into our final design, we made an attempt on two stage OTA design. The
topology is shown below:
With proper bias conditions, this two stage amplifier can get close to 70 dB in open loop
condition, but lose its stability as the 3 dB frequency and gain bandwidth products are extremely
low compared to the gain­boosting fully differential amplifier. If we decrease the bias current as
a stability compensation, the gain response will decrease dramatically (around 40 dB). Therefore,
it is undesirable for our specific design.