In this paper we have provided a method for designing a Two Stage CMOS Operational Amplifier which operates at 1.8V power supply using Cadence Virtuoso 45nm CMOS technology. Further, designing the two stage op-amp for the same power supply using Cadence Virtuoso 180nm CMOS Technology, keeping the slew rate of the op-amp same as that 45nm technology. The trade-off curves are computed between various characteristics such as Gain, Phase Margin,GBW,3db Gain etc. and the results obtained for 45n CMOS Technology is compared with those obtained for 180nm CMOS Technology It has been demonstrated that on lowering the technology and keeping the slew rate constant, the Power dissipation decreases.
Concurrent Quad-band Low Noise Amplifier (QB-LNA) using Multisection Impedanc...IJECEIAES
A quad-band low noise amplifier (QB-LNA) based on multisection impedance transformer designed and evaluated in this research. As a novelty, a multisection impedance transformer was used to produce QB-LNA. A multisection impedance transformer is used as input and output impedance matching because it has higher stability, large Q factor, and low noise than lumpedcomponent.The QB-LNA was designed on FR4 microstrip substrate with r= 4.4, thickness h=1.6 mm, and tan = 0.026. The proposed QB-LNA was designed and analyzed by Advanced Design System (ADS).The simulation has shown that QB-LNA achieves gain (S ) of 22.91 dB, 16.5 dB, 11.18 dB, and 7.25 dB at 0.92 GHz, 1.84 GHz, 2.61 GHz, and 3.54 GHz, respectively.The QB-LNA obtainreturn loss (S 11 21 ) of -21.28 dB, -31.87 dB, 28.08 dB, and -30.85 dB at 0.92 GHz, 1.84 GHz, 2.61 GHz, and 3.54 GHz, respectively. It also achieves a Noise figure (nf) of 2.35 dB, 2.13 dB, 2.56 dB, and 3.55 dB at 0.92 GHz, 1.84 GHz, 2.61 GHz, and 3.54 GHz, respectively. This research also has shown that the Figure of merit (FoM) of the proposed QB-LNA is higher than that of another multiband LNA.
Optimization of Digitally Controlled Oscillator with Low Poweriosrjce
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels
PARASITIC-AWARE FULL PHYSICAL CHIP DESIGN OF LNA RFIC AT 2.45GHZ USING IBM 13...Ilango Jeyasubramanian
• Analyzed and designed a single stage cascoded LNA with Q-based calculation for desired input matching, output matching, power gain, IIP3 and Noise figure, including all the parasitics in the on-chip and off-chip components using SpectreRF simulations.
• Synthesized the LNA layout for on-chip components with spiral inductor, MOS capacitor, MIM capacitor and Bond-pads with ESD protections.
• Our LNA exhibited a noise figure of 1.23dB, linear gain of 18.54 dB, IIP3 of -4.60dbm, S11 of -31.11db, S22 of -24.91db with the operating range between 2.4-2.5GHZ along with 10% variation tolerance.
A low dropout (LDO) voltage regulator with high power supply rejection ratio (PSRR) and low
temperature coefficient (TC) is presented in this paper. Large 1μF off-chip load capacitor is used to
achieve the high PSRR. However, this decreases the gain and pushes the LDO’s output pole to lower
frequency causing the circuit to become unstable. The proposed LDO uses rail-to-rail folded cascode
amplifier to compensate the gain and stability problems. 2nd order curvature characteristic is used in
bandgap voltage reference circuit that is applied at the input of the amplifier to minimize the TC.
The characteristic is achieved by implementing MOSFET transistors operate in weak and strong
inversions. The LDO is designed using 0.18 μm CMOS technology and achieves a constant 1.8 V output
voltage for input voltages from 3.2 V to 5 V and load current up to a 128mA at temperature between -40 °C
to 125 °C. The proposed LDO is targeted for RF application which has stringent requirement on noise
rejection over a broad range of frequency.
The paper introduces a multi-pass loop voltage controlled ring oscillator. The proposed structure uses cross-coupled PMOS transistors and replica bias with coarse/fine control signal. The design implemented in TSMC 90 nm CMOS technology, 0.9V power supply with frequency tuning range 481MHz to 4.08GHz and -94.17dBc/Hz at 1MHz offset from 4.08GHz with 26.15mW power consumption.
Concurrent Quad-band Low Noise Amplifier (QB-LNA) using Multisection Impedanc...IJECEIAES
A quad-band low noise amplifier (QB-LNA) based on multisection impedance transformer designed and evaluated in this research. As a novelty, a multisection impedance transformer was used to produce QB-LNA. A multisection impedance transformer is used as input and output impedance matching because it has higher stability, large Q factor, and low noise than lumpedcomponent.The QB-LNA was designed on FR4 microstrip substrate with r= 4.4, thickness h=1.6 mm, and tan = 0.026. The proposed QB-LNA was designed and analyzed by Advanced Design System (ADS).The simulation has shown that QB-LNA achieves gain (S ) of 22.91 dB, 16.5 dB, 11.18 dB, and 7.25 dB at 0.92 GHz, 1.84 GHz, 2.61 GHz, and 3.54 GHz, respectively.The QB-LNA obtainreturn loss (S 11 21 ) of -21.28 dB, -31.87 dB, 28.08 dB, and -30.85 dB at 0.92 GHz, 1.84 GHz, 2.61 GHz, and 3.54 GHz, respectively. It also achieves a Noise figure (nf) of 2.35 dB, 2.13 dB, 2.56 dB, and 3.55 dB at 0.92 GHz, 1.84 GHz, 2.61 GHz, and 3.54 GHz, respectively. This research also has shown that the Figure of merit (FoM) of the proposed QB-LNA is higher than that of another multiband LNA.
Optimization of Digitally Controlled Oscillator with Low Poweriosrjce
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels
PARASITIC-AWARE FULL PHYSICAL CHIP DESIGN OF LNA RFIC AT 2.45GHZ USING IBM 13...Ilango Jeyasubramanian
• Analyzed and designed a single stage cascoded LNA with Q-based calculation for desired input matching, output matching, power gain, IIP3 and Noise figure, including all the parasitics in the on-chip and off-chip components using SpectreRF simulations.
• Synthesized the LNA layout for on-chip components with spiral inductor, MOS capacitor, MIM capacitor and Bond-pads with ESD protections.
• Our LNA exhibited a noise figure of 1.23dB, linear gain of 18.54 dB, IIP3 of -4.60dbm, S11 of -31.11db, S22 of -24.91db with the operating range between 2.4-2.5GHZ along with 10% variation tolerance.
A low dropout (LDO) voltage regulator with high power supply rejection ratio (PSRR) and low
temperature coefficient (TC) is presented in this paper. Large 1μF off-chip load capacitor is used to
achieve the high PSRR. However, this decreases the gain and pushes the LDO’s output pole to lower
frequency causing the circuit to become unstable. The proposed LDO uses rail-to-rail folded cascode
amplifier to compensate the gain and stability problems. 2nd order curvature characteristic is used in
bandgap voltage reference circuit that is applied at the input of the amplifier to minimize the TC.
The characteristic is achieved by implementing MOSFET transistors operate in weak and strong
inversions. The LDO is designed using 0.18 μm CMOS technology and achieves a constant 1.8 V output
voltage for input voltages from 3.2 V to 5 V and load current up to a 128mA at temperature between -40 °C
to 125 °C. The proposed LDO is targeted for RF application which has stringent requirement on noise
rejection over a broad range of frequency.
The paper introduces a multi-pass loop voltage controlled ring oscillator. The proposed structure uses cross-coupled PMOS transistors and replica bias with coarse/fine control signal. The design implemented in TSMC 90 nm CMOS technology, 0.9V power supply with frequency tuning range 481MHz to 4.08GHz and -94.17dBc/Hz at 1MHz offset from 4.08GHz with 26.15mW power consumption.
PARASITICS REDUCTION FOR RFIC CMOS LAYOUT AND IIP3 VS Q-BASED DESIGN ANALYSI...Ilango Jeyasubramanian
• Measured parasitic resistance and capacitance of two cascoded NMOS layout in LNA. Reduced down the parasitic resistance to about 1 ohm using a multi-fingered and multi-contacted layout.
• Analyzed the Q-based tuning of RFIC LNA by adding an ideal capacitor between the gate and source of CS stage of cascoded LNA and the corresponding variation of linearity using Cadence SpectreRF simulations.
ACCURATE Q-PREDICTION FOR RFIC SPIRAL INDUCTORS USING THE 3DB BANDWIDTHIlango Jeyasubramanian
• Analyzed and extracted the inductance, parasitic resistance and capacitance for a spiral inductor layout in IBM 130nm technology using MATLAB code.
• Analyzed the improved Q-prediction accuracy by measuring Q factor as Wo/dW at different resonant frequencies from the inductor self-resonant frequency by numerically adding a capacitor (Cnum ) in parallel to the measured Y11 data of spiral inductor equivalent model using MATLAB codes.
• Measurement from new method showed significant Q-value to be useful enough all the way up to the self-resonance frequency at 1-5Ghz when compared to unreasonable results from conventional [-Imag(Y11)/ Re(Y11)] value.
•Designed a two stage OPAMP with a current mirror amplifier and a second CS stage along with miller compensation to provide sufficient Phase margin for stability.The circuit is also provided with temperature independent self-biased startup circuit.
•Our OPAMP exhibited a gain of 82.74dB, OVSR of 1.57V, Slew rate of 9.79V/us, Phase margin of 60 deg, GBW of 18.6 MHz, CMRR of 88.473dB, Power dissipation of 0.22mW with a 1.8V power supply.
Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Op...IJERA Editor
This paper presents a low power high performance and higher sampling speed sample and hold circuit. The
proposed circuit is designed at 180 nm technology and has high linearity. The circuit can be used for the ADC
frontend applications and supports double sampling architecture. The proposed sample and hold circuit has
common mode range beyond rail to rail and uses two differential pairs transistor stages connected in parallel as
its input stage.
PARASITICS REDUCTION FOR RFIC CMOS LAYOUT AND IIP3 VS Q-BASED DESIGN ANALYSI...Ilango Jeyasubramanian
• Measured parasitic resistance and capacitance of two cascoded NMOS layout in LNA. Reduced down the parasitic resistance to about 1 ohm using a multi-fingered and multi-contacted layout.
• Analyzed the Q-based tuning of RFIC LNA by adding an ideal capacitor between the gate and source of CS stage of cascoded LNA and the corresponding variation of linearity using Cadence SpectreRF simulations.
ACCURATE Q-PREDICTION FOR RFIC SPIRAL INDUCTORS USING THE 3DB BANDWIDTHIlango Jeyasubramanian
• Analyzed and extracted the inductance, parasitic resistance and capacitance for a spiral inductor layout in IBM 130nm technology using MATLAB code.
• Analyzed the improved Q-prediction accuracy by measuring Q factor as Wo/dW at different resonant frequencies from the inductor self-resonant frequency by numerically adding a capacitor (Cnum ) in parallel to the measured Y11 data of spiral inductor equivalent model using MATLAB codes.
• Measurement from new method showed significant Q-value to be useful enough all the way up to the self-resonance frequency at 1-5Ghz when compared to unreasonable results from conventional [-Imag(Y11)/ Re(Y11)] value.
•Designed a two stage OPAMP with a current mirror amplifier and a second CS stage along with miller compensation to provide sufficient Phase margin for stability.The circuit is also provided with temperature independent self-biased startup circuit.
•Our OPAMP exhibited a gain of 82.74dB, OVSR of 1.57V, Slew rate of 9.79V/us, Phase margin of 60 deg, GBW of 18.6 MHz, CMRR of 88.473dB, Power dissipation of 0.22mW with a 1.8V power supply.
Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Op...IJERA Editor
This paper presents a low power high performance and higher sampling speed sample and hold circuit. The
proposed circuit is designed at 180 nm technology and has high linearity. The circuit can be used for the ADC
frontend applications and supports double sampling architecture. The proposed sample and hold circuit has
common mode range beyond rail to rail and uses two differential pairs transistor stages connected in parallel as
its input stage.
In this paper Low power low voltage CMOS analog multiplier circuit is proposed. It is based on flipped voltage
follower. It consists of four voltage adders and a multiplier core. The circuit is analyzed and designed in 0.18um
CMOS process model and simulation results have shown that, under single 0.9V supply voltage, and it
consumes only 31.8μW quiescent power and 110MHZ bandwidth.
Design and Implementation of Schmitt Trigger using Operational AmplifierIJERA Editor
A Schmitt trigger is an electronic circuit, a Comparator that is used to detect whether a voltage has crossed over a given reference level. It has two stable states and is very useful as signal conditioning device. When an input waveform in the form of sinusoidal waveform, triangular waveform, or any other periodic waveform is given, the Schmitt trigger will produce a Rectangular or square output waveform that has sharp leading and trailing edges. Such fast rise and fall times are desirable for all digital circuits. The state of the art presented in the paper is the design and implementation of Schmitt trigger using operational amplifier µA-741, generating a Rectangular waveform. Furthermore, the Schmitt trigger exhibiting hysteresis is also presented in the paper. Due to the phenomenon of hysteresis, the output transition from HIGH to LOW and LOW to HIGH will take place at various thresholds.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Gain improvement of two stage opamp through body bias in 45nm cmos technologyeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Designed a differential input and single ended output high gain (>= 85 dB) operational amplifier using CMOS 0.35um technology using a single independent current source. The amplifier was also designed to achieve a CMRR (>= 80dB), Average Slew Rate (>= 15 V/us), UGF (>= 15 MHz) & Output Voltage Swing ( >= 1.4V). The maximum power dissipation through the complete circuit including the current source branch was limited to 0.3 mW.
Design of Low Voltage Low Power CMOS OP-AMPIJERA Editor
Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed
mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS
technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates
at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain
frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin
of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.
Design and Development of Gate Signal for 36 Volt 1000Hz Three Phase InverterIJMER
The sinusoidal PWM gating signals generation is most popular PWM method, which reduce
harmonic reduction in output. SPWM can be generated by FPGA, micro controller and micro processor but
this kind of device needs programming and coding hence avoided in using power system of aircraft. This
paper present an experiment using SPWM method to generate 1000 Hz gating signals suitable for 36 Volt ,
1000 Hz, 3 phase, three wire supply. Discrete components design approach is chosen to provide noise
immunity at higher amplitude level of signal and a large flexibility to adjust and process various operating
parameters of signals. The circuit is proved with commercial components however MIL version of
components can be easily incorporated in design in later stage
Design of a current Mode Sample and Hold Circuit at sampling rate of 150 MS/sIJERA Editor
A current mode sample and hold circuit is presented in this paper at 180nm technology. The major concerns of
VLSI are area, power, delay and speed. Hence, we have used a MOSFET in triode region in the proposed
architecture for voltage to current conversion instead of a resistor being used in previously proposed circuit. The
proposed circuit achieves high sampling frequency and with more accuracy than the previous one. The
performance of the proposed circuit is depicted in the form of simulation results.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
Planning Of Procurement o different goods and services
Comparative Study of CMOS Op-Amp In 45nm And 180 Nm Technology
1. Mehul Garg et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 7( Version 1), July 2014, pp.64-67
www.ijera.com 64 | P a g e
Comparative Study of CMOS Op-Amp In 45nm And 180 Nm Technology Siddharth1, Mehul Garg2, Aditya Gahlaut3 Jaypee Institute of Information Technology, Noida, India ABSTRACT In this paper we have provided a method for designing a Two Stage CMOS Operational Amplifier which operates at 1.8V power supply using Cadence Virtuoso 45nm CMOS technology. Further, designing the two stage op-amp for the same power supply using Cadence Virtuoso 180nm CMOS Technology, keeping the slew rate of the op-amp same as that 45nm technology. The trade-off curves are computed between various characteristics such as Gain, Phase Margin,GBW,3db Gain etc. and the results obtained for 45n CMOS Technology is compared with those obtained for 180nm CMOS Technology It has been demonstrated that on lowering the technology and keeping the slew rate constant, the Power dissipation decreases..
Keywords - Op-Amp (Operational Amplifier), CMOS (Complementary Metal Oxide Semiconductor Field Effect Transistor), Slew Rate, Two-Stage, Cadence, 45nm, 180nm, Power Dissipation
I. INTRODUCTION
Operational Amplifiers are the basic building block of many analog circuits. They have wide applications in many analog circuit including switched capacitor filters, sigma delta A/D converter, sample and hold amplifiers etc. The basic 2 stage operational amplifier consists of three sections [1] : A.Dual input Differential Amplifier: In Fig. I, the transistors nm0, nm1, pm0 and pm1 form the first stage i.e. differential stage of the operational amplifier.nm0 and nm1 are nmos transistors whose gate acts as the differential input node. Gate of nmos nm0 is the inverting input and the gate of nmos nm1 is the non-inverting input. In this stage current is mirrored from nm0 by pm1 and pm0 and subtracted from the current through nm1.This current mirror topology is used for converting the differential input signal to single ended output signal. B.Bias String: In Fig. I, the bias string block of the op-amp architecture is formed by transistor nm6 and nm7 that supplies a voltage between the gate and source of nm6 and nm4.nm6 and nm7 are diode connected and hence, it ensures that they operate in saturation region. The required biasing of the remaining transistors is controlled by their respective node voltages. C.Output Buffer: The Output buffer, more commonly known as Second Gain Stage, comprises of transistor nm4 and pm4 in Fig. I. It is a common source amplifier which provides an additional gain to the amplifier. The output of the differential input stage acts as the input for this stage. The gain
provided by this stage is the product of trans- conductance of pm4 and the effective load resistance i.e. the output resistance of nm4 and pm4. Figure I: circuit topology
II. DESIGN STRATEGY OF OP-AMP
The values of (w/l) for the transistors were calculated using the following basic equations[1] keeping the slew rate constant and equal to 1600V/μsec Id=(μnCox(w/l)Veff2)/2 (1) transconductance,gm=√(2μnCox(w/l)Id) (2) gm=2Id/Cc (3) Slew Rate,SR=Ibias/Cc (4) ICMR(+)=Vdd-√(Id/βpm0)-Vthpm0(max.)+ Vthnm0(min.) (5) ICMR(-)=Vss-√(Id/βnm0)-Vthnm0(max.)+ Vdsnm6(sat.) (6) Saturation Voltage,Vds=Ids/β (7)
III. CHARACTERISTIC FEATURES OF OP-AMP
OPEN LOOP GAIN :
RESEARCH ARTICLE OPEN ACCESS
2. Mehul Garg et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 7( Version 1), July 2014, pp.64-67
www.ijera.com 65 | P a g e
The ratio of change in output voltage to the change in voltage across the input terminals is known as open loop gain of the op-amp.It is also known as differential mode voltage amplification.[2] COMMON MODE GAIN: The ratio of output voltage to the input voltage when both the terminals of the op-amp are supplied same potential is known as common mode gain of op-amp.It is also known as common-mode voltage amplification.[2] COMMON MODE REJECTION RATIO: The ratio of differential voltage amplification to common-mode voltage amplification is known as common mode rejection ratio (CMRR). Ideally this ratio would be infinite with common mode voltages being totally rejected. [2] SLEW RATE: The rate at which the output changes with respect to the time required for a step change in the input is known as slew rate of the op-amp. It is generally expressed in the units of V/ μsec. [2] INPUT COMMON MODE VOLTAGE RANGE: The range of common-mode input voltage that may cause the operational amplifier to cease functioning properly if the input voltage goes beyond this range is known as input common mode voltage range.[2] UNITY GAIN BANDWIDTH: The range of frequencies within which the open- loop voltage amplification is greater that unity is referred as the unity gain bandwidth of the op-amp.[2] TOTAL POWER DISSIPATION: The total dc power supplied to the device less any power delivered from the device to a load is known as total power dissipation of the op-amp.[2] At no load, PD = VDD * I (8)
IV. SIMULATION RESULTS
A. Test Circuit
Figure II: test circuit
B. Open Loop Gain:
Open Loop gain is the result of the AC Analysis carried out on the circuit with V1(Inverting) connected with a sine wave having DC amplitude of 0V,AC amplitude of 1mV and frequency of 1 KHz and V2(non-inverting) connected to ground. Start Time =1Hz Stop Time = 10 GHz
Figure III: open loop gain in 180 nm
Figure IV: open loop gain in 45nm
C. Unity Gain Bandwidth:
Figure V: unity gain bandwidth in 180nm
3. Mehul Garg et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 7( Version 1), July 2014, pp.64-67
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Figure VI: unity gain bandwidth in 45nm
D. Common Mode Gain:
For the calculation of common mode gain, both Vinverting and Vnon-inverting terminals of the op-amp is connected to the common voltage source of sine wave having DC magnitude of 0V,AC amplitude of 1mV and frequency of 1KHz. AC analysis of the circuit is,then,carried out.
Figure VII: common mode gain in 180nm
Figure VIII: common mode gain in 45nm
E. -3dB Gain Bandwidth Figure IIIX: -3dB gain bandwidth in 180nm
Figure X: -3dB gain bandwidth in 45nm
V. RESULTS
The circuit in both technologies are simulated using Power Supply: Vdd = 1.8V Vss = -1.8V The results obtained after simulation of the circuit are tabulated below: Table 1: Simulation Results
Results
180nm
45nm
Bias Current,Ibias
160uA
80uA
Cc
100fF
50fF
Open Loop Gain,Ad
47.85dB
52.68dB
Phase Margin,PM
63.221o
60.9652o
Unity Gain BW
668.42MHz
2.2232GHz
-3dB Gain BW
898.16MHz
3.1525GHz
Common Mode Gain, Ac
-5.83dB
-6.752dB
CMRR
53.68 dB
59.432 dB
ICMR(+)
1.6V
1.6V
ICMR(-)
0.8V
0.9V
Power Dissipation,Pd
3.5822mW
1.735mW
4. Mehul Garg et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 7( Version 1), July 2014, pp.64-67
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VI. CONCLUSION
As shown in the above results, taking the slew rate and the ICMR values constant, the power consumption of the two stage operational amplifier has decreased. It was also noticed that the gain at 45nm Technology was higher than that of 180nm technology circuit.
ACKNOWLEDGEMENT
We wish to express our heartfelt gratitude to Mrs. Rakhi Tomar (Assistant Professor, JIIT NOIDA) for her constant support and guidance throughout this work. We also wish to thank Ms. Rashi Aggarwal (Lab Technician, JIIT Noida) for her cooperation during the course of this project.
REFERENCES
[1] Amana Yadav, Design of Two-Stage CMOS Op-Amp and Analyze the Effect of Scaling, International Journal of Engineering Research and Applications (IJERA), Vol. 2, Issue 5, September- October 2012, pp.647- 654
[2] Ron Mancini, OPAmps for Everyone, Texas Instruments, August 2002, 11.1-11.22.
[3] Prabhat kumar, Alpana Pandey , Low Power Operational Amplifier, International Journal of Emerging Technologies in Computational and Applied Sciences, June- August, 2013 pp170- 174.
[4] B. Razavi, Design of analog cmos integrated circuits (New York: Mc-Graw-Hill, 2001).
[5] Kang Sung-Mo, Leblebici Yusuf, Cmos digital integrated circuits, analysis and design (Tata McGraw-Hill Edition 2003, Third Edition).
[6] Ing. Ahmad Khateb, Step by step cadence manual and examples schematic,Department of Microelectronics.