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2011 年會-IC封測產業技術發展現況與未來挑戰
- 1. 1 Corporate R&DCorporate R&D June15, 2011June 15, 2011 IC封測產業封測產業封測產業封測產業(技術技術技術技術)發展現況與未來挑戰發展現況與未來挑戰發展現況與未來挑戰發展現況與未來挑戰
- 2. 2 Introduction IC Packaging IndustryMarket Trend and Challenges IC Packaging Technology & Trend Application of ‘Automatic Image based Inspection” in IC packaging industry AOI SAM & Xray TSV 3DIC Metrology Summary OutlineOutline
- 3. Packaging: Protection &Information 3
- 4. 4 1. Mechanical support. 提供可承載IC之形體。 2.Protect die, gold wire. 提供機械強度以保護 IC 內部之晶片、金線。 3. Connect & distribute signal. 提供晶片到系統之間訊號之連結. 4. Insulate moisture, electricity. 隔離外在環境（濕氣、電性干擾）影響，確保 IC 功能。 5. Dissipate & distribute power. 提供優良之散熱（散熱片）。 The Purpose of IC Packaging (& Assembly)The Purpose of IC Packaging (& Assembly)
- 5. 5 WLCSP Multiple substrate/ leadframepackages Wafers Electronics by applications Bumping Wafer Sort Assembly Final Test Drop Ship IDM Fabless Foundry Business ModelBusiness Model
- 6. 6 Introduction IC Packaging IndustryMarket Trend and Challenges IC Packaging Technology & Trend Application of ‘Automatic Image based Inspection” in IC packaging industry AOI SAM & Xray TSV 3DIC Metrology Summary OutlineOutline
- 7. 7 Worldwide Semiconductor RevenueForecastWorldwide Semiconductor Revenue Forecast
- 8.
- 9. IC Package UnitsGrowth Source: Yole 9
- 10. 10 IC Packaging MarketTrend 11.7%11.7% 144 B144 B 210 B210 B Overall IC Packaging Total unitsTotal units 15.7%15.7% Source: Prismark Wireless related IC Packaging FC: driven by volume size (low Z ,<1.0mm)/ elec. performance/ integration (multi- dies) WL: cost driven
- 11. IC 封測產業面臨之挑戰封測產業面臨之挑戰封測產業面臨之挑戰封測產業面臨之挑戰 • ASPdropping as the overall electronics industry • High materials cost ratio in overall cost • Escalating gold/ silver price (gold 400 -> 1,500 USD/ ounce)-> margin killer! • High dependence on foreign materials (recent case of JPN earthquake) • New technology (wafer level- bumping, CSP, TSV) attract upstream IC fab into business (middle end) 11
- 12. 12 Introduction IC Packaging IndustryMarket Trend and Challenges IC Packaging Technology & Trend Application of ‘Automatic Image based Inspection” in IC packaging industry AOI SAM & Xray TSV 3DIC Metrology Summary OutlineOutline
- 13. 13 IC Packaging TechnologyTrendIC Packaging Technology Trend 1980 1990 20102000 IC Packaging Technology 1.5um 0.5um 0.18um 0.04um (40nm) IC fab technology node (Moore’s Law) I. IC interconnect (連接技術連接技術連接技術連接技術) II. Carrier (載板載板載板載板) Wire Bonding (WB銲線銲線銲線銲線)))) Metal Bumping (金屬凸塊)+)+)+)+ RDL - Au, solder (high Pb, Pb free SnAg), Cu II. Package type family DIP, TSOP, QFP QFN… TSV Lead Frames Laminated Substrates + Sn balls (BGA) PBGA, TFBGA… Flip Chip (FC) BGA, FC CSP, WL CSP TSV interposer 3DIC 1 1 Lead Frames 2 4 3 1D 2D
- 14. 14 Cycle time 5days I.I.I.I. 銲線封裝製程銲線封裝製程銲線封裝製程銲線封裝製程_Lead Frame(_Lead Frame(_Lead Frame(_Lead Frame(導線架)))) 晶圓切成晶粒晶圓切成晶粒 產出可用IC產出可用IC 晶片訊號透過載具引到 外部 保護晶片免受破壞 晶片訊號透過載具引到 外部 保護晶片免受破壞 導線架 樹脂 散熱片 金/銅線
- 15.
- 16. 16 III.1 Bumping (凸塊凸塊凸塊凸塊)製程製程製程製程 Cycletime 4 days 乾膜 乾膜 鋁墊 護層 底層金屬UBM 晶圓 光阻 晶圓檢驗晶圓檢驗 底層金屬濺鍍底層金屬濺鍍 光阻成像光阻成像 錫膏印刷錫膏印刷 乾膜成像乾膜成像 底層金屬蝕刻/光阻去除底層金屬蝕刻/光阻去除 包裝包裝 外觀檢驗外觀檢驗 乾膜去除/ 第二次迴銲 乾膜去除/ 第二次迴銲 第一次迴銲第一次迴銲
- 17. 17 III.2 Flip Chip(覆晶覆晶覆晶覆晶)封裝製程封裝製程封裝製程封裝製程 晶圓檢驗晶圓檢驗 割片割片研磨研磨 基板烘烤基板烘烤 上元件 及晶片 上元件 及晶片 點膠點膠 上散熱片上散熱片 印字印字植球植球合檢合檢包裝包裝 Cycle time 5 days
- 18. 18 Package Portfolio I QFPFamily BGA Family VQFP QFP DHS-QFP EDHS-QFP LQFP DHS-LQFP E-PAD LQFP TQFP E-PAD TQFP EBGA PBGA EDHS-BGA MPBGA POPBGA FCBGA EHS-FCBGA MP-FCBGA Terminator FCBGA SOP SOJ VSOP COL- VSOP(2 dies) DDVSOP SO Family TSOP COL-TSOP (4 dies) Balance mold COL-TSOP (8 dies) Un-balance mold
- 19. 19 Package Portfolio II MemoryCardCSP Family LGA S-LGA V/U/W/XTLGA TFBGA S-TFBGA V/U/W/XFBGA COSBGA FCCSP WB-S-FCCSP WLBGA Micro SD SPIL sample SD Mini SD MMC RSMMC MMC Micro MS MS MicroMS Duo XD SiP Module LGA /QFN WB FC die WB die WB S M D Substrate FC die WiFi + BT Module ASIC MI -Y MI- X MI- Z S M D Substrate GPS Module LGA / QFN Substrate FC dieFC S M D Wimax Module LGA FC die Substrate WiFi + BT + FM Radio Module QFN FCQFN NBA1-QFN sFCCSP Enhanced PoP eQFN (CUF) (MUF)(UF only)
- 20. 20 Package Development Directions PBGA EDHS-PBGA EBGA FCBGA MoldedFCBGA Stack Die CSP WB+FC MPBGA POP PIP W/B CSP FCCSP QFN/NBA1 WLBGA FCBGA SiP CSP Larger size, Higher I/O density More dies, Mult-Pkg Small form factor Small form Performance Available 2011~2013 55x55 FCBGA 28 nm FCBGA Fine bump Pitch Larger Die size Larger pkg. size LF FCBGA 1.0 mil WFR 1.0 mil WFR0.4 mm Pkg 0.35 mm pkg MMC/RS MMC/MMC u SD/Mini SD/uSD QFP/LQFP/TQFP/VQFP BGA Memory Card QFP CSPSO TFBGA > 10 die TSV F2F Micro-bump Module IPD MEMS FO-WLP Cu pillar bump FCCSP Exposed die FCCSP eQFN 9 dies TFLGA Production > 10 dies 6 dies TSOP Enhanced PoP eQFN Cu pillar bump FCCSP Micro Bump VCI IPD Exposed Die FCCSP FO-WLP
- 21. 21 4 Carrier bondingCarrier bonding TopTop--diedie SiinterposerSi interposer SubstrateSubstrate TSVTSV Micro BumpMicro Bump RDLRDL C2C bondingC2C bonding UBMUBM CMPCMP Carrier + ThinningCarrier + Thinning TSV 3D-IC Package
- 22. 22 Motivations to Drive3D ICMotivations to Drive 3D IC Source: Yole
- 23. 23 Benefits from 3DInterconnectionsBenefits from 3D Interconnections 2D Connections • Large Form Factor • Long connections SOC Solution • Increase performance • Reduce system size • But might increase device cost 3D Interconnections • Reduce system size • Short interconnections • Reduce package cost Source : IMEC
- 24. 24 What is TSV?Whatis TSV? Through Silicon Vias (TSV) Source: Intel , Samsung, University of Alberta. Create interconnections by using vias, which go through the silicon wafers to form 3D IC Z-direction integration
- 25. 25 TSV Advantages: Elevatorsvs. StairsTSV Advantages: Elevators vs. Stairs Elevator!! Source: Joungho Kim @KAIST
- 26. 26 TSV AdvantagesTSV Advantages Source:Joungho Kim @KAIST
- 27. 27 3D3D--IC Application EvolutionICApplication Evolution Source : Yole • Via size become smaller
- 28. SPIL 3D-IC PackageDevelopment Roadmap Memory Logic Fine Pitch Micro Bump Silicon Interposer - Bridge ASIC to substrate - Platform of high integrated MCM MCM on silicon interposer - IPD integration optional Memory stack - Multi memory die stacked - High capacity 2011 2012 2013 ~~~~ ~~~~ -Chip on Interposer - Stacking - Homogeneous Stacking - MCM on Si Interposer - Heterogeneous Stacking Fine Pitch Micro Joint Structure Logic TSI TSI Logic TSI MemoryLogic TSI eFlash RF eDRAM Logic MEMS Analog / RF Memory Logic Heterogeneous Stacking - Bridge multi function die - Full integrated package 28
- 29. 29 Si-interposer Thk. 100um Wafer THK:99um Via Pitch: 99um Via diameter: 49um TSI (TSV Si Interposer)TSI (TSV Si Interposer)
- 30. TSI/Package Prototype Result Micro-bump Bumppitch=100um Bump height=50um TSI Via diameter=50um Via pitch=250um Wafer THK=100um Top-die:8x8 TSI : 24x24 Substrate : 40x40 solder bump Bump pitch=250um Bump height=77um Top-die:8x8 4 Top-die side by side 30
- 31. 31 GSM Band Balun WLANBPF DCS Band LPF WLAN Diplexer CapacitorCapacitor InductorInductor InductorInductor InductorInductor IPD (Integrated Passive Device)IPD (Integrated Passive Device) From Design to Component, SPIL can provide a customized IPD solution to meet customer’s unique requirement.
- 32. 32 Testing Services Digital Analog Frequency Frequency Fast Fast RF - PortScale -Ultra Flex + EPSILON Consumer - J750 - Catalyst - HP83000 - Quartet - SC312 Computing - Ultra Flex - Sapphire - V93000 - PinScale - T2000 - iFlex SOC -PinScale -Ultra Flex -T2000 Memory Card - Maveric II - Magnum
- 33. 33 System Test CapabilitySystemTest Capability 3DIC Test MEMS Test Advance Test Develop Advance Test Develop EMC Signal Integrate PCB Substrate Design PCB Substrate Design LED Test Load Board Probe Card Low Cost Tester Design Test Tool Kit
- 34. 34 QS CertificationQS Certification ISO9002 / IECQ ‘93 ISO 9001 / QS9000 ‘98 ISO14001:1996 ‘99 ISO17025 ‘00 ISO 9001:2000 ‘02 TS16949 / SONY GP ‘03 OHSAS 18001:1999 ‘04 ISO 14001:2004 ‘05 OHSAS 18001:2007 ‘07 QC080000 ‘08‘84 Founded
- 35. Prototype Wafer Bumping Wafer Sort Module Assembly Function Test DropShip Design • Substrate & Bump mask design • Module / Package Co- Design • Characterization • Reliability validation • FOC/ Repsv/ RDL • WLCSP • Probe card design • Test program optimization • Test System Setup • Socket / change EVB design • Test program Design SPIL Total SolutionsSPIL Total Solutions • WiFi • BT • GPS • Mobile TV….. 35
- 36. 36 IC Package TechnologyChallenges Huge Variety with High Quality Requirement Legacy technology yield > 99.5% Technology with lower materials cost Cu wires Substrate-less (Fan Out) technology HDI substrate alternatives High performance/ multi-dies / thin (<1.0mm) package technology 3DIC –yielding/ reliability / cost
- 37. 37 Introduction IC Packaging IndustryMarket Trend and Challenges IC Packaging Technology & Trend Application of ‘Automatic Image based Inspection” in IC packaging industry AOI SAM & X-ray TSV 3DIC Metrology Summary OutlineOutline
- 38. 38 Principle of AutomaticImage based Inspection Examined Object Wave Source • Visible Light (Optical) • UV/ IR • X –ray • Acoustic (ultrasonic) wave Move in mechanism Move out mechanism Reflecting Wave detection 0 10 20 30 40 50 60 70 80 90 100 Manual Inspection Automatic Inspection Contrasted image Image processing -> identify abnormality Pass/ fail -Main applications: seeking quality issues (to improve) - KPI: 1. Resolution (細) 2. Throughput (快) - 3. Robustness (穩): 不誤宰/ 誤放 (找問題還是找麻煩?)
- 39. 39 AOI Trend: CCDCamera • 數位化的影像陣列相對於螢幕座標之示意圖數位化的影像陣列相對於螢幕座標之示意圖數位化的影像陣列相對於螢幕座標之示意圖數位化的影像陣列相對於螢幕座標之示意圖。。。。 • 影像被分割的越細影像被分割的越細影像被分割的越細影像被分割的越細，，，，每個像素所能表示的明暗範圍越大每個像素所能表示的明暗範圍越大每個像素所能表示的明暗範圍越大每個像素所能表示的明暗範圍越大，，，，影影影影 像的品質自然越好像的品質自然越好像的品質自然越好像的品質自然越好，，，，但是所付出的代價則是大量的記憶空間但是所付出的代價則是大量的記憶空間但是所付出的代價則是大量的記憶空間但是所付出的代價則是大量的記憶空間 和處理時間和處理時間和處理時間和處理時間。。。。。。。。
- 40. 40 AOI trend: 打光打光打光打光 打光的目的打光的目的打光的目的打光的目的 獲得明顯的對比獲得明顯的對比獲得明顯的對比獲得明顯的對比(即反差即反差即反差即反差Contrast)以凸顯輪廓以凸顯輪廓以凸顯輪廓以凸顯輪廓。。。。 強化待測物體的特徵強化待測物體的特徵強化待測物體的特徵強化待測物體的特徵。。。。 環型光源環型光源環型光源環型光源同軸擴散光源同軸擴散光源同軸擴散光源同軸擴散光源 打光實例打光實例打光實例打光實例：：：：
- 41. 41 AOI 檢測實例檢測實例檢測實例檢測實例 2D Configuration MultipleDevice Capability 1x1 1x2 (2x1) 2x2 3x2 (2X3) 定位設定定位設定定位設定定位設定→→→→檢測範圍設定檢測範圍設定檢測範圍設定檢測範圍設定→→→→打光打光打光打光→→→→檢出規格設定檢出規格設定檢出規格設定檢出規格設定→→→→檢測檢測檢測檢測
- 42. 42 Image Analysis andHighlighting 原始影像原始影像原始影像原始影像 經分析後影像經分析後影像經分析後影像經分析後影像(紅色紅色紅色紅色)
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- 45. 45 SAM Theory Coupling Ultrasound • Atransducer produces a high frequency sound wave which interacts with the sample. • High frequency sound waves can not propagate through air. • Couplant- A material used to carry the high frequency sound waves. •Water is the most common couplant for immersion testing. Ultrasound • A transducer produces a high frequency sound wave which interacts with the sample. • High frequency sound waves can not propagate through air. • Couplant- A material used to carry the high frequency sound waves. •Water is the most common couplant for immersion testing. Inspection Modes •Pulse Echo •Through Transmission Inspection Modes •Pulse Echo •Through Transmission H2O Transducer Receive
- 46. 46 SAM Transducer Focusing De-focused--too close Correct focus De-focused-- too far 1. Note the time in microseconds of the signal at the different focus locations. (Red arrow) 2. Also note the amplitude of the signal. When the signal is not in focus the amplitude is lower compared to that of correct focus. Water path 28% 85% 33%
- 47. 47 SAM Common Applications 。。。。Failure Analysis 。。。。 Reliability 。。。。 Process Control 。。。。 Vendor Qualification 。。。。 Production 。。。。 Quality Control 。。。。 Research 。。。。 Plastic encapsulated IC pkg 。。。。 Flip Chips 。。。。 Bonded Wafers 。。。。 Printed Circuit Boards 。。。。 Capacitors 。。。。 Ceramics 。。。。 Power Devices 。。。。 Material Characterization
- 48. 48 SAM machine S牌牌牌牌 H牌牌牌牌 Machine model 1.HS-10001.MT-SCOPE-HYPER 2.QUANTUM-350 2.FS200 3.Fusion 3.FS300 4.ECHO Transducer type Frequency Spot size (mm) Frequency Spot size (mm) 15MHz 0.5inch 0.201 15MHz 15mm 0.300 50MHz 10mm 0.081 50MHz 12mm 0.090 75MHz 12mm 0.080 75MHz 12mm 0.060 110MHz 8mm 0.046 3M 8.1mm 0.032 UHF 8mm 0.025 4M 5.2mm 0.025 8M 2.9mm 0.007
- 49. 49 SAM main applicationin the PKG flow - 1 1. FCBGA Process Flow Heatsink attach 上散熱片上散熱片上散熱片上散熱片 Substrate Pre-bake 基板預烤基板預烤基板預烤基板預烤 Reflow 過迴銲爐過迴銲爐過迴銲爐過迴銲爐 Underfill 液態樹脂填充液態樹脂填充液態樹脂填充液態樹脂填充 Substrate loading 基板置於載具基板置於載具基板置於載具基板置於載具 Chip Attach 上片上片上片上片 Material receive 收料收料收料收料 Wafer saw 割片割片割片割片 Wafer mount 貼片貼片貼片貼片 IQC 進料檢驗進料檢驗進料檢驗進料檢驗 Ball attach 植球植球植球植球 F/V 合檢合檢合檢合檢 Marking 印字印字印字印字 O/S test 電性測試電性測試電性測試電性測試 SMT 上被動元件上被動元件上被動元件上被動元件 SAM gate
- 50. 50 SAM main applicationin the PKG flow - 2 2. BGA Process Flow Die attach 上片上片上片上片 O/S test 電性測試電性測試電性測試電性測試 Material receive 收料收料收料收料 Wafer Lapping 磨片磨片磨片磨片 Wafer mount /saw 貼割片貼割片貼割片貼割片 IQC 進料檢驗進料檢驗進料檢驗進料檢驗 Substrate Pre-bake 基板預烤基板預烤基板預烤基板預烤 Wire bond 銲線銲線銲線銲線 Marking 印字印字印字印字 Singulation 切單切單切單切單 F/V 合檢合檢合檢合檢 Molding 模壓模壓模壓模壓 D/A adhesive cure Solder ball placement 植球植球植球植球 SAM gate
- 51. 51 SAM detection defectphotos-1 Bump Crack Void Die crack Die surface delam Die Pad delam
- 52. 52 SAM detection defectphotos-2 3D Display Crack Delam Die surface delam Die crack
- 53. 53 X-ray theory X-RAY TUBE內電子束高速撞擊靶後產生內電子束高速撞擊靶後產生內電子束高速撞擊靶後產生內電子束高速撞擊靶後產生XXXX---- RAYRAYRAYRAY，，，，射線經射線經射線經射線經Detector由不可見光轉成可見光由不可見光轉成可見光由不可見光轉成可見光由不可見光轉成可見光 後後後後,,,,再經由電腦處理影像後呈現所需影像再經由電腦處理影像後呈現所需影像再經由電腦處理影像後呈現所需影像再經由電腦處理影像後呈現所需影像。。。。 物質吸收X射線t 密度越高的材料容易吸收密度越高的材料容易吸收密度越高的材料容易吸收密度越高的材料容易吸收XXXX射線射線射線射線,,,,產生出來的影像偏黑產生出來的影像偏黑產生出來的影像偏黑產生出來的影像偏黑 如如如如::::金線金線金線金線、、、、錫錫錫錫 球等球等球等球等。。。。受測物的灰階成像除了受密度影響外受測物的灰階成像除了受密度影響外受測物的灰階成像除了受密度影響外受測物的灰階成像除了受密度影響外，，，，材料厚度也是影響因材料厚度也是影響因材料厚度也是影響因材料厚度也是影響因 素之一素之一素之一素之一。。。。 X-RAY Detector Computer 電子束 X射線 靶 受測物 訊號處理 訊號轉換 載物台
- 54. 54 X-ray Common Applications 。。。。Failure Analysis 。。。。 Reliability 。。。。 Process Control 。。。。 Vendor Qualification 。。。。 Production 。。。。 Quality Control 。。。。 Research
- 55. 55 X-ray machine Supplier Machinemodel Spot Size S company SMX-160ET 1um SMX-160GT 1um SMX-160E-ll 1um SMX-160EA300 1um F company FXS 100.20 5um FXS 100.23 2um COUGAR 1um Y.CHEETAH 1um N company NXR-1400 5um
- 56. 56 X-ray main applicationin the PKG flow - 1 1. FCBGA Process Flow Heatsink attach 上散熱片上散熱片上散熱片上散熱片 Substrate Pre-bake 基板預烤基板預烤基板預烤基板預烤 Reflow 過迴銲爐過迴銲爐過迴銲爐過迴銲爐 Underfill 液態樹脂填充液態樹脂填充液態樹脂填充液態樹脂填充 Substrate loading 基板置於載具基板置於載具基板置於載具基板置於載具 Chip Attach 上片上片上片上片 Material receive 收料收料收料收料 Wafer saw 割片割片割片割片 Wafer mount 貼片貼片貼片貼片 IQC 進料檢驗進料檢驗進料檢驗進料檢驗 Ball attach 植球植球植球植球 F/V 合檢合檢合檢合檢 Marking 印字印字印字印字 O/S test 電性測試電性測試電性測試電性測試 SMT 上被動元件上被動元件上被動元件上被動元件 X-RAY Gate
- 57. 57 X-ray main applicationin the PKG flow - 2 2.BGA Process Flow Die attach 上片上片上片上片 O/S test 電性測試電性測試電性測試電性測試 Material receive 收料收料收料收料 Wafer Lapping 磨片磨片磨片磨片 Wafer mount /saw 貼割片貼割片貼割片貼割片 IQC 進料檢驗進料檢驗進料檢驗進料檢驗 Substrate Pre-bake 基板預烤基板預烤基板預烤基板預烤 Wire bond 銲線銲線銲線銲線 Marking 印字印字印字印字 Simulation 切單切單切單切單 F/V 合檢合檢合檢合檢 Molding 模壓模壓模壓模壓 D/A adhesive cure Solder ball placement 植球植球植球植球 X-RAY Gate
- 58. 58 X-ray New option-CT X-RAYSource 沿軸線旋轉被測物沿軸線旋轉被測物沿軸線旋轉被測物沿軸線旋轉被測物 Detector 3維影像重組維影像重組維影像重組維影像重組 截取大量的截取大量的截取大量的截取大量的2D圖像圖像圖像圖像 取得取得取得取得CT影像影像影像影像 X-RAY 系統可升級成具備斷層掃描的系統可升級成具備斷層掃描的系統可升級成具備斷層掃描的系統可升級成具備斷層掃描的CTCTCTCT系統系統系統系統。。。。 CT系統主要增加了系統主要增加了系統主要增加了系統主要增加了旋轉挾具旋轉挾具旋轉挾具旋轉挾具和和和和3D3D3D3D建立與分析軟體建立與分析軟體建立與分析軟體建立與分析軟體，，，， 藉由受測物藉由受測物藉由受測物藉由受測物360360360360度的度的度的度的2D2D2D2D影像收集影像收集影像收集影像收集，，，，再經由軟體的分再經由軟體的分再經由軟體的分再經由軟體的分 析重組析重組析重組析重組，，，，進而得到進而得到進而得到進而得到三維空間結構圖三維空間結構圖三維空間結構圖三維空間結構圖
- 59. 59 X-ray detection defectphotos - 1 FC Process Imagine Defect Item Void Bridge Non-wetting Missing bump Wire Process Imagine Defect Item 線短路線短路線短路線短路 球脫球脫球脫球脫 縫脫縫脫縫脫縫脫
- 60. 60 X-ray detection defectphotos - 2 CT Imagine Short coming of SAM & X-ray: Not yet fully automatic, slow throughput
- 61. New metrology evaluationfor TSV 3DIC Confidential61 1. Source: Confocal (white light) spectral interferometry • Measured Items: CD, depth, defect(bottom & surface), bump high 2. Source: IR interferometry (bright field/ dark field) • Measured Items: CD, depth,Surface defects, Copper studs/Bump height (optional), Post- Bonding voids, Delamination in glue layer, Pre- Bonding Glue uniformity/defects, Thinned Wafer edge, Notch-to-Notch Alignment, TTV of carrier, 3.Source: X-ray • 3D image
- 62. 62 SummarySummary Faster, Smaller, Coolerand Cheaper continue to be four major requirements in semiconductor industry. More high performance IC packaging technologies are being developed , such as Cu pillars, Pop, TSV 3DIC to meet system requirement. On the other hand, industry also hurry in low cost technology due to escalating materials cost Automatic image based inspection tool played very important roles in IC packaging industry to ensure high quality, AOI is maturing, SAM/X-ray need to be more automatic, and new metrology for TSV 3DIC are emerging.
- 63.