Ultra-low voltage digital circuit design is an active research area, especially for portable applications such as wearable electronics, intelligent remote sensors, implantable medical devices, and energy-harvesting systems. Due to their application scenarios and circuit components, two major goals for these systems are minimizing energy consumption and improving compatibility with low-voltage power supplies and analog components. The most effective solution to achieve these goals is to reduce the supply voltage, which, however, raises the issue of operability. At ultra-low supply voltages, the integrity of digital signals degrades dramatically due to the indifference between active and leakage currents. In addition, the system timing becomes more unpredictable as the impact of process and supply voltage variations being more significant at lower voltages. This paper presents a comparative study among three techniques for designing digital circuits operating at ultra-low voltages, i.e., Schmitt-triggered gate structure, delayinsensitive asynchronous logic, and Fully-Depleted Silicon-on-Insulator technology. Results show that despite the tradeoffs, all eight combinations of these techniques are viable for designing ultra-low voltage circuits. For a given application, the optimum circuit design can be selected from these combinations based on the lowest voltage, the dynamic range, the power budget, the performance requirement, and the available semiconductor process node.
Accurate leakage current models for MOSFET nanoscale devices IJECEIAES
This paper underlines a closed form of MOSFET transistor’s leakage current mechanisms in the sub 100nmparadigm.The incorporation of drain induced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (I sub ) was investigated in detail. The Band-To-Band Tunneling (I BTBT ) due to the source and Drain PN reverse junction were also modeled with a close and accurate model using a rectangular approximation method (RJA). The three types of gate leakage (I G ) were also modeled and analyzed for parasitic (I GO ), inversion channel (I GC ), and gate substrate (I GB ). In addition, the leakage resources due to the aggressive reduction in the oxide thickness (<5nm) have been investigated. Simulation results using HSPICE exhibits a tremendous agreement with the BSIM4 model. The dominant value of the sub-threshold leakage was due to the DIBL and GIDL effects. Various recommendations regarding minimizing the leakage current at both device level and the circuit level were suggested at the end of this paper.
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Techn...VLSICS Design
Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very
Large Scale Integration) technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area
,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic
Circuits) are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs
have been proposed over last few years with different logic styles. To reduce the power consumption
several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets,
charge sharing by parasitic components while connecting source and drain of CMOS transistors There are
situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset
themselves) after some prescribed delays. These circuits are hence called postcharge or self-resetting logic
which are widely used in dynamic logic circuits. Overall performance of various adder designs is
evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using
Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V.
On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low
PDP among its counterparts.
The rapid growths of portable electronic devices are increased and they are designing with low power and high speed is critical. To design a three input XOR and XNOR gates using the systematic cell design methodology can be achieved by implementing transmission gate. By this type of designing the low power and high speed can achieved. This architecture is used to maintain summation results for after completing addition process. XOR/XNOR circuits are proposed with high driving capability, full-balanced full-swing outputs and low number transistors of basic structure, high performance and operating at low voltages. This simulation is carried out using TSMC 90nmCMOS technology in Tanner EDA Tool.
Accurate leakage current models for MOSFET nanoscale devices IJECEIAES
This paper underlines a closed form of MOSFET transistor’s leakage current mechanisms in the sub 100nmparadigm.The incorporation of drain induced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (I sub ) was investigated in detail. The Band-To-Band Tunneling (I BTBT ) due to the source and Drain PN reverse junction were also modeled with a close and accurate model using a rectangular approximation method (RJA). The three types of gate leakage (I G ) were also modeled and analyzed for parasitic (I GO ), inversion channel (I GC ), and gate substrate (I GB ). In addition, the leakage resources due to the aggressive reduction in the oxide thickness (<5nm) have been investigated. Simulation results using HSPICE exhibits a tremendous agreement with the BSIM4 model. The dominant value of the sub-threshold leakage was due to the DIBL and GIDL effects. Various recommendations regarding minimizing the leakage current at both device level and the circuit level were suggested at the end of this paper.
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Techn...VLSICS Design
Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very
Large Scale Integration) technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area
,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic
Circuits) are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs
have been proposed over last few years with different logic styles. To reduce the power consumption
several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets,
charge sharing by parasitic components while connecting source and drain of CMOS transistors There are
situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset
themselves) after some prescribed delays. These circuits are hence called postcharge or self-resetting logic
which are widely used in dynamic logic circuits. Overall performance of various adder designs is
evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using
Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V.
On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low
PDP among its counterparts.
The rapid growths of portable electronic devices are increased and they are designing with low power and high speed is critical. To design a three input XOR and XNOR gates using the systematic cell design methodology can be achieved by implementing transmission gate. By this type of designing the low power and high speed can achieved. This architecture is used to maintain summation results for after completing addition process. XOR/XNOR circuits are proposed with high driving capability, full-balanced full-swing outputs and low number transistors of basic structure, high performance and operating at low voltages. This simulation is carried out using TSMC 90nmCMOS technology in Tanner EDA Tool.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation and analysis of power reduction in 2 to 4 decoder design using...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Multilevel inverter offers many benefits for high power application compavered to conventional cascaded Multilevel Inverter topology.This paper presents Symmetric CMLI using variable frequency carrier based pulse width modulation techniques. The proposed topology reduces total harmonic distortion and reduced switching losses for seven level inverter. The simulation study of the proposed topology has been carried out in MATLAB/SIMULINK. The main objective of this paper is to achieve number of levels of MLI with reduced number of switches and DC power sources compared to conventional topology.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
250 MHz Multiphase Delay Locked Loop for Low Power Applications IJECEIAES
Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. The proposed design is implemented at 0.18 um CMOS technology and at power supply of 1.8 V . It has power consumption of 1.39 mW at 125 center frequency with locking range from 0.5 MHz to 250 MHz . MHz
Design of subthreshold dml logic gates with power gating techniqueseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Low power is one of the key research area in today’s electronic industry. Need of low power has created a major pattern shift in the field of electronics where power dissipation is equally important as area, performance etc. Several low power portable electronic equipments, low voltage design techniques have been developed and have driven analog designers to create techniques eg. Self cascode mosfet and stacking technique. For this aim in mind we designed a Folded Cascode using low power techniques and analyzed its various properties through the Spice simulations for 0.13 micron CMOS technology from TSMC and the supply voltage 1.8V.
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
PERFORMANCE ANALYSIS OF SRAM CELL USING REVERSIBLE LOGIC GATESBUKYABALAJI
ABSTRACT: Reversible logic shows a great potential
in the design of Low-power circuits. Remarkable work
has been done in design of basic arithmetic circuits.
Present day progress in sequential circuit design of
reversible logic circuits has shown new ways in
performance of Static random access memory
(SRAM) and Dynamic random access memory
(DRAM). As the memory size is increasing
exponentially, the power absorbed by memory cells is
also growing rapidly. In recent years reversible logic
has achieved great interest because of its low power
performances. This paper proposes a new SRAM
c e l l which u s e s Feynman gates. The proposed
SRAM cell shows reduction of 66% in terms of
quantum cost, 66% reduction in quantum delay, 60%
reduction in number of gates count and 50% reduction
in number of transistors count
An approach to design Flash Analog to Digital Converter for High Speed and Lo...VLSICS Design
This paper proposes the Flash ADC design using Quantized Differential Comparator and fat tree encoder. This approach explores the use of a systematically incorporated input offset voltage in a differential amplifier for quantizing the reference voltages necessary for Flash ADC architectures, therefore eliminating the need for a passive resistor array for the purpose. This approach allows very small voltage comparison and complete elimination of resistor ladder circuit. The thermometer code-to-binary code encoder has become the bottleneck of the ultra-high speed flash ADCs. In this paper, the fat tree thermometer code to-binary code encoder is used for the ultra high speed flash ADCs. The simulation and the implementation results shows that the fat tree encoder performs the commonly used ROM encoder in terms of speed and power for the 6 bit CMOS flash ADC case. The speed is improved by almost a factor of 2 when using the fat tree encoder, which in fact demonstrates the fat tree encoder and it is an effective solution for the bottleneck problem in ultra-high speed ADCs.The design has been carried out for the 0.18um technology using CADENCE tool.
A transmission gate is similar to a relay that can conduct in both directions or block by a control signal with almost any voltage potential. CMOS transmission gate consists of one nMOS and one pMOS transistor, connected in parallel. The gate voltages applied to these two transistors are also set to be complementary signals. As such, the CMOS TG operates as a bidirectional switch between the nodes A and B which is controlled by signal C.
A Bus Encoding Method for Crosstalk and Power Reduction in RC Coupled VLSI In...VLSICS Design
The performance factors such as propagation delay, power dissipation and crosstalk in RC modelled interconnects are major design issues for the System on-chip (SoC) designs in current Deep Submicron (DSM) era. The crosstalk effect is a consequence of coupling and switching activities that is encountered when there is a transition as compared to previous state of wire and or when there are transitions in adjacent wires. Therefore, minimization or elimination of switching and coupling activities is crucial in enhancing the performance of SoC designs. There are several methods for the reduction of power dissipation, crosstalk and delay. The encoding method is most effective and popular method for enhancing the behaviour of on-chip buses. This paper proposes encoding scheme to achieve overall reduction in transitions. The reduction in transition improves the performance in terms of reduced power dissipation, coupling activity and delay in on-chip buses. This encoding method is implemented using VHDL. The result evidently demonstrates reduction in transitions which consequently improves the overall performance of on-chip buses.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation and analysis of power reduction in 2 to 4 decoder design using...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Multilevel inverter offers many benefits for high power application compavered to conventional cascaded Multilevel Inverter topology.This paper presents Symmetric CMLI using variable frequency carrier based pulse width modulation techniques. The proposed topology reduces total harmonic distortion and reduced switching losses for seven level inverter. The simulation study of the proposed topology has been carried out in MATLAB/SIMULINK. The main objective of this paper is to achieve number of levels of MLI with reduced number of switches and DC power sources compared to conventional topology.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
250 MHz Multiphase Delay Locked Loop for Low Power Applications IJECEIAES
Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. The proposed design is implemented at 0.18 um CMOS technology and at power supply of 1.8 V . It has power consumption of 1.39 mW at 125 center frequency with locking range from 0.5 MHz to 250 MHz . MHz
Design of subthreshold dml logic gates with power gating techniqueseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Low power is one of the key research area in today’s electronic industry. Need of low power has created a major pattern shift in the field of electronics where power dissipation is equally important as area, performance etc. Several low power portable electronic equipments, low voltage design techniques have been developed and have driven analog designers to create techniques eg. Self cascode mosfet and stacking technique. For this aim in mind we designed a Folded Cascode using low power techniques and analyzed its various properties through the Spice simulations for 0.13 micron CMOS technology from TSMC and the supply voltage 1.8V.
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
PERFORMANCE ANALYSIS OF SRAM CELL USING REVERSIBLE LOGIC GATESBUKYABALAJI
ABSTRACT: Reversible logic shows a great potential
in the design of Low-power circuits. Remarkable work
has been done in design of basic arithmetic circuits.
Present day progress in sequential circuit design of
reversible logic circuits has shown new ways in
performance of Static random access memory
(SRAM) and Dynamic random access memory
(DRAM). As the memory size is increasing
exponentially, the power absorbed by memory cells is
also growing rapidly. In recent years reversible logic
has achieved great interest because of its low power
performances. This paper proposes a new SRAM
c e l l which u s e s Feynman gates. The proposed
SRAM cell shows reduction of 66% in terms of
quantum cost, 66% reduction in quantum delay, 60%
reduction in number of gates count and 50% reduction
in number of transistors count
An approach to design Flash Analog to Digital Converter for High Speed and Lo...VLSICS Design
This paper proposes the Flash ADC design using Quantized Differential Comparator and fat tree encoder. This approach explores the use of a systematically incorporated input offset voltage in a differential amplifier for quantizing the reference voltages necessary for Flash ADC architectures, therefore eliminating the need for a passive resistor array for the purpose. This approach allows very small voltage comparison and complete elimination of resistor ladder circuit. The thermometer code-to-binary code encoder has become the bottleneck of the ultra-high speed flash ADCs. In this paper, the fat tree thermometer code to-binary code encoder is used for the ultra high speed flash ADCs. The simulation and the implementation results shows that the fat tree encoder performs the commonly used ROM encoder in terms of speed and power for the 6 bit CMOS flash ADC case. The speed is improved by almost a factor of 2 when using the fat tree encoder, which in fact demonstrates the fat tree encoder and it is an effective solution for the bottleneck problem in ultra-high speed ADCs.The design has been carried out for the 0.18um technology using CADENCE tool.
A transmission gate is similar to a relay that can conduct in both directions or block by a control signal with almost any voltage potential. CMOS transmission gate consists of one nMOS and one pMOS transistor, connected in parallel. The gate voltages applied to these two transistors are also set to be complementary signals. As such, the CMOS TG operates as a bidirectional switch between the nodes A and B which is controlled by signal C.
A Bus Encoding Method for Crosstalk and Power Reduction in RC Coupled VLSI In...VLSICS Design
The performance factors such as propagation delay, power dissipation and crosstalk in RC modelled interconnects are major design issues for the System on-chip (SoC) designs in current Deep Submicron (DSM) era. The crosstalk effect is a consequence of coupling and switching activities that is encountered when there is a transition as compared to previous state of wire and or when there are transitions in adjacent wires. Therefore, minimization or elimination of switching and coupling activities is crucial in enhancing the performance of SoC designs. There are several methods for the reduction of power dissipation, crosstalk and delay. The encoding method is most effective and popular method for enhancing the behaviour of on-chip buses. This paper proposes encoding scheme to achieve overall reduction in transitions. The reduction in transition improves the performance in terms of reduced power dissipation, coupling activity and delay in on-chip buses. This encoding method is implemented using VHDL. The result evidently demonstrates reduction in transitions which consequently improves the overall performance of on-chip buses.
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial
space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the
aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD
and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the “stacked” architecture introduce negligible overhead
compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the “stacked” architecture introduce negligible overhead compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial
space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the
aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running
different workloads. These results show that the “stacked” architecture introduce negligible overhead compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITSVLSICS Design
A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.
Improving energy efficiency has always been the prime objective of the custom and automated digital circuit design techniques. However, as the field of design automation has matured over the last few decades, there have been no new automated design techniques, that can provide considerable improvements in circuit power, delay. Although emerging nano-devices are expected to replace the existing MOSFET devices, they are far from being as mature as semiconductor devices and their full potential and promises are many years away from being practical. The research described in this dissertation consists of four main parts. First is a new circuit architecture of a differential threshold logic flip-flop called PNAND. The PNAND gate is an edge-triggered multi-input sequential cell whose next state function is a threshold function of its inputs. Second a new approach, called hybridization, that replaces flip-flops and parts of their logic cones with PNAND cells is described. The resulting hybrid circuit, which consists of conventional logic cells and PNANDs, is shown to have significantly less power consumption, smaller area, less standby power and less power variation. Third, a new architecture of a field programmable array, called field programmable threshold logic array (FPTLA), in which the standard lookup table (LUT) is replaced by a PNAND is described. The FPTLA is shown to have as much as 50% lower energy delay product compared to conventional FPGA using well known FPGA modeling tool called VPR. Fourth, a novel clock skewing technique that makes use of the completion detection feature of the differential mode flip-flops is described.
AREA EFFICIENT 3.3GHZ PHASE LOCKED LOOP WITH FOUR MULTIPLE OUTPUT USING 45NM ...VLSICS Design
This paper present area efficient layout designs for 3.3GigaHertz (GHz) Phase Locked loop (PLL) with four multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output, using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry, translation onto silicon, CAD and practical experience in layout design. The proposed PLL is designed using 45 nm CMOS/VLSI technology with microwind 3.1. This software allows designing and simulating an integrated circuit at physical description level. The main novelties related to the 45 nm technology are the high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate length required for 45 nm technology is 25nm. Low Power (0.211miliwatt) phase locked loop with four multiple outputs as PLL8x, PLL4x, PLL2x, & PLL1x of 3.3 GHz, 1.65 GHz, 0.825 GHz, and 0.412 GHz respectively is obtained using 45 nm VLSI technology.
A new improved mcml logic for dpa resistant circuitsVLSICS Design
Security of electronic data remains the major conce
rn. The art of encryption to secure the data can be
achieved in various levels of abstraction. The choi
ce of the logic style in implementing the security
algorithms has greater significance, and it can enh
ance the ability of providing better resistance to
side
channel attacks. The static CMOS logic style is pro
ved to be prone to side channel power attacks. The
exploration of CMOS current mode logic style for re
sistance against these side channel attacks is disc
ussed
in this paper. Various characteristics of the curre
nt mode logic styles, which make it suitable for ma
king
DPA resistant circuits are explored. A new methodol
ogy of biasing the sleep transistors of (MOS curren
t
mode logic) MCML families is proposed. It uses pass
gate transistors for power-gating the circuits. Th
e
power variations of the proposed circuits are compa
red against the standard CMOS counterparts. Logic
gates such as XOR, NAND and AND gate structures of
MCML families and static CMOS are designed and
compared for the ability of side channel resistance
. A distributed arrangement of sleep transistors fo
r
reducing the static power dissipation in the logic
gates is also proposed, designed and analyzed. All
the
logic gates in MCML and CMOS were implemented using
standard 180 nm CMOS technology employing
Cadence® EDA tools.
A NOVEL LOW POWER HIGH DYNAMIC THRESHOLD SWING LIMITED REPEATER INSERTION FOR...VLSICS Design
In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs. With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay and power consumption. An eminent technique known as repeater/buffer insertion is used in long interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm technology. By simulating and comparing these various repeater circuits along with the proposed circuits it is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power is reduced by using the high- Vth in HDTSL when compared to DTSL.
A novel low power high dynamic threshold swing limited repeater insertion for...VLSICS Design
In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs.
With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay
and power consumption. An eminent technique known as repeater/buffer insertion is used in long
interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power
alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold
Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic
Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High
Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold
voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm
technology. By simulating and comparing these various repeater circuits along with the proposed circuits it
is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power
is reduced by using the high- Vth in HDTSL when compared to DTSL.
A low power cmos analog circuit design for acquiring multichannel eeg signalsVLSICS Design
EEG signals are the signatures of neural activities and are captured by multiple-electrodes and the signals are recorded from pairs of electrodes. To acquire these multichannel signals a low power CMOS circuit was designed and implemented. The design operates in weak inversion region employing sub threshold
source coupled logic. A 16 channel differential multiplexer is designed by utilizing a transmission gate with
dynamic threshold logic and a 4 to 16 decoder is used to select the individual channels. The ON and OFF
resistance of the transmission gate obtained is 27 ohms and 10 M ohms respectively. The power dissipation
achieved is around 337nW for a dynamic range of 1μV to 0.4 V.
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
Call for paper 2012, hard copy of Certificate, research paper publishing, where to publish research paper,
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJCER, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, research and review articles, IJCER Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathematics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer review journal, indexed journal, research and review articles, engineering journal, www.ijceronline.com, research journals,
yahoo journals, bing journals, International Journal of Computational Engineering Research, Google journals, hard copy of Certificate,
journal of engineering, online Submission
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 7, JULY 199MalikPinckney86
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 7, JULY 1997 1079
Low-Power Logic Styles: CMOS
Versus Pass-Transistor Logic
Reto Zimmermann and Wolfgang Fichtner,Fellow, IEEE
Abstract—Recently reported logic style comparisons based on
full-adder circuits claimed complementary pass-transistor logic
(CPL) to be much more power-efficient than complementary
CMOS. However, new comparisons performed on more efficient
CMOS circuit realizations and a wider range of different logic
cells, as well as the use of realistic circuit arrangements demon-
strate CMOS to be superior to CPL in most cases with respect
to speed, area, power dissipation, and power-delay products.
An implemented 32-b adder using complementary CMOS has
a power-delay product of less than half that of the CPL version.
Robustness with respect to voltage scaling and transistor sizing,
as well as generality and ease-of-use, are additional advantages
of CMOS logic gates, especially when cell-based design and logic
synthesis are targeted. This paper shows that complementary
CMOS is the logic style of choice for the implementation of
arbitrary combinational circuits if low voltage, low power, and
small power-delay products are of concern.
Index Terms—Adder circuits, CPL, complementary CMOS,
low-voltage low-power logic styles, pass-transistor logic, VLSI
circuit design.
I. I NTRODUCTION
T HE increasing demand for low-power very large scaleintegration (VLSI) can be addressed at different de-
sign levels, such as the architectural, circuit, layout, and
the process technology level [1]. At the circuit design level,
considerable potential for power savings exists by means of
proper choice of a logic style for implementing combinational
circuits. This is because all the important parameters governing
power dissipation—switching capacitance, transition activity,
and short-circuit currents—are strongly influenced by the
chosen logic style. Depending on the application, the kind
of circuit to be implemented, and the design technique used,
different performance aspects become important, disallowing
the formulation of universal rules for optimal logic styles. In-
vestigations of low-power logic styles reported in the literature
so far, however, have mainly focused on particular logic cells,
namely full-adders, used in some arithmetic circuits. In this
paper, these investigations are extended to a much wider set of
logic gates, and with that, to arbitrary combinational circuits.
The power dissipation characteristics of various existing logic
styles are compared qualitatively and quantitatively by actual
logic gate implementations and simulations under realistic cir-
cuit arrangements and operating conditions [2]. Investigations
of sequential elements, such as latches and flip-flops, were
Manuscript received November 20, 1996; revised January 29, 1997.
The authors are with the Integrated Systems Laboratory, Swiss Federal
Institute of Technology (ETH), CH-8092 Zurich, Switzerland.
Publisher It ...
A DAPTIVE S UPPLY V OLTAGE M ANAGEMENT F OR L OW P OWER L OGIC C IRCU...VLSICS Design
With the rise in demand of portable hand held devic
es and with the rise in application of wireless sen
sor
networks and RFID reduction of total power consumpt
ion has become a necessity. To save power we
operate the logic circuitry of our devices at sub-t
hreshold. In sub-threshold the drain current is
exponentially dependent on the threshold voltage he
nce the threshold variation causes profound variati
on
of I
ON
and I
OFF
the ratio of which affect the speed of a circuit d
rastically. So to mitigate this problem we
present a adaptive power management circuit which w
ill determine the minimum required supply voltage
to meet the timing requirement. Also to reduce the
power overhead and avoid bulky coil and EMI noise
we used the switch capacitor power regulator to reg
ulate and manage power instead of linear dropout
(LDO) and Inductor base switch mode power converter
Codec Scheme for Power Optimization in VLSI InterconnectsIJEEE
This paper presents a codec scheme for optimizing power in VLSI Interconnects. It is based on the traditional bus encoding method which is considered to be one of the most effective ways of power and delay reduction. The work done aims at optimizing power by designing the scheme using Full-Custom design approach. The model has been designed and implemented using Cadence Virtuoso Analog Design Suite in 0.18µm CMOS technology. Power has been computed for different possible combinations of input data. Delay has been reckoned for the maximum power consuming input combination. Layout editor has been used to generate the physical description of the circuit. The 4 bit input data combination consuming maximum dynamic power of 6.44µW and propagation delay of 722.7ps is “1000” with previously transmitted 4 bit data being “0111”. A significant power reduction of 38.89% has been observed by designing the scheme using Full-Custom approach as compared to the conventional Semi-Custom approach of design.
Back track input vector algorithm for leakage reduction in cmos vlsi digital ...VLSICS Design
A new algorithm based on Input Vector Control (IVC) technique is proposed, which shifts logic gate of a
circuit to its minimum leakage state, when device goes into its idle state. Leakage current in CMOS VLSI
circuit has become a major constrain in a battery operated device for technology node below 90nm, as it
drains the battery even when a circuit is in standby mode. Major concern is the leakage even in run time
condition, here aim is to focus on run time leakage reduction technique of integrated Circuit. It is inherited
by stacking effect when the series transistors are maximized in OFF state condition. This method is
independent of process technology and does not require any additional power supply. This paper gives an
optimized solution of input pattern determination of some small circuit to find minimum leakage vector
considering promising and non-promising node which helps to reduce the time complexity of the algorithm.
Proposed algorithm is simulated using HSPICE simulator for 2 input NAND gate and different standard
logic cells and achieved 94.2% and 54.59 % average leakage power reduction for 2 input NAND cell and
different logics respectively.
Similar to A COMPARATIVE STUDY OF ULTRA-LOW VOLTAGE DIGITAL CIRCUIT DESIGN (20)
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About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
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Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
A COMPARATIVE STUDY OF ULTRA-LOW VOLTAGE DIGITAL CIRCUIT DESIGN
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
DOI : 10.5121/vlsic.2012.3301 1
A COMPARATIVE STUDY OF ULTRA-LOW VOLTAGE
DIGITAL CIRCUIT DESIGN
Aaron Arthurs, Justin Roark, and Jia Di
Computer Engineering and Computer Science Department, University of Arkansas
Fayetteville, Arkansas, USA
jdi@uark.edu
ABSTRACT
Ultra-low voltage digital circuit design is an active research area, especially for portable applications such
as wearable electronics, intelligent remote sensors, implantable medical devices, and energy-harvesting
systems. Due to their application scenarios and circuit components, two major goals for these systems are
minimizing energy consumption and improving compatibility with low-voltage power supplies and analog
components. The most effective solution to achieve these goals is to reduce the supply voltage, which,
however, raises the issue of operability. At ultra-low supply voltages, the integrity of digital signals
degrades dramatically due to the indifference between active and leakage currents. In addition, the system
timing becomes more unpredictable as the impact of process and supply voltage variations being more
significant at lower voltages. This paper presents a comparative study among three techniques for
designing digital circuits operating at ultra-low voltages, i.e., Schmitt-triggered gate structure, delay-
insensitive asynchronous logic, and Fully-Depleted Silicon-on-Insulator technology. Results show that
despite the tradeoffs, all eight combinations of these techniques are viable for designing ultra-low voltage
circuits. For a given application, the optimum circuit design can be selected from these combinations based
on the lowest voltage, the dynamic range, the power budget, the performance requirement, and the
available semiconductor process node.
KEYWORDS
Ultra-Low Voltage, Asynchronous Logic, Delay-Insensitive, Schmitt-Triggered, Silicon-on-Insulator
1. INTRODUCTION
Digital circuits capable of operating reliably under ultra-low voltages are highly beneficial to
portable electronic systems that have strict power constraints. There are trade-offs in battery-
powered portable devices among power consumption, performance, and supply voltage. Ultra-
low voltage designs significantly reduce active power consumption and are useful in devices that
cannot maintain a steady, above-threshold supply voltage. Applications of ultra-low voltage
circuits include intelligent remote sensors, energy-harvesting systems, implantable medical
devices, and wearable electronics.
However, at such low supply voltages operability becomes an issue. In ultra-low voltage designs,
the threshold voltage of the transistor is never reached, i.e., subthreshold operation. In this region,
leakage current (Ioff), rather than active current (Ion), drives the transistors. Therefore, the drive
strength significantly degrades, which differentiates many circuit characteristics from those
working in above-threshold, saturation region. One difference is the increased propagation delay
in each logic gate due to the low drive strength, which makes ultra-low voltage circuits only
suitable for low-speed applications. Another difference is the need of special gate structures in
order to prevent the failure in pulling up/down the gate output. For example, logic gates for
subthreshold operation are advised to have no more than two inputs.
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
2
The architecture and gate design of a digital system have strong impacts on the scalability of
supply voltage (VDD). A Fast Fourier Transform circuit has been developed on a 0.18µm bulk-
silicon process to operate at 180mV [1]. Setting the supply voltage for a CMOS inverter to 4kT/q
is described in [2]. Process, voltage, and temperature (PVT) variation induced timing fluctuations
have a greater impact on subthreshold circuit operations than that on above-threshold operations.
Techniques such as doping profile modification and adaptive body-biasing have been proposed as
means to mitigate such timing fluctuations. Similar to other power reduction techniques such as
dynamic voltage scaling, forced transistor stacking, and power gating [3-5], maintaining the
integrity of the digital signal is critical to achieve reliability under ultra-low voltages.
Up to now, ultra-low voltage digital circuit design is still a relatively new research area and there
is no universally adopted conclusion on which design methodology is the best for a given
application. This paper is to provide a comparative study on the combination of process-,
architecture-, and circuit-level techniques in order for researchers to evaluate the effectiveness
and efficiency of each solution, as well as the tradeoffs among them. The process-level
comparison is between a bulk-silicon process from IBM and a Fully-Depleted Silicon-on-
Insulator (FD-SOI) process from MIT Lincoln Laboratory [6]. The architecture-level comparison
is between the traditional clocked synchronous logic and a delay-insensitive asynchronous logic,
NULL Convention Logic [7]. The circuit level comparison is between the regular static gate
design and a Schmitt-triggered inverter based gate structure [8]. The metrics include active
energy, leakage power, and performance.
2. BACKGROUND
2.1. Asynchronous Logic and NULL Convention Logic (NCL)
Asynchronous circuits are by definition circuits that do not require an external mechanism (e.g.,
clocks) to control the flow of data processing. Delay-insensitive (DI) asynchronous logic is a
subset of asynchronous paradigm, which is correct-by-construction and does not require timing
analysis. NCL is a quasi-delay-insensitive style of asynchronous logic which, for the mostly
negligible compromise of the interconnect isochronic fork assumption, has practical use in
designing modern and future digital circuits [8]. The benefits of NCL include high energy
efficiency, robust circuit operation, flexible timing requirement, PVT variation tolerance, and low
noise/emission.
In addition to DATA 0 and 1, NCL introduces a third signal state called NULL, which indicates
that data is not ready yet. A common implementation of NCL is dual-rail logic where each signal
is composed of two wires that indicate either NULL or a single bit of data. NCL circuits operate
by alternating DATA and NULL wavefronts, transitioning between data validity and invalidity to
separate multiple sets of data. In order to ensure the validity of circuit outputs, NCL requires that
all inputs transition to DATA (NULL) before processing the subsequent NULL (DATA).
NCL specifies a pipeline framework that is similar to that of synchronous logic, as shown in
Figure 1. In an NCL pipeline, a circuit is divided into multiple stages, and each stage is
sandwiched between two DI registers. A DI register, unlike a synchronous register, is controlled
by input data from the previous stage (or primary input) and a completion signal from the next
stage (or primary output). When the DI register receives a completion signal from the next stage,
it latches either DATA or NULL from its input and propagates the completion signal to the
previous stage. In a cycle of operation of an NCL pipeline, each stage 1) requests for DATA from
their previous stage; 2) processes DATA from the previous stage and outputs results to the next
stage; 3) waits for the next stage to acknowledge the results; 4) requests for NULL from the
previous stage; 5) propagates NULL to the next stage; and 6) waits for the next stage to
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
3
acknowledge NULL. In short, DATA/NULL propagates forward followed by an
acknowledgment of receiving DATA/NULL.
DI Register
KiKo
DI
Combinational
Logic
DI Register
KiKo
Completion
Detection
DI
Combinational
Logic
DI Register
KiKo
Completion
Detection
DI Register
KiKo
Figure 1. NCL Architecture.
The basic building blocks of NCL circuits are 27 threshold gates [6]. A threshold gate is a state-
holding circuit that specifies a Boolean expression, which triggers output assertion and keeps the
output asserted until all gate inputs are unasserted. As shown in Figure 2, the generic threshold
gate is THmn gate, where 1 ≤ m ≤ n. THmn gates have n inputs; at least m of the n inputs must be
asserted before the output will become asserted. Once a gate’s output is asserted, all n inputs must
be unasserted for the output to be unasserted. The gate holds its current state through hysteresis, a
feedback function that ensures complete transitions to either the DATA (asserted) or NULL
(unasserted) state. For example, a TH34w2 gate has four inputs and a threshold of three; the first
input has a weight of two, and the remaining three inputs each has a weight of one. The Boolean
expression that asserts the TH34w2 gate’s output is ab+ac+ad+bcd. Once asserted, the output
can only be unasserted if all inputs are unasserted. Static CMOS threshold gates are composed of
networks that either change the output or hold the output. As shown in Figure 3, the RESET block
forces the output to be logic 0 and the SET block forces the output to be logic 1. The Hold0 and
Hold1 blocks maintain the output unchanged when the number of logic 1’s among the inputs is
between 0 and the gate’s threshold.
m
input 1
input 2
input n
output
Figure 2. THmn Threshold Gate.
Figure 3. Static Threshold Gate Structure.
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
4
2.2. Schmitt-Triggered Gate Structure
The Schmitt-triggered gate design, introduced in [8], actively suppresses leakage current through
either the pull-up or pull-down network. Following the static CMOS implementation of a Schmitt
trigger, the pull-up and pull-down networks are duplicated and stacked in series. The node in
between the original and duplicate networks becomes a virtual supply, which is also connected to
the opposite supply voltage through a power-gating transistor. The gate output is fed back to
control each virtual supply’s power-gating transistor. While the gate inputs select which network
is active, the gate output feedback drives the inactive network’s supply to the same voltage as the
gate output, i.e., positive feedback. Figure 4 shows a general schematic of a Schmitt-triggered
gate.
Figure 4. Schmitt-Triggered Gate Structure.
Correct operation of a Schmitt-triggered gate requires that the active network overpowers the
power-gating transistor. Conversely, the power-gating transistor must suppress leakage current
paths through the inactive network. Weak power-gating transistors are utilized in order for the
active network to override the gate output feedback; otherwise, the gate output will not switch
state.
Ideally, each virtual supply swings between the respective network supply voltage and the
opposite supply voltage, depending on which network is active. However, in reality each virtual
supply alternates between their network supply voltage and a voltage level in between supplies.
For example, the virtual ground in the pull-down network alternates between ground and a
voltage level higher than ground. Experiments show that each virtual supply is biased towards
their network supply voltage due to weak power-gating transistors.
2.3. Fully-Depleted Silicon-On-Insulator
SOI technologies fall under two categories: partially-depleted and fully-depleted (PD-SOI and
FD-SOI). The difference between PD-SOI and FD-SOI processes is the thickness of the SOI and
buried oxide layers. FD-SOI uses thin SOI and buried oxide layers such that the depletion region
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
5
extends throughout the transistor’s floating body and partially into the substrate underneath the
buried oxide layer. For digital circuits, full depletion is preferred over partial depletion because
full depletion removes all free charged carriers from the body when forming the inversion layer
(channel). FD-SOI requires little or no doping in the transistor’s body. The combination of a
neutrally charged body and the buried oxide significantly reduces the drain-to-substrate parasitic
capacitance, requiring less energy to switch the transistor. Since the body is lightly and uniformly
doped, it takes little effort to form the inversion layer, and threshold variation is reduced because
light doping minimizes random dopant fluctuation. When an FD-SOI transistor is inactive, the
drain-to-body leakage current is negligible due to the body being electrically isolated and having
little intrinsic charge.
3. TEST CIRCUITS AND SIMULATION SETUP
The test circuit selected is an IEEE single-precision (32-bit) floating-point coprocessor that
supports addition, subtraction, and multiplication. Figure 5 shows its block diagram. This
coprocessor is implemented in eight versions, corresponding to all eight combinations of the three
techniques, i.e., bulk-Si static synchronous, bulk-Si Schmitt-triggered synchronous, bulk-Si static
NCL, bulk-Si Schmitt-triggered NCL, FD-SOI static synchronous, FD-SOI Schmitt-triggered
synchronous, FD-SOI static NCL, and FD-SOI Schmitt-triggered NCL.
Add
Align Significands
Normalize
Round and Selective
Complement
Normalize
Selective Complement
and Possible SwapSubMux
Control
& Sign
Logic
Add
SignificandsExponents
Signs
Add/Sub
SignificandExponentSign
Cout
Cin
Sum / Difference
SignificandsExponentsSigns
Add
Exponents
Multiply Significands
Normalize
Adjust
Exponent
Round
Normalize
Adjust
Exponent
XOR
SignificandExponentSign
Product
Figure 5. Block Diagram of the Test Circuit.
The methodology to size the transistors in a Schmitt-triggered gate is currently a trial-and-error
process that depends on the target supply voltage, the fan-out of each gate, and each transistor’s
input (gate) capacitance. The transistor sizes in each network are counterbalanced against the
feedback transistors until the gate output can swing sufficiently, at least between 20 and 80
percent of the supply voltage. Based on the results from [8], 65 mV is chosen as the target supply
voltage for each Schmitt-triggered gate. On the other hand, static CMOS gates are sized to
balance output rise and fall times at an above-threshold supply of 1V.
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
6
Cadence UltraSim is chosen to run transistor-level simulations because it is optimized for large-
scale mixed-signal circuits. UltraSim employs circuit partitioning and simplified MOSFET
models in order to improve simulation performance. There are several levels of accuracy that
range from BSIM MOSFET models with no partitioning to digital table-lookup models with
hierarchical circuit partitioning. Tuning the simulator is a trade-off between simulation
performance and accuracy that depends on the type of verification required. In this paper,
functioning testing and power analysis are the two main objectives of simulation. While
functional testing can be performed at any accuracy level, power analysis at minimum requires
the analog table-lookup models for MOSFETs. UltraSim must therefore be set to ‘mixed-signal’
mode that uses analog table-lookup models and circuit partitioning.
The IBM 8RF-DM 130nm process is chosen for bulk-Si, and the MIT Lincoln Lab 150nm xLP
process is selected for FD-SOI. The base MOSFET models used between the two processes
differ. UltraSim is set to ‘mixed-signal’ mode for the 130nm bulk-silicon process and ‘digital-
accurate’ mode for the 150nm xLP process. In ‘digital-accurate’ mode, UltraSim uses digital
table-lookup models that are not suitable for power analysis. The reason for using ‘digital-
accurate’ mode is that the xLP MOSFET devices have irresolvable convergence issues with
UltraSim’s analog table-lookup models. Another option considered is simulating the xLP process
with the BSIMSOI MOSFET models, but simulation performance degrades significantly and
becomes impractical for a large digital circuit such as the IEEE floating-point coprocessor.
Each NCL coprocessor connects to a Verilog-A NCL controller that supplies input vectors,
performs handshaking, and checks the results. The NCL controller also measures the amount of
time taken to process each set of inputs, including the NULL cycle. Each synchronous
coprocessor connects to a Verilog-A synchronous controller. The synchronous controller drives a
digital clock at 50 percent duty cycle at an adjustable frequency, supplies input vectors on each
negative clock edge, and checks the results on falling clock edges after the coprocessor pipeline is
primed. Between the coprocessor-under-test and Verilog-A controller are input buffers, which act
as input transition filters to ensure correct input timing at any given supply voltage. Both the NCL
and synchronous controllers provide the same set of input values that consist of three additions,
three subtractions, and three multiplications as shown in Table 1.
Table 1. Input/Output IEEE Single-Precision Floating-Point Vectors
Vector Operation X (input) Y (input) Z (output)
1 Addition 0x447CC000 0x448AE000 0x4504A000
2 Addition 0xC070B7FE 0xC12E057D 0xC16A337D
3 Addition 0x490D7523 0xD011CC0C 0xD011C9D6
4 Subtraction 0x447CC000 0x448AE000 0xC2C80000
5 Subtraction 0xC070B7FE 0xC12E057D 0x40E3AEFA
6 Subtraction 0x490D7523 0xD011CC0C 0x5011CE42
7 Multiplication 0x447CC000 0x448AE000 0x49891CA8
8 Multiplication 0xC070B7FE 0xC12E057D 0x4223A238
9 Multiplication 0x490D7523 0xD011CC0C 0xD9A12032
All coprocessors undergo a discrete supply voltage sweep, from 50mV to 1V, to determine their
operating supply range. At certain supply voltages, the minimum required clock period and
throughput are recorded. Active energy and leakage power are measured by integrating the supply
current over the appropriate period of time. Equations 1 and 2 measure active energy and leakage
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
7
power respectively. Active energy is measured during circuit operation while leakage power is
calculated over a one-second period after circuit operation.
∫=
2
1
)(
t
t
dttiVddgyActiveEner (1)
23
)(
3
2
tt
dttiVdd
erLeakagePow
t
t
−
=
∫ (2)
4. RESULTS AND ANALYSIS
During simulations, it is discovered that all four Schmitt-triggered designs operate within a much
narrower VDD range compared to the static counterparts, with the highest operational VDD below
the lowest operational VDD of static designs. In other words, there is no overlap in terms of
operational VDD points between the two design groups. Therefore, the results for these two groups
are presented separately. In addition, all four bulk-Si designs are simulated using UltraSim’s
‘mixed-signal’ mode, for which MOSFETs are modelled with pre-calculated tables to speed up
BSIM equation calculations. However, as stated in the previous section, convergence problems
occur when simulating the four FD-SOI designs using ‘mixed-signal’ mode. A less accurate
mode, ‘digital-accurate’, which bypasses BSIM equations using simplified equations and digital
look-up tables, has to be used to simulate these designs. Therefore, the results from these
simulations are presented separately and are not meant to be compared with those of the other
four circuits.
Table 2 shows the comparison between the two bulk-Si static designs. Several observations can
be made: 1) both designs function properly from 1V VDD to 125mV, which is a wide dynamic
range. This is due to the reliable static gate structures; 2) at all VDD points the synchronous design
has better result in active energy and leakage power. This is due to the smaller area of
synchronous design. The average performance data of the two designs are similar. At ultra-low
voltages, the performance penalty of NCL’s four-phase handshaking protocol is less critical since
the data processing time inside logic gates becomes significantly longer. In fact, it is expected that
if process variation factors are taken into account, the NCL design should have substantial
advantage in performance over the synchronous design. The clock period of synchronous design
needs to account for the worst-case pipeline stage delay, but the NCL handshaking protocol
absorbs delay variations across all stages and exhibits average-case performance.
Table 2. Bulk-Si Static Design Comparison
VDD
(mV)
Active Energy
(pJ)
Leakage Power
(nW)
Average Performance
(µS)
Synchronous NCL Synchronous NCL Synchronous NCL
500 48 119 697 1121 1 0.6
300 59 195 304 516 10 11.8
200 246 255 176 296 100 85.6
150 341 469 114 207 200 234.7
125 417 602 99 168 300 377.5
115 Failure Failure Failure Failure Failure Failure
Table 3 shows the comparison between the two bulk-Si Schmitt-triggered designs. Several
observations can be made: 1) both designs operate at lower VDD points than static counterparts.
This is due to the Schmitt-triggered gate structure; 2) the NCL design has a wider dynamic range
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
8
than the synchronous design because of its robust timing requirement; 3) the active energy,
leakage power, and the average performance data of the two designs are comparable, while the
NCL design is slightly better. This means under ultra-low VDD, energy and delay caused by the
Schmitt-triggered structure inside each gate are dominant factors compared to the logic portion.
Table 3. Bulk-Si Schmitt Design Comparison
VDD
(mV)
Active Energy
(pJ)
Leakage Power
(nW)
Average Performance
(µS)
Synchronous NCL Synchronous NCL Synchronous NCL
125 Failure Failure Failure Failure Failure Failure
115 Failure 12680 Failure 293 Failure 4500
100 Failure 15160 Failure 252 Failure 6303
90 17070 14060 257 223 5000 6630
80 13137 12980 227 196 10000 7013
75 Failure 12440 Failure 182 Failure 7249
70 Failure Failure Failure Failure Failure Failure
Table 4 shows the comparison between the two FD-SOI static designs. Several observations can
be made: 1) both designs function properly from 1V VDD to 150mV, which is a wide dynamic
range. This is again due to the reliable static gate structures; 2) the active energy, leakage power,
and the average performance data of the two designs are comparable at 500mV VDD, while the
NCL design is much better at 150mV VDD. However, as stated before, these data are less accurate
(e.g., the active energy data for the Boolean design at 150mV VDD) due to the use of a less-
accurate simulation mode.
Table 4. FD-SOI Static Design Comparison
VDD
(mV)
Active Energy
(pJ)
Leakage Power
(nW)
Average Performance
(µS)
Synchronous NCL Synchronous NCL Synchronous NCL
500 162 183 398 358 1 0.7
150 557 114 33 22 1000 347.8
115 Failure Failure Failure Failure Failure Failure
Table 5 shows the comparison between the two FD-SOI Schmitt-triggered designs. The two
designs have different dynamic ranges, which only overlap at 125mV VDD. As mentioned
previously, data from the FD-SOI process are less accurate (e.g., the average performance data
for the NCL design at 150mV VDD) due to the use of a less-accurate simulation mode.
Table 5. FD-SOI Schmitt Design Comparison
VDD
(mV)
Active Energy
(pJ)
Leakage Power
(nW)
Average Performance
(µS)
Synchronous NCL Synchronous NCL Synchronous NCL
200 Failure Failure Failure Failure Failure Failure
150 Failure 17950 Failure 151 Failure 12571
125 4655 12130 70 150 5000 8674
100 6515 Failure 50 Failure 10000 Failure
90 5239 Failure 41 Failure 10000 Failure
80 Failure Failure Failure Failure Failure Failure
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
9
3. CONCLUSIONS
This paper presents a comparative study of three potential circuit design techniques for ultra-low
voltage digital circuits, i.e., Fully-Depleted Silicon-on-Insulator, delay-insensitive asynchronous
logic (specifically, the NULL Convention Logic), and Schmitt-triggered gate structure. Eight
IEEE single-precision floating-point coprocessors have been designed applying different
combinations of these three techniques. IBM 8RF 130nm process is used as the example of bulk-
Si process, and MIT Lincoln Lab’s xLP FD-SOI 150nm process is used as the example of FD-
SOI process.
Cadence UltraSim simulation results show that 1) the static designs have much wider dynamic
ranges than the Schmitt-triggered designs; 2) the Schmitt-triggered designs are capable of
operating at much lower VDD points than the static designs; 3) the bulk-Si static synchronous
design has better energy and power figures than the NCL counterpart, while the performance of
the two is comparable; 4) the bulk-Si Schmitt-triggered NCL design has wider dynamic range
than the synchronous counterpart, while the energy/power/performance figures of the two are
comparable; and 5) due to convergence problem, the FD-SOI designs are simulated using a less-
accurate mode, thereby the data presented can only be used for reference purpose.
Overall, all these combinations are viable for designing ultra-low voltage digital circuits. For a
given application, the optimum circuit design methodology can be selected from these
combinations based on the lowest voltage, the dynamic range, the power budget, the performance
requirement, and the available semiconductor process node.
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10. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012
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Authors
Aaron Arthurs received B.S. and M.S. degrees in Computer Engineering from the
University of Arkansas in 2004 and 2007, respectively. He is currently a Ph.D. student in
Computer Engineering at the same university. His research interests include digital IC
design for ultra-low power, extreme environment, and embedded systems.
Justin Roark received B.S. degree in Electrical Engineering from the University of Arkansas in 2011. He is
currently a M.S. student in Computer Engineering at the same university. His research interests include
delay-insensitive asynchronous IC design for ultra-low power and radiation hardness.
Dr. Jia Di received his B.S. and M.S. degrees from Tsinghua University, Beijing, China,
in 1997 and 2000, respectively, and his Ph.D. in Electrical Engineering from the
University of Central Florida, USA, in the year of 2004. He is currently an Associate
Professor in the Computer Science and Computer Engineering department of the
University of Arkansas. His research interests include asynchronous logic circuit design
for ultra-low power, extreme temperature, radiation-hardening, and hardware security.