CMOS technology has achieved the device dimension in the nanometer range. Beyond this CMOS technology is the QCA (Quantum-dot Cellular Automata). Due to nanoscale defects may occur in this technology so in the consequences of it the faults will occur. This paper presents the defect analysis of QCA basic devices like Majority Voter (MV), inverter. The defect analysis and its effects on the output of combinational circuit using Hardware Description Language for QCA (HDLQ) is presented in this paper.
A parity generator is a circuit that generates redundant bits used for error detection
and is used when transmitting binary information. Previous parity generator circuits
based on quantum-dot cellular automata (QCA) are designed to reduce the area of the
circuit. Input cells of existing circuit are designed inside the circuit and the circuit’s
signal is not propagated properly due to the influence between adjacent wires. In
addition, existing circuits consume many clocks because the XOR gate, which is an
essential component of the parity generator circuit, consumes many clocks. In order to
solve this problem, we design a 3-bit odd parity generator circuit using QCA for fast
operation. The proposed circuit uses an XOR gate that can operate one clock faster
than the existing XOR gate to reduce the clock, and by extending this XOR gate, the
output value can be obtained faster than the conventional circuit. In the proposed
circuit, the result is verified through simulation and the performance is compared with
the existing circuit
DESIGNING AN EFFICIENT APPROACH FOR JK AND T FLIP-FLOP WITH POWER DISSIPATION...VLSICS Design
QCA (Quantum Dot Cellular Automata) is an emerging and pioneer technology, which is a paradigm for
computing with interacting quantum dots. Many eminent researchers have well thought of eloquent work in
the existing areas of the sequential circuit. However, this paper proclaims three new approaches to design
JK and T flip-flop. Since flip-flops and memory design are the crucial building blocks of digital circuits,
therefore we concern the underlying principle of fundamental design of JK and T flip-flop and then work
out to model the new structure favorable with the forthcoming excellence required. This new concept
places elsewhere the need of using feedback path in flip flop design. Also two algorithms have been shown
for explanatory purpose. The proposed structure is able to establish the validity and genuineness than
earlier design. By using the proposed T flip-flop, a 2-bit and 3-bit counter is also designed in the paper.
The simulation result of the proposed design proves their vigorousness and correctness in the output.
Design of Binary to BCD Code Converter using Area Optimized Quantum Dot Cellu...CSCJournals
The Integrated Circuit Technology (IC) is growing day to day to improve circuit performance and density for compact systems. A novel technology, Quantum dot Cellular Automata (QCA) was introduced to overcome the scaling limitations of CMOS technology. In order to bring a new paradigm of IC design in an efficient and optimized manner, a binary to BCD code converter is designed using QCA technology based area optimized adder. It is observed that the proposed binary to BCD code converter design gives better results in terms of the area and number of QCA cells. The results obtained by the proposed design shows that 61% of area reduced compared to boolean expression based design, this design is further optimized to reduce the QCA cell count by 45% with respect to the design in [1].
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
call for paper 2012, hard copy of journal, research paper publishing, where to publish research paper,
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals
New Two Simple Sinusoidal Generators with Four 45 Phase Shifted Voltage Outp...IJECEIAES
Two new 45 o phase shifted sinusoidal oscillator configurations employing single Second Generation Fully Differential Current Conveyor (FDCCII), two grounded capacitors and two grounded resistors are presented. The proposed oscillators can provide four sinusoidal voltage outputs with each a 45 o phase difference. These circuits can also be utilized as voltage-mode quadrature oscillators. Additional output stages incorporation in FDCCII can also result in current outputs spaced 45 degree apart. The proposed circuits enjoy the simplicity and less passive and active component. The Total Harmonic Distortion (THD) of the output waveforms was reasonability values (less than 4.5%). The circuits can supply two equi-quadrature outputs and the Lissajous patterns confirm the quadrature voltage output waveforms. The workability of the circuits is simulated by PSPICE 0.18 µm CMOS technology. The non-ideal analysis and simulation results verifying theoretical analyses are also investigated.
This paper proposes an asymmetrical cascaded single phase H-bridge inverter. The proposed inverter consists of two modules with unequal and isolated dc sources. Each module is composed of dc source, conventional four switches H-bridge and single bidirectional switch. To increase the output voltage levels, the tertiary ratio, 1:3, between its two dc sources is adopted. Both the fundamental frequency and the multicarrier pulse width modulation (PWM) control schemes are employed to generate switches signals. By controlling the inverter modulation index, the proposed inverter can generate an output voltage having up to seventeen levels by using only two modules. The proposed topology has also the feature of modularity which means that it can be extended to any levels by adding new modules. The proposed topology is simulated using an inductive load and some selected simulation results have been provided to validate the proposed inverter.
A parity generator is a circuit that generates redundant bits used for error detection
and is used when transmitting binary information. Previous parity generator circuits
based on quantum-dot cellular automata (QCA) are designed to reduce the area of the
circuit. Input cells of existing circuit are designed inside the circuit and the circuit’s
signal is not propagated properly due to the influence between adjacent wires. In
addition, existing circuits consume many clocks because the XOR gate, which is an
essential component of the parity generator circuit, consumes many clocks. In order to
solve this problem, we design a 3-bit odd parity generator circuit using QCA for fast
operation. The proposed circuit uses an XOR gate that can operate one clock faster
than the existing XOR gate to reduce the clock, and by extending this XOR gate, the
output value can be obtained faster than the conventional circuit. In the proposed
circuit, the result is verified through simulation and the performance is compared with
the existing circuit
DESIGNING AN EFFICIENT APPROACH FOR JK AND T FLIP-FLOP WITH POWER DISSIPATION...VLSICS Design
QCA (Quantum Dot Cellular Automata) is an emerging and pioneer technology, which is a paradigm for
computing with interacting quantum dots. Many eminent researchers have well thought of eloquent work in
the existing areas of the sequential circuit. However, this paper proclaims three new approaches to design
JK and T flip-flop. Since flip-flops and memory design are the crucial building blocks of digital circuits,
therefore we concern the underlying principle of fundamental design of JK and T flip-flop and then work
out to model the new structure favorable with the forthcoming excellence required. This new concept
places elsewhere the need of using feedback path in flip flop design. Also two algorithms have been shown
for explanatory purpose. The proposed structure is able to establish the validity and genuineness than
earlier design. By using the proposed T flip-flop, a 2-bit and 3-bit counter is also designed in the paper.
The simulation result of the proposed design proves their vigorousness and correctness in the output.
Design of Binary to BCD Code Converter using Area Optimized Quantum Dot Cellu...CSCJournals
The Integrated Circuit Technology (IC) is growing day to day to improve circuit performance and density for compact systems. A novel technology, Quantum dot Cellular Automata (QCA) was introduced to overcome the scaling limitations of CMOS technology. In order to bring a new paradigm of IC design in an efficient and optimized manner, a binary to BCD code converter is designed using QCA technology based area optimized adder. It is observed that the proposed binary to BCD code converter design gives better results in terms of the area and number of QCA cells. The results obtained by the proposed design shows that 61% of area reduced compared to boolean expression based design, this design is further optimized to reduce the QCA cell count by 45% with respect to the design in [1].
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
call for paper 2012, hard copy of journal, research paper publishing, where to publish research paper,
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals
New Two Simple Sinusoidal Generators with Four 45 Phase Shifted Voltage Outp...IJECEIAES
Two new 45 o phase shifted sinusoidal oscillator configurations employing single Second Generation Fully Differential Current Conveyor (FDCCII), two grounded capacitors and two grounded resistors are presented. The proposed oscillators can provide four sinusoidal voltage outputs with each a 45 o phase difference. These circuits can also be utilized as voltage-mode quadrature oscillators. Additional output stages incorporation in FDCCII can also result in current outputs spaced 45 degree apart. The proposed circuits enjoy the simplicity and less passive and active component. The Total Harmonic Distortion (THD) of the output waveforms was reasonability values (less than 4.5%). The circuits can supply two equi-quadrature outputs and the Lissajous patterns confirm the quadrature voltage output waveforms. The workability of the circuits is simulated by PSPICE 0.18 µm CMOS technology. The non-ideal analysis and simulation results verifying theoretical analyses are also investigated.
This paper proposes an asymmetrical cascaded single phase H-bridge inverter. The proposed inverter consists of two modules with unequal and isolated dc sources. Each module is composed of dc source, conventional four switches H-bridge and single bidirectional switch. To increase the output voltage levels, the tertiary ratio, 1:3, between its two dc sources is adopted. Both the fundamental frequency and the multicarrier pulse width modulation (PWM) control schemes are employed to generate switches signals. By controlling the inverter modulation index, the proposed inverter can generate an output voltage having up to seventeen levels by using only two modules. The proposed topology has also the feature of modularity which means that it can be extended to any levels by adding new modules. The proposed topology is simulated using an inductive load and some selected simulation results have been provided to validate the proposed inverter.
Analogy Fault Model for Biquad Filter by Using Vectorisation Method ijcisjournal
In this paper a simple shortcoming model for a CMOS exchanged capacitor low pass channel is tried. The
exchanged capacitor (SC) low pass channel circuit is modularized into practical macros. These useful
macros incorporate OPAMP, switches and capacitors. The circuit is distinguished as flawed if the
recurrence reaction of the exchange capacity does not meet the configuration detail. The sign stream chart
(SFG) models of the considerable number of macros are investigated to get the broken exchange capacity
of the circuit under test (CUT). A CMOS exchanged capacitor low pass channel for sign recipient
applications is picked as a case to exhibit the testing of the simple shortcoming model. To find out error is
to calculate EIGEN values and EIGEN vectors is to detect the error of each component and parameters
Design of Quantum Dot Cellular Automata Based Parity Generator and Checker wi...VIT-AP University
Quantum-dot Cellular Automata is an alternative to CMOS technology for the future digital designs. When compared to its CMOS counterpart, it has extremely low power consumption, as there is no current flow in cell. The methodology of parity generator and checker is based on the parity generation and matched it at the receiver end. By using the parity match bits, the error in circuit can be sensed. In this paper, novel parity generator and detector circuit are introduced. The circuit is designed in single layer, minimum clock and minimum latency, which is achieved in QCA framework. The proposed circuits are better than the existing in terms of clock cycle delay, cell complexity and clock cycle utilize. The simulation of presented cell structures have been verified using QCA designer tool. In addition, QCA Probabilistic (QCAPro) tool is used to calculate the minimum, maximum and average energy dissipation aspect in proposed QCA circuit. Appropriate comparison table and power analysis is shown to prove that our proposed circuit is cost effective.
Design of a Low-Power 1.65 GBPS Data Channel for HDMI TransmitterVLSICS Design
This paper presents a design of low power data channel for application in High Definition Multimedia
Interface (HDMI) Transmitter circuit. The input is 10 bit parallel data and output is serial data at 1.65
Gbps. This circuit uses only a single frequency of serial clock input. All other timing signals are derived
within the circuit from the serial clock. This design has dedicated lines to disable and enable all its
channels within two pixel-clock periods only. A pair of disable and enable functions performed
immediately after power-on of the circuit serves as the reset function. The presented design is immune to
data-dependent switching spikes in supply current and pushes them in the range of serial frequency and its
multiples. Thus filtering requirements are relaxed. The output stage uses a bias voltage of 2.8 volts for a
receiver pull-up voltage of 3.3 volts. The reported data channel is designed using UMC 180 nm CMOS
Technology. The design is modifiable for other inter-board serial interfaces like USB and LAN with
different number of bits at the parallel input.
Quantum-dot Cellular Automata (QCA) is an alternative innovation to the
Complementary Metal Oxide Semiconductor (CMOS) because CMOS has scaling
limitations that lead to high leakage power. QCA is structured on quantum cells, whose
sizes are on the nanoscale. This component causes faults in QCA circuits. Converting
a code into another that is programmed in logic arrays becomes important in the
physical realization of the circuits. There are many methods to resolve this problem in
circuits. A code converter is a solution to convert one code into another. In this paper,
QCA-based “4-bit binary-to-gray” and “4-bit gray-to-binary code converters” are
suggested. The offered layout prospects to a decrease in energy expenditure and can
be utilized in many fields for shielding data from outsiders and increasing information
flexibility. We executed a relative analysis of the suggested design with present earlier
designs and turned out that the suggested layout is productive on condition that
complexity, cell count, area intake, and clocking. This paper offers a streamlined design
and layout concerning code converters depending on QCA. These structures are
designed with the QCADesigner, simulator and the simulation results are examined.
A New Proposal for OFCC-based Instrumentation AmplifierYayah Zakaria
This contribution puts forward a new voltage mode instrumentation amplifier (VMIA) based on operational floating current conveyor (OFCC). It presents high impedance at input terminals and provides output at low impedance making the proposal ideal for voltage mode operation. The proposed VMIA
architecture has two stages - the first stage comprises of two OFCCs to sense input voltages and coverts the voltage difference to current while the second stage has single OFCC that converts the current to voltage. In addition it employs two resistors to provide gain and imposes no condition on the values
of resistors. The behavior of the proposed structure is also analyzed for OFCC non idealities namely finite transimpedance and tracking error. The proposal is verified through SPICE simulations using CMOS based schematic of OFCC. Experimental results, by bread boarding it using commercially available IC AD844, are also included.
Integrated Active Filters using low gain modulesIDES Editor
New integrated filters in CMOS technology are
presented which use current mirror based amplifiers to create
low gain modules as structural active blocks. The simplest
current amplifiers are purposely chosen. Wave techniques are
used for obtaining high reliability and low sensitivity filters
of any type. The derived filters are modular, simple in structure
and easy to design. Examples in simulation level are given
Modeling and simulation of fourteen bus system employing D-STATCOM for power ...IDES Editor
This work deals with modeling and simulation of
fourteen bus system employing D-STATCOM for power
quality improvement. The improvement in voltage stability
with D-STATCOM is presented. A 11 level inverter based DSTATCOM
is proposed to reduce the harmonics in the output.
Voltages at various buses with and without D-STATCOM are
presented. The simulation results are compared with the
analytical results.
DESIGN OF A HIGH PRECISION, WIDE RANGED ANALOG CLOCK GENERATOR WITH FIELD PRO...VLSICS Design
This paper presents a circuit of a high-precision, wide ranged, analog clock generator with on-chip programmability feature using Floating-gate transistors. The programmable oscillator can attain a continuous range of time-periods lying in the programming precision range of Floating Gates. The circuit consists of two sub circuits: Current Generator circuit and Wave Generator circuit. The current of current generator circuit is programmable and mirrored to the wave generator to generate the desired square wave. The topology is well suited to applications like clocking high performance ADCs and DACs as well as used as the internal clock in structured analog CMOS designs. A simulation model of the circuit was built in T-Spice, 0.35µm CMOS process. The circuit results in finely tuned clock with programmability precision of about 13bit [1]. Simulation results show high amount of temperature insensitivity (0.507ns/°C) for a large range of thermal conditions. The proposed circuit can compensate any change in temperature. The circuit design can be operated at low supply voltage i.e., 1v.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Experimental Study of SBPWM for Z-Source Inverter Five PhaseIAES-IJPEDS
On the basis of a conventional Z-source inverter, this paper presents an extension of the existing study about a driving scheme implementation of a simple boost pulse width modulation under open loop system for five phase two level system. The impact of design parameter (fixed modulation index and switching frequency) versus performance parameter (capacitor voltage, inductor current, total harmonic distortion and DC link voltage) are studied and analysed. To validate the advantages of Z-source five-phase inverter, the driving scheme are simulated using Matlab/Simulink and verified with real- time target board eZdspTMTMS320F28335. From the study, it was found that under specified modulation index and switching frequency, the THD of an output current fulfilled the EN61000-3-2 standard.
Dual output DC-DC quasi impedance source converterIJECEIAES
A double output port DC-DC quasi impedance source converter (q-ZSC) is proposed. Each of the outputs has a different voltage gain. One of the outputs is capable of bidirectional (four-quadrant) operation by only varying the duty ratio. The second output has the gain of traditional two-switch buck-boost converter. Operation of the converter was verified by simulating its responses for different input voltages and duty ratios using MATLAB SIMULINK software. Its average steady-state output current and voltage values were determined and used to determine the ripples that existed. These ripples are less than 5% of the average steady-state values for all the input voltage and duty ratio ranges considered.
A New Multilevel Inverter with Reduced Number of SwitchesIAES-IJPEDS
In recent day’s Multilevel inverter (MLI) technologies become a incredibly main choice in the area of high power medium voltage energy control. Though multilevel inverter has a number of advantages it has drawbacks in the vein of higher levels because of using more number of semiconductor switches. This may leads to vast size and price of the inverter is very high. So in order to overcome this problem the new multilevel inverter is proposed with reduced number of switches. The proposed method is well suited for a high power application and it built with three Dc sources and six Switches. Multi carrier pwm technique is used for sine wave generation. The results are validated through the harmonic spectrum of the FFT window by using Matlab/simulink. The result of the proposed MLI is compared with the conventional MLI and other seven level existing topologies.
Improved performance with fractional order control for asymmetrical cascaded ...journalBEEI
This paper proposes a control scheme for seven level asymmetrical cascaded H-bridge multi level inverter (ACHBMLI) based on fractional order calculus. The seven level ACHBMLI consists of two H-bridges that are connected in series and are excited by different dc voltage sources. A simplified model is developed by assuming the small signal variation component is equal in both the H-bridges. A fractional order PID (FO-PID) controller is designed for the ACHBMLI using the simplified model. Simulation study shows the adequacy of FO-PID controller in giving an output voltage with minimum distortions. A conventional PID controller is also designed for ACHBMLI using the same simplified model. The performance of the ACHBMLI with FO-PID controller is compared with the performance of ACHBMLI with conventional PID controller. The simulation results prove the superiority of FO-PID controller in maintaining the output voltage of the ACHBMLI close to the reference voltage and in reducing the harmonic distortion of output voltage of the inverter. The simulation was done using MATLAB and the parameters of FO-PID controller was designed using FOMCON tool box.
Nanotechnology in Semiconductor Nanostructure.
Presentation on "Quantum Dot", was performed under the Subject "QUANTUM PHENOMENA IN NANOSTRUCTURES" at AIUB. The simulation is done from a website nanoHUB which stands for online simulation for nanotechnology- https://nanohub.org/
Analogy Fault Model for Biquad Filter by Using Vectorisation Method ijcisjournal
In this paper a simple shortcoming model for a CMOS exchanged capacitor low pass channel is tried. The
exchanged capacitor (SC) low pass channel circuit is modularized into practical macros. These useful
macros incorporate OPAMP, switches and capacitors. The circuit is distinguished as flawed if the
recurrence reaction of the exchange capacity does not meet the configuration detail. The sign stream chart
(SFG) models of the considerable number of macros are investigated to get the broken exchange capacity
of the circuit under test (CUT). A CMOS exchanged capacitor low pass channel for sign recipient
applications is picked as a case to exhibit the testing of the simple shortcoming model. To find out error is
to calculate EIGEN values and EIGEN vectors is to detect the error of each component and parameters
Design of Quantum Dot Cellular Automata Based Parity Generator and Checker wi...VIT-AP University
Quantum-dot Cellular Automata is an alternative to CMOS technology for the future digital designs. When compared to its CMOS counterpart, it has extremely low power consumption, as there is no current flow in cell. The methodology of parity generator and checker is based on the parity generation and matched it at the receiver end. By using the parity match bits, the error in circuit can be sensed. In this paper, novel parity generator and detector circuit are introduced. The circuit is designed in single layer, minimum clock and minimum latency, which is achieved in QCA framework. The proposed circuits are better than the existing in terms of clock cycle delay, cell complexity and clock cycle utilize. The simulation of presented cell structures have been verified using QCA designer tool. In addition, QCA Probabilistic (QCAPro) tool is used to calculate the minimum, maximum and average energy dissipation aspect in proposed QCA circuit. Appropriate comparison table and power analysis is shown to prove that our proposed circuit is cost effective.
Design of a Low-Power 1.65 GBPS Data Channel for HDMI TransmitterVLSICS Design
This paper presents a design of low power data channel for application in High Definition Multimedia
Interface (HDMI) Transmitter circuit. The input is 10 bit parallel data and output is serial data at 1.65
Gbps. This circuit uses only a single frequency of serial clock input. All other timing signals are derived
within the circuit from the serial clock. This design has dedicated lines to disable and enable all its
channels within two pixel-clock periods only. A pair of disable and enable functions performed
immediately after power-on of the circuit serves as the reset function. The presented design is immune to
data-dependent switching spikes in supply current and pushes them in the range of serial frequency and its
multiples. Thus filtering requirements are relaxed. The output stage uses a bias voltage of 2.8 volts for a
receiver pull-up voltage of 3.3 volts. The reported data channel is designed using UMC 180 nm CMOS
Technology. The design is modifiable for other inter-board serial interfaces like USB and LAN with
different number of bits at the parallel input.
Quantum-dot Cellular Automata (QCA) is an alternative innovation to the
Complementary Metal Oxide Semiconductor (CMOS) because CMOS has scaling
limitations that lead to high leakage power. QCA is structured on quantum cells, whose
sizes are on the nanoscale. This component causes faults in QCA circuits. Converting
a code into another that is programmed in logic arrays becomes important in the
physical realization of the circuits. There are many methods to resolve this problem in
circuits. A code converter is a solution to convert one code into another. In this paper,
QCA-based “4-bit binary-to-gray” and “4-bit gray-to-binary code converters” are
suggested. The offered layout prospects to a decrease in energy expenditure and can
be utilized in many fields for shielding data from outsiders and increasing information
flexibility. We executed a relative analysis of the suggested design with present earlier
designs and turned out that the suggested layout is productive on condition that
complexity, cell count, area intake, and clocking. This paper offers a streamlined design
and layout concerning code converters depending on QCA. These structures are
designed with the QCADesigner, simulator and the simulation results are examined.
A New Proposal for OFCC-based Instrumentation AmplifierYayah Zakaria
This contribution puts forward a new voltage mode instrumentation amplifier (VMIA) based on operational floating current conveyor (OFCC). It presents high impedance at input terminals and provides output at low impedance making the proposal ideal for voltage mode operation. The proposed VMIA
architecture has two stages - the first stage comprises of two OFCCs to sense input voltages and coverts the voltage difference to current while the second stage has single OFCC that converts the current to voltage. In addition it employs two resistors to provide gain and imposes no condition on the values
of resistors. The behavior of the proposed structure is also analyzed for OFCC non idealities namely finite transimpedance and tracking error. The proposal is verified through SPICE simulations using CMOS based schematic of OFCC. Experimental results, by bread boarding it using commercially available IC AD844, are also included.
Integrated Active Filters using low gain modulesIDES Editor
New integrated filters in CMOS technology are
presented which use current mirror based amplifiers to create
low gain modules as structural active blocks. The simplest
current amplifiers are purposely chosen. Wave techniques are
used for obtaining high reliability and low sensitivity filters
of any type. The derived filters are modular, simple in structure
and easy to design. Examples in simulation level are given
Modeling and simulation of fourteen bus system employing D-STATCOM for power ...IDES Editor
This work deals with modeling and simulation of
fourteen bus system employing D-STATCOM for power
quality improvement. The improvement in voltage stability
with D-STATCOM is presented. A 11 level inverter based DSTATCOM
is proposed to reduce the harmonics in the output.
Voltages at various buses with and without D-STATCOM are
presented. The simulation results are compared with the
analytical results.
DESIGN OF A HIGH PRECISION, WIDE RANGED ANALOG CLOCK GENERATOR WITH FIELD PRO...VLSICS Design
This paper presents a circuit of a high-precision, wide ranged, analog clock generator with on-chip programmability feature using Floating-gate transistors. The programmable oscillator can attain a continuous range of time-periods lying in the programming precision range of Floating Gates. The circuit consists of two sub circuits: Current Generator circuit and Wave Generator circuit. The current of current generator circuit is programmable and mirrored to the wave generator to generate the desired square wave. The topology is well suited to applications like clocking high performance ADCs and DACs as well as used as the internal clock in structured analog CMOS designs. A simulation model of the circuit was built in T-Spice, 0.35µm CMOS process. The circuit results in finely tuned clock with programmability precision of about 13bit [1]. Simulation results show high amount of temperature insensitivity (0.507ns/°C) for a large range of thermal conditions. The proposed circuit can compensate any change in temperature. The circuit design can be operated at low supply voltage i.e., 1v.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Experimental Study of SBPWM for Z-Source Inverter Five PhaseIAES-IJPEDS
On the basis of a conventional Z-source inverter, this paper presents an extension of the existing study about a driving scheme implementation of a simple boost pulse width modulation under open loop system for five phase two level system. The impact of design parameter (fixed modulation index and switching frequency) versus performance parameter (capacitor voltage, inductor current, total harmonic distortion and DC link voltage) are studied and analysed. To validate the advantages of Z-source five-phase inverter, the driving scheme are simulated using Matlab/Simulink and verified with real- time target board eZdspTMTMS320F28335. From the study, it was found that under specified modulation index and switching frequency, the THD of an output current fulfilled the EN61000-3-2 standard.
Dual output DC-DC quasi impedance source converterIJECEIAES
A double output port DC-DC quasi impedance source converter (q-ZSC) is proposed. Each of the outputs has a different voltage gain. One of the outputs is capable of bidirectional (four-quadrant) operation by only varying the duty ratio. The second output has the gain of traditional two-switch buck-boost converter. Operation of the converter was verified by simulating its responses for different input voltages and duty ratios using MATLAB SIMULINK software. Its average steady-state output current and voltage values were determined and used to determine the ripples that existed. These ripples are less than 5% of the average steady-state values for all the input voltage and duty ratio ranges considered.
A New Multilevel Inverter with Reduced Number of SwitchesIAES-IJPEDS
In recent day’s Multilevel inverter (MLI) technologies become a incredibly main choice in the area of high power medium voltage energy control. Though multilevel inverter has a number of advantages it has drawbacks in the vein of higher levels because of using more number of semiconductor switches. This may leads to vast size and price of the inverter is very high. So in order to overcome this problem the new multilevel inverter is proposed with reduced number of switches. The proposed method is well suited for a high power application and it built with three Dc sources and six Switches. Multi carrier pwm technique is used for sine wave generation. The results are validated through the harmonic spectrum of the FFT window by using Matlab/simulink. The result of the proposed MLI is compared with the conventional MLI and other seven level existing topologies.
Improved performance with fractional order control for asymmetrical cascaded ...journalBEEI
This paper proposes a control scheme for seven level asymmetrical cascaded H-bridge multi level inverter (ACHBMLI) based on fractional order calculus. The seven level ACHBMLI consists of two H-bridges that are connected in series and are excited by different dc voltage sources. A simplified model is developed by assuming the small signal variation component is equal in both the H-bridges. A fractional order PID (FO-PID) controller is designed for the ACHBMLI using the simplified model. Simulation study shows the adequacy of FO-PID controller in giving an output voltage with minimum distortions. A conventional PID controller is also designed for ACHBMLI using the same simplified model. The performance of the ACHBMLI with FO-PID controller is compared with the performance of ACHBMLI with conventional PID controller. The simulation results prove the superiority of FO-PID controller in maintaining the output voltage of the ACHBMLI close to the reference voltage and in reducing the harmonic distortion of output voltage of the inverter. The simulation was done using MATLAB and the parameters of FO-PID controller was designed using FOMCON tool box.
Nanotechnology in Semiconductor Nanostructure.
Presentation on "Quantum Dot", was performed under the Subject "QUANTUM PHENOMENA IN NANOSTRUCTURES" at AIUB. The simulation is done from a website nanoHUB which stands for online simulation for nanotechnology- https://nanohub.org/
Quantum dots (QD) are semiconductors made via several possible routes. John Ashmead discusses how they are made, their properties and their applications in research.
Quantum Dot Light Emitting Diode
Introduction
Quantum dots (QD) or semiconductor Nano crystals could provide an alternative for commercial applications such as display technology. This display technology would be similar to organic light-emitting diode (OLED) displays, in that light would be supplied on demand, which would enable more efficient displays.
Quantum dots could support large, flexible displays. At present, they are used only to filter light from LEDs to backlight LCDs, rather than as actual displays. Properties and performance are determined by the size and/or composition of the QD. QDs are both photo-active (photo luminescent) and electro-active (electroluminescent) allowing them to be readily incorporated into new emissive display architectures.
Definition
QD-LED or QLED is considered as a next generation display technology after OLED-Displays.
“QLED means Quantum dot light emitting diodes and are a form of light emitting technology and consist of nano-scale crystals that can provide an alternative for applications such as display technology”. The light emitting centers are cadmium selenide (CdSe) nanocrystals, or quantum dots.
Charactristics
❀ QLEDs are a reliable, energy efficient, tunable color solution for display and lighting applications that reduce manufacturing costs, while employing ultra-thin, transparent or flexible materials.
❀ Quantum-dot-based LEDs are characterized by pure and saturated emission colors with narrow bandwidth.
❀ Their emission wavelength is easily tuned by changing the size of the quantum dots. Moreover, QD-LED offer high color purity and durability combined with the efficiency, flexibility, and low processing cost of organic light-emitting devices. QD-LED structure can be tuned over the entire visible wavelength range from 460 nm (blue) to 650 nm
❀ Due to spectrally narrow, tunable emission, and ease of processing, colloidal QDs are attractive materials for LED technologies.
Effect of Electron - Phonon Interaction on electron Spin Polarization in a q...optljjournal
This paper presents a theoretical model for the effect of electron
-
phonon interaction, temperature and
magnetic field on degree of electron spin polarization in GaAs/InAs quantum dot LED. To describe the
dynamics, quantum Langevin equation for photon numbe
r and carrier number is used. Simulation results
show that degree of electron spin polarization in quantum dot decreases with increase of electron phonon
interaction parameter at constant temperature and constant magnetic field which agrees with experiment
al results in literatures
Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Envi...VIT-AP University
Quantum-dot Cellular Automata (QCA) based reversible logic circuit has an enormous benefit over CMOS based logic circuit. As a promising technology for Nanoelectronics computing, reversible-QCA has gained more and more attention from researchers around the world. In this paper, a reversible authenticator circuit based on QCA was implemented. This article presents a Nano-authenticator circuit to verify the authenticated and unauthenticated inputs. The proposed QCA designs have been implemented in a different manner from existing designs, which are primarily based on a coplanar design approach. The efficiency of QCA design has been investigated based on parameters such as cell count, area, and latency. Furthermore, missing an additional cell defect of the reversible authenticator has been analyzed, and covers the fault tolerance of 60.41% and 75%, respectively. In addition, the proposed Feynman gate in QCA environment achieves 76.35% area, 12.5% cell count and 95.55% average energy dissipation improvement as compared to the existing layout. Moreover, the new reversible authentication circuit achieves 87.75% cost and 43.54% area improvement in comparison with the previous state-of-art design.
Analysis on Fault Mapping of Reversible Gates with Extended Hardware Descript...VIT-AP University
Quantum-dot cellular automata is a modern computing paradigm, conceived in feature of nanometer
scale with high integration density, and significant low power. For the QCA technology, making these
high-density design means an increase in the complexity which in turn leads to growth in the number of faults. The defect model presented in this paper categorized into two types, which include single missing and additional cell considering for QCA fault. Proposed gates have been designed in the
QCA and verified. The proposed Fredkin gate design has been compared with an existing design,
and 43% and 70% improvement in cell count and area respectively are revealed. Also, the Toffoli
design in QCA which achieve some parameters such as cell complexity of 39, and the average fault tolerance of 53.5%. The polarization value for both single cells missing an addition cell missing has been studied to explain the logic signal strength effect physically. A QCA framework for the 3-input
Ex-OR, 2:1 multiplexer, Fredkin, and Toffoli gate for the fault problem in which reliability analysis based on Hardware description language for QCA devices (HDLQ) is discussed and verified on the fault pattern look-up table.
An Explicit Cell-Based Nesting Robust Architecture and Analysis of Full AdderVIT-AP University
Moving towards micrometre scale to nanometre scale device shrinks down emerging nanometre technology such as quantum-dot cellular automata as a nesting
success. The introduced architecture is robust where the explicit design of full adder
and full subtraction uses for Ex-OR design. A new architecture of Ex-OR based on one majority gate is proposed, which its most optimized architecture and its placement of cells from the novel design. The analysis based on simulation showed that the
introduced Ex-OR and full adder makes only 11 and 46 cells count, respectively. In
proposed Ex-OR design, first output is received with no any latency which can be a
suitable design for implementation of the high-speed full adder design. In addition,
power estimation results are obtained after simulation of proposed designs in QCAPro
tool. Therefore, the novel designs improve the energy dissipation parameters such as mean leakage energy dissipation, mean switching energy dissipation and total energy dissipation 75, 11.28 and 82.19% in comparison with the most robust design in existing.
Two Bit Arithmetic Logic Unit (ALU) in QCAidescitation
Quantum cellular automata (QCA) is a new
technology in nanometre scale (<18nm) to support nano
technology. QCA is very effective in terms of high space density
and power dissipation and will be playing a major role in the
development of the Quantum computer with low power
consumption and high speed. This paper describes the design
and layout of a 2-bit ALU based on quantum-dot cellular
automata (QCA) using the QCADesigner design tool. The
ALU design is based on combinational circuits which reduces
the required hard-ware complexity and allows for reasonable
simulation times. The paper aims to provide evidence that
QCA has potential applications in future Quantum computers,
provided that the underlying technology is made feasible.
Design has been made using certain combinational circuits
by using Majority gate, AND, OR, NOT, X-OR in QCA. 2 bit
ALU needs the design of Logical Extender, Arithmetic
Extender and the Full adder circuits using QCA. The QCA is
a novel tool to realize Nano level digital devices and study and
analyze their various parameters.
Cost-effective architecture of decoder circuits and futuristic scope in the e...VIT-AP University
The goal of Very Large Scale Integration (VLSI) over the past several decades has been the miniaturisation of chip size, along with increased computing speed and decreased power consumption. Miniaturization of size, high computing speed, and low power consumption does not appear to be able to meet the demand of consumers at this time. Quantum dot cellular automata is a more promising methodology that has the potential to optimise power, speed, and area at the nano-computing scale. In the field of nanocomputing, combinational circuit design has seen a significant amount of research and development effort. This article presents a comprehensive review as well as a proposed design of a decoder that has an accurate clocking mechanism and the best design. In terms of cell count, total area, cell area, area coverage, latency, QCA cost, and quantum cost, the novel 2-to-4 decoder achieves values of 87, 0.10, 0.0281, 28.1, 2.5, 0.625, 0.25, which is better than the prior work. Comparing the 2-to-4 decoder design to a standard design, the improvement is 72.64 %, 80 %, 72.71 %, 28.1 %, 64.28 %, 97,44 and 92.85 % in cell count, total area, cell area, area coverage, latency, QCA cost, and Quantum cost, respectively.
Presentation of a fault tolerance algorithm for design of quantum-dot cellul...IJECEIAES
A novel algorithm for working out the Kink energy of quantum-dot cellular automata (QCA) circuits and their fault tolerability is introduced. In this algorithm at first with determining the input values on a specified design, the calculation between cells makes use of Kink physical relations will be managed. Therefore, the polarization of any cell and consequently output cell will be set. Then by determining missed cell(s) on the discussed circuit, the polarization of output cell will be obtained and by comparing it with safe state or software simulation, its fault tolerability will be proved. The proposed algorithm was implemented on a novel and advance fault tolerance full adder whose performance has been demonstrated. This algorithm could be implemented on any QCA circuit. Noticeably higher speed of the algorithm than simulation and traditional manual methods, expandability of this algorithm for variable circuits, beyond of four-dot square of QCA circuits, and the investigation of several damaged cells instead just one and special cell are the advantages of algorithmic action.
Design and Development of a Single Channel Analyzer with Microcontroller Base...IJAEMSJORNAL
Single Channel Analyzer (SCA) is a most common device used in today’s nuclear world. Therefore, A SCA with microcontroller based controlled output has been proposed in this article. The system comprises of Lower Level Discriminator (LLD), Upper Level Discriminator (ULD), wide dynamic range, Fast Processing and Hysteresis. The Comparator LM339N used as the key component that performs the main function of the proposed nuclear module. The multi-turn potentiometers have been used as LLD and ULD for the incoming linear pulses from shaping amplifier. The system has also employ the Hysteresis facilities so that oscillations due to stray feedback are not possible. A lower pin and less housing PIC microcontroller (P16F676) has been used to control the width and time delay of the output pulses.
Abstract: A technology called Quantum Dot Cellular Automata (QCA) offers a far more effective computational
platform than CMOS. Through the polarization of electrons, digital information is represented. In comparison to
CMOS technology, it is more attractive because to its size, faster speed, feature, high degree of scalability, greater
switching frequency, and low power consumption. This paper suggests structures of basic logic gates in the QCA
technology. For the aim of verification, the produced circuits aresimulated, and their results are then compared
to those of their published counterparts. The comparison outcomes provide hope for adding the suggested
structures to the collection of QCA gates.
Designing of an Energy-Efficient Nanoelectronics Architecture for Binary Comp...VIT-AP University
Quantum-dot cellular automata is a nanoscale computation circuit design approach which computes bits via charges
among quantum-dot in the quantum cell of QCA. This technology has promises the feature of energy efficient and high
density in the era of high-speed nanotechnology. This article contributes a new nanoscale design of binary comparator
with less latency, area, and clock utilized. The proposed comparator architecture is robust and enjoys wire crossing
without any crossover, which needs only normal and rotated cells. All the simulation results and calculated parameters
are based on the QCADesigner tool. QCAPro tool based approach has been used to perform the energy dissipation
estimation of the new comparator architecture. A better primitives results as compared to state-of-art technology has
been achieved and good contribution in this area.
A 20 Gb/s INJECTION-LOCKED CLOCK AND DATA RECOVERY CIRCUITVLSICS Design
This paper presents a 20 Gb/s injection-locked clock and data recovery (CDR) circuit for burst mode applications. Utilizing a half rate injection-locked oscillator (ILO) in the proposed CDR circuit leads to higher speed operation and lower power consumption. In addition, to accommodate process, voltage, and temperature (PVT) variations and to increase the lock range, a frequency locked loop is proposed to use in this circuit. The circuit is designed in 0.18 µm CMOS and the simulations for 27-1 pseudo random bit sequence (PRBS) show that the circuit consumes 55.3 mW at 20 Gb/s, while the recovered clock rms jitter is 1.1 ps.
Practical Implementation for Stator Faults Protection and Diagnosisin 3-Ph IM...theijes
This paper presents a real-time practical implementation for an online protection and diagnosis technique for induction motor stator faults. The Artificial Neural Network (ANN), the wavelet packet transform (WPT)- algorithms are developed as based approaches for protecting and diagnosing various stator faults occurring in three-phase induction motors. These approaches are based on the entropy of the WPT-coefficients of line currents using an optimized mother wavelet 'db3' at the second level of resolution with thresholds determined experimentally during the various conditions of the motor. The algorithm is implemented in real-time using the LabJack U3-HV instrument device as an interface between the WPT-algorithm which developed in Matlab program/PC and the 3-ph CT’s which are used to sense the 3-ph current lines motor. The proposed technique is tested on a laboratory induction motor which is chosen with unknown parameters. It is a rewinded motor that realizes a different requirement. It has many output terminals from its windings in order to implement the various faults. The online test results give a tripping signal at an instant time that through applied a new moving frame technique. A few cycles presents to isolate the main C.B of the motor power supply in all cases of faults. In addition, the WPT-algorithm is developed to issue online a flagging fault message window which helped to diagnose the faults type.
Submission Deadline: 30th September 2022
Acceptance Notification: Within Three Days’ time period
Online Publication: Within 24 Hrs. time Period
Expected Date of Dispatch of Printed Journal: 5th October 2022
MODELING AND ANALYSIS OF SURFACE ROUGHNESS AND WHITE LATER THICKNESS IN WIRE-...IAEME Publication
White layer thickness (WLT) formed and surface roughness in wire electric discharge turning (WEDT) of tungsten carbide composite has been made to model through response surface methodology (RSM). A Taguchi’s standard Design of experiments involving five input variables with three levels has been employed to establish a mathematical model between input parameters and responses. Percentage of cobalt content, spindle speed, Pulse on-time, wire feed and pulse off-time were changed during the experimental tests based on the Taguchi’s orthogonal array L27 (3^13). Analysis of variance (ANOVA) revealed that the mathematical models obtained can adequately describe performance within the parameters of the factors considered. There was a good agreement between the experimental and predicted values in this study.
A STUDY ON THE REASONS FOR TRANSGENDER TO BECOME ENTREPRENEURSIAEME Publication
The study explores the reasons for a transgender to become entrepreneurs. In this study transgender entrepreneur was taken as independent variable and reasons to become as dependent variable. Data were collected through a structured questionnaire containing a five point Likert Scale. The study examined the data of 30 transgender entrepreneurs in Salem Municipal Corporation of Tamil Nadu State, India. Simple Random sampling technique was used. Garrett Ranking Technique (Percentile Position, Mean Scores) was used as the analysis for the present study to identify the top 13 stimulus factors for establishment of trans entrepreneurial venture. Economic advancement of a nation is governed upon the upshot of a resolute entrepreneurial doings. The conception of entrepreneurship has stretched and materialized to the socially deflated uncharted sections of transgender community. Presently transgenders have smashed their stereotypes and are making recent headlines of achievements in various fields of our Indian society. The trans-community is gradually being observed in a new light and has been trying to achieve prospective growth in entrepreneurship. The findings of the research revealed that the optimistic changes are taking place to change affirmative societal outlook of the transgender for entrepreneurial ventureship. It also laid emphasis on other transgenders to renovate their traditional living. The paper also highlights that legislators, supervisory body should endorse an impartial canons and reforms in Tamil Nadu Transgender Welfare Board Association.
BROAD UNEXPOSED SKILLS OF TRANSGENDER ENTREPRENEURSIAEME Publication
Since ages gender difference is always a debatable theme whether caused by nature, evolution or environment. The birth of a transgender is dreadful not only for the child but also for their parents. The pain of living in the wrong physique and treated as second class victimized citizen is outrageous and fully harboured with vicious baseless negative scruples. For so long, social exclusion had perpetuated inequality and deprivation experiencing ingrained malign stigma and besieged victims of crime or violence across their life spans. They are pushed into the murky way of life with a source of eternal disgust, bereft sexual potency and perennial fear. Although they are highly visible but very little is known about them. The common public needs to comprehend the ravaged arrogance on these insensitive souls and assist in integrating them into the mainstream by offering equal opportunity, treat with humanity and respect their dignity. Entrepreneurship in the current age is endorsing the gender fairness movement. Unstable careers and economic inadequacy had inclined one of the gender variant people called Transgender to become entrepreneurs. These tiny budding entrepreneurs resulted in economic transition by means of employment, free from the clutches of stereotype jobs, raised standard of living and handful of financial empowerment. Besides all these inhibitions, they were able to witness a platform for skill set development that ignited them to enter into entrepreneurial domain. This paper epitomizes skill sets involved in trans-entrepreneurs of Thoothukudi Municipal Corporation of Tamil Nadu State and is a groundbreaking determination to sightsee various skills incorporated and the impact on entrepreneurship.
DETERMINANTS AFFECTING THE USER'S INTENTION TO USE MOBILE BANKING APPLICATIONSIAEME Publication
The banking and financial services industries are experiencing increased technology penetration. Among them, the banking industry has made technological advancements to better serve the general populace. The economy focused on transforming the banking sector's system into a cashless, paperless, and faceless one. The researcher wants to evaluate the user's intention for utilising a mobile banking application. The study also examines the variables affecting the user's behaviour intention when selecting specific applications for financial transactions. The researcher employed a well-structured questionnaire and a descriptive study methodology to gather the respondents' primary data utilising the snowball sampling technique. The study includes variables like performance expectations, effort expectations, social impact, enabling circumstances, and perceived risk. Each of the aforementioned variables has a major impact on how users utilise mobile banking applications. The outcome will assist the service provider in comprehending the user's history with mobile banking applications.
ANALYSE THE USER PREDILECTION ON GPAY AND PHONEPE FOR DIGITAL TRANSACTIONSIAEME Publication
Technology upgradation in banking sector took the economy to view that payment mode towards online transactions using mobile applications. This system enabled connectivity between banks, Merchant and user in a convenient mode. there are various applications used for online transactions such as Google pay, Paytm, freecharge, mobikiwi, oxygen, phonepe and so on and it also includes mobile banking applications. The study aimed at evaluating the predilection of the user in adopting digital transaction. The study is descriptive in nature. The researcher used random sample techniques to collect the data. The findings reveal that mobile applications differ with the quality of service rendered by Gpay and Phonepe. The researcher suggest the Phonepe application should focus on implementing the application should be user friendly interface and Gpay on motivating the users to feel the importance of request for money and modes of payments in the application.
VOICE BASED ATM FOR VISUALLY IMPAIRED USING ARDUINOIAEME Publication
The prototype of a voice-based ATM for visually impaired using Arduino is to help people who are blind. This uses RFID cards which contain users fingerprint encrypted on it and interacts with the users through voice commands. ATM operates when sensor detects the presence of one person in the cabin. After scanning the RFID card, it will ask to select the mode like –normal or blind. User can select the respective mode through voice input, if blind mode is selected the balance check or cash withdraw can be done through voice input. Normal mode procedure is same as the existing ATM.
IMPACT OF EMOTIONAL INTELLIGENCE ON HUMAN RESOURCE MANAGEMENT PRACTICES AMONG...IAEME Publication
There is increasing acceptability of emotional intelligence as a major factor in personality assessment and effective human resource management. Emotional intelligence as the ability to build capacity, empathize, co-operate, motivate and develop others cannot be divorced from both effective performance and human resource management systems. The human person is crucial in defining organizational leadership and fortunes in terms of challenges and opportunities and walking across both multinational and bilateral relationships. The growing complexity of the business world requires a great deal of self-confidence, integrity, communication, conflict and diversity management to keep the global enterprise within the paths of productivity and sustainability. Using the exploratory research design and 255 participants the result of this original study indicates strong positive correlation between emotional intelligence and effective human resource management. The paper offers suggestions on further studies between emotional intelligence and human capital development and recommends for conflict management as an integral part of effective human resource management.
VISUALISING AGING PARENTS & THEIR CLOSE CARERS LIFE JOURNEY IN AGING ECONOMYIAEME Publication
Our life journey, in general, is closely defined by the way we understand the meaning of why we coexist and deal with its challenges. As we develop the "inspiration economy", we could say that nearly all of the challenges we have faced are opportunities that help us to discover the rest of our journey. In this note paper, we explore how being faced with the opportunity of being a close carer for an aging parent with dementia brought intangible discoveries that changed our insight of the meaning of the rest of our life journey.
A STUDY ON THE IMPACT OF ORGANIZATIONAL CULTURE ON THE EFFECTIVENESS OF PERFO...IAEME Publication
The main objective of this study is to analyze the impact of aspects of Organizational Culture on the Effectiveness of the Performance Management System (PMS) in the Health Care Organization at Thanjavur. Organizational Culture and PMS play a crucial role in present-day organizations in achieving their objectives. PMS needs employees’ cooperation to achieve its intended objectives. Employees' cooperation depends upon the organization’s culture. The present study uses exploratory research to examine the relationship between the Organization's culture and the Effectiveness of the Performance Management System. The study uses a Structured Questionnaire to collect the primary data. For this study, Thirty-six non-clinical employees were selected from twelve randomly selected Health Care organizations at Thanjavur. Thirty-two fully completed questionnaires were received.
Living in 21st century in itself reminds all of us the necessity of police and its administration. As more and more we are entering into the modern society and culture, the more we require the services of the so called ‘Khaki Worthy’ men i.e., the police personnel. Whether we talk of Indian police or the other nation’s police, they all have the same recognition as they have in India. But as already mentioned, their services and requirements are different after the like 26th November, 2008 incidents, where they without saving their own lives has sacrificed themselves without any hitch and without caring about their respective family members and wards. In other words, they are like our heroes and mentors who can guide us from the darkness of fear, militancy, corruption and other dark sides of life and so on. Now the question arises, if Gandhi would have been alive today, what would have been his reaction/opinion to the police and its functioning? Would he have some thing different in his mind now what he had been in his mind before the partition or would he be going to start some Satyagraha in the form of some improvement in the functioning of the police administration? Really these questions or rather night mares can come to any one’s mind, when there is too much confusion is prevailing in our minds, when there is too much corruption in the society and when the polices working is also in the questioning because of one or the other case throughout the India. It is matter of great concern that we have to thing over our administration and our practical approach because the police personals are also like us, they are part and parcel of our society and among one of us, so why we all are pin pointing towards them.
A STUDY ON TALENT MANAGEMENT AND ITS IMPACT ON EMPLOYEE RETENTION IN SELECTED...IAEME Publication
The goal of this study was to see how talent management affected employee retention in the selected IT organizations in Chennai. The fundamental issue was the difficulty to attract, hire, and retain talented personnel who perform well and the gap between supply and demand of talent acquisition and retaining them within the firms. The study's main goals were to determine the impact of talent management on employee retention in IT companies in Chennai, investigate talent management strategies that IT companies could use to improve talent acquisition, performance management, career planning and formulate retention strategies that the IT firms could use. The respondents were given a structured close-ended questionnaire with the 5 Point Likert Scale as part of the study's quantitative research design. The target population consisted of 289 IT professionals. The questionnaires were distributed and collected by the researcher directly. The Statistical Package for Social Sciences (SPSS) was used to collect and analyse the questionnaire responses. Hypotheses that were formulated for the various areas of the study were tested using a variety of statistical tests. The key findings of the study suggested that talent management had an impact on employee retention. The studies also found that there is a clear link between the implementation of talent management and retention measures. Management should provide enough training and development for employees, clarify job responsibilities, provide adequate remuneration packages, and recognise employees for exceptional performance.
ATTRITION IN THE IT INDUSTRY DURING COVID-19 PANDEMIC: LINKING EMOTIONAL INTE...IAEME Publication
Globally, Millions of dollars were spent by the organizations for employing skilled Information Technology (IT) professionals. It is costly to replace unskilled employees with IT professionals possessing technical skills and competencies that aid in interconnecting the business processes. The organization’s employment tactics were forced to alter by globalization along with technological innovations as they consistently diminish to remain lean, outsource to concentrate on core competencies along with restructuring/reallocate personnel to gather efficiency. As other jobs, organizations or professions have become reasonably more appropriate in a shifting employment landscape, the above alterations trigger both involuntary as well as voluntary turnover. The employee view on jobs is also afflicted by the COVID-19 pandemic along with the employee-driven labour market. So, having effective strategies is necessary to tackle the withdrawal rate of employees. By associating Emotional Intelligence (EI) along with Talent Management (TM) in the IT industry, the rise in attrition rate was analyzed in this study. Only 303 respondents were collected out of 350 participants to whom questionnaires were distributed. From the employees of IT organizations located in Bangalore (India), the data were congregated. A simple random sampling methodology was employed to congregate data as of the respondents. Generating the hypothesis along with testing is eventuated. The effect of EI and TM along with regression analysis between TM and EI was analyzed. The outcomes indicated that employee and Organizational Performance (OP) were elevated by effective EI along with TM.
INFLUENCE OF TALENT MANAGEMENT PRACTICES ON ORGANIZATIONAL PERFORMANCE A STUD...IAEME Publication
By implementing talent management strategy, organizations would have the option to retain their skilled professionals while additionally working on their overall performance. It is the course of appropriately utilizing the ideal individuals, setting them up for future top positions, exploring and dealing with their performance, and holding them back from leaving the organization. It is employee performance that determines the success of every organization. The firm quickly obtains an upper hand over its rivals in the event that its employees having particular skills that cannot be duplicated by the competitors. Thus, firms are centred on creating successful talent management practices and processes to deal with the unique human resources. Firms are additionally endeavouring to keep their top/key staff since on the off chance that they leave; the whole store of information leaves the firm's hands. The study's objective was to determine the impact of talent management on organizational performance among the selected IT organizations in Chennai. The study recommends that talent management limitedly affects performance. On the off chance that this talent is appropriately management and implemented properly, organizations might benefit as much as possible from their maintained assets to support development and productivity, both monetarily and non-monetarily.
A STUDY OF VARIOUS TYPES OF LOANS OF SELECTED PUBLIC AND PRIVATE SECTOR BANKS...IAEME Publication
Banking regulations act of India, 1949 defines banking as “acceptance of deposits for the purpose of lending or investment from the public, repayment on demand or otherwise and withdrawable through cheques, drafts order or otherwise”, the major participants of the Indian financial system are commercial banks, the financial institution encompassing term lending institutions. Investments institutions, specialized financial institution and the state level development banks, non banking financial companies (NBFC) and other market intermediaries such has the stock brokers and money lenders are among the oldest of the certain variants of NBFC and the oldest market participants. The asset quality of banks is one of the most important indicators of their financial health. The Indian banking sector has been facing severe problems of increasing Non- Performing Assets (NPAs). The NPAs growth directly and indirectly affects the quality of assets and profitability of banks. It also shows the efficiency of banks credit risk management and the recovery effectiveness. NPA do not generate any income, whereas, the bank is required to make provisions for such as assets that why is a double edge weapon. This paper outlines the concept of quality of bank loans of different types like Housing, Agriculture and MSME loans in state Haryana of selected public and private sector banks. This study is highlighting problems associated with the role of commercial bank in financing Small and Medium Scale Enterprises (SME). The overall objective of the research was to assess the effect of the financing provisions existing for the setting up and operations of MSMEs in the country and to generate recommendations for more robust financing mechanisms for successful operation of the MSMEs, in turn understanding the impact of MSME loans on financial institutions due to NPA. There are many research conducted on the topic of Non- Performing Assets (NPA) Management, concerning particular bank, comparative study of public and private banks etc. In this paper the researcher is considering the aggregate data of selected public sector and private sector banks and attempts to compare the NPA of Housing, Agriculture and MSME loans in state Haryana of public and private sector banks. The tools used in the study are average and Anova test and variance. The findings reveal that NPA is common problem for both public and private sector banks and is associated with all types of loans either that is housing loans, agriculture loans and loans to SMES. NPAs of both public and private sector banks show the increasing trend. In 2010-11 GNPA of public and private sector were at same level it was 2% but after 2010-11 it increased in many fold and at present there is GNPA in some more than 15%. It shows the dark area of Indian banking sector.
EXPERIMENTAL STUDY OF MECHANICAL AND TRIBOLOGICAL RELATION OF NYLON/BaSO4 POL...IAEME Publication
An experiment conducted in this study found that BaSO4 changed Nylon 6's mechanical properties. By changing the weight ratios, BaSO4 was used to make Nylon 6. This Researcher looked into how hard Nylon-6/BaSO4 composites are and how well they wear. Experiments were done based on Taguchi design L9. Nylon-6/BaSO4 composites can be tested for their hardness number using a Rockwell hardness testing apparatus. On Nylon/BaSO4, the wear behavior was measured by a wear monitor, pinon-disc friction by varying reinforcement, sliding speed, and sliding distance, and the microstructure of the crack surfaces was observed by SEM. This study provides significant contributions to ultimate strength by increasing BaSO4 content up to 16% in the composites, and sliding speed contributes 72.45% to the wear rate
ROLE OF SOCIAL ENTREPRENEURSHIP IN RURAL DEVELOPMENT OF INDIA - PROBLEMS AND ...IAEME Publication
The majority of the population in India lives in villages. The village is the back bone of the country. Village or rural industries play an important role in the national economy, particularly in the rural development. Developing the rural economy is one of the key indicators towards a country’s success. Whether it be the need to look after the welfare of the farmers or invest in rural infrastructure, Governments have to ensure that rural development isn’t compromised. The economic development of our country largely depends on the progress of rural areas and the standard of living of rural masses. Village or rural industries play an important role in the national economy, particularly in the rural development. Rural entrepreneurship is based on stimulating local entrepreneurial talent and the subsequent growth of indigenous enterprises. It recognizes opportunity in the rural areas and accelerates a unique blend of resources either inside or outside of agriculture. Rural entrepreneurship brings an economic value to the rural sector by creating new methods of production, new markets, new products and generate employment opportunities thereby ensuring continuous rural development. Social Entrepreneurship has the direct and primary objective of serving the society along with the earning profits. So, social entrepreneurship is different from the economic entrepreneurship as its basic objective is not to earn profits but for providing innovative solutions to meet the society needs which are not taken care by majority of the entrepreneurs as they are in the business for profit making as a sole objective. So, the Social Entrepreneurs have the huge growth potential particularly in the developing countries like India where we have huge societal disparities in terms of the financial positions of the population. Still 22 percent of the Indian population is below the poverty line and also there is disparity among the rural & urban population in terms of families living under BPL. 25.7 percent of the rural population & 13.7 percent of the urban population is under BPL which clearly shows the disparity of the poor people in the rural and urban areas. The need to develop social entrepreneurship in agriculture is dictated by a large number of social problems. Such problems include low living standards, unemployment, and social tension. The reasons that led to the emergence of the practice of social entrepreneurship are the above factors. The research problem lays upon disclosing the importance of role of social entrepreneurship in rural development of India. The paper the tendencies of social entrepreneurship in India, to present successful examples of such business for providing recommendations how to improve situation in rural areas in terms of social entrepreneurship development. Indian government has made some steps towards development of social enterprises, social entrepreneurship, and social in- novation, but a lot remains to be improved.
OPTIMAL RECONFIGURATION OF POWER DISTRIBUTION RADIAL NETWORK USING HYBRID MET...IAEME Publication
Distribution system is a critical link between the electric power distributor and the consumers. Most of the distribution networks commonly used by the electric utility is the radial distribution network. However in this type of network, it has technical issues such as enormous power losses which affect the quality of the supply. Nowadays, the introduction of Distributed Generation (DG) units in the system help improve and support the voltage profile of the network as well as the performance of the system components through power loss mitigation. In this study network reconfiguration was done using two meta-heuristic algorithms Particle Swarm Optimization and Gravitational Search Algorithm (PSO-GSA) to enhance power quality and voltage profile in the system when simultaneously applied with the DG units. Backward/Forward Sweep Method was used in the load flow analysis and simulated using the MATLAB program. Five cases were considered in the Reconfiguration based on the contribution of DG units. The proposed method was tested using IEEE 33 bus system. Based on the results, there was a voltage profile improvement in the system from 0.9038 p.u. to 0.9594 p.u.. The integration of DG in the network also reduced power losses from 210.98 kW to 69.3963 kW. Simulated results are drawn to show the performance of each case.
APPLICATION OF FRUGAL APPROACH FOR PRODUCTIVITY IMPROVEMENT - A CASE STUDY OF...IAEME Publication
Manufacturing industries have witnessed an outburst in productivity. For productivity improvement manufacturing industries are taking various initiatives by using lean tools and techniques. However, in different manufacturing industries, frugal approach is applied in product design and services as a tool for improvement. Frugal approach contributed to prove less is more and seems indirectly contributing to improve productivity. Hence, there is need to understand status of frugal approach application in manufacturing industries. All manufacturing industries are trying hard and putting continuous efforts for competitive existence. For productivity improvements, manufacturing industries are coming up with different effective and efficient solutions in manufacturing processes and operations. To overcome current challenges, manufacturing industries have started using frugal approach in product design and services. For this study, methodology adopted with both primary and secondary sources of data. For primary source interview and observation technique is used and for secondary source review has done based on available literatures in website, printed magazines, manual etc. An attempt has made for understanding application of frugal approach with the study of manufacturing industry project. Manufacturing industry selected for this project study is Mahindra and Mahindra Ltd. This paper will help researcher to find the connections between the two concepts productivity improvement and frugal approach. This paper will help to understand significance of frugal approach for productivity improvement in manufacturing industry. This will also help to understand current scenario of frugal approach in manufacturing industry. In manufacturing industries various process are involved to deliver the final product. In the process of converting input in to output through manufacturing process productivity plays very critical role. Hence this study will help to evolve status of frugal approach in productivity improvement programme. The notion of frugal can be viewed as an approach towards productivity improvement in manufacturing industries.
A MULTIPLE – CHANNEL QUEUING MODELS ON FUZZY ENVIRONMENTIAEME Publication
In this paper, we investigated a queuing model of fuzzy environment-based a multiple channel queuing model (M/M/C) ( /FCFS) and study its performance under realistic conditions. It applies a nonagonal fuzzy number to analyse the relevant performance of a multiple channel queuing model (M/M/C) ( /FCFS). Based on the sub interval average ranking method for nonagonal fuzzy number, we convert fuzzy number to crisp one. Numerical results reveal that the efficiency of this method. Intuitively, the fuzzy environment adapts well to a multiple channel queuing models (M/M/C) ( /FCFS) are very well.
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.
We have compiled the most important slides from each speaker's presentation. This year’s compilation, available for free, captures the key insights and contributions shared during the DfMAy 2024 conference.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
HEAP SORT ILLUSTRATED WITH HEAPIFY, BUILD HEAP FOR DYNAMIC ARRAYS.
Heap sort is a comparison-based sorting technique based on Binary Heap data structure. It is similar to the selection sort where we first find the minimum element and place the minimum element at the beginning. Repeat the same process for the remaining elements.
Water billing management system project report.pdfKamal Acharya
Our project entitled “Water Billing Management System” aims is to generate Water bill with all the charges and penalty. Manual system that is employed is extremely laborious and quite inadequate. It only makes the process more difficult and hard.
The aim of our project is to develop a system that is meant to partially computerize the work performed in the Water Board like generating monthly Water bill, record of consuming unit of water, store record of the customer and previous unpaid record.
We used HTML/PHP as front end and MYSQL as back end for developing our project. HTML is primarily a visual design environment. We can create a android application by designing the form and that make up the user interface. Adding android application code to the form and the objects such as buttons and text boxes on them and adding any required support code in additional modular.
MySQL is free open source database that facilitates the effective management of the databases by connecting them to the software. It is a stable ,reliable and the powerful solution with the advanced features and advantages which are as follows: Data Security.MySQL is free open source database that facilitates the effective management of the databases by connecting them to the software.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
NUMERICAL SIMULATIONS OF HEAT AND MASS TRANSFER IN CONDENSING HEAT EXCHANGERS...ssuser7dcef0
Power plants release a large amount of water vapor into the
atmosphere through the stack. The flue gas can be a potential
source for obtaining much needed cooling water for a power
plant. If a power plant could recover and reuse a portion of this
moisture, it could reduce its total cooling water intake
requirement. One of the most practical way to recover water
from flue gas is to use a condensing heat exchanger. The power
plant could also recover latent heat due to condensation as well
as sensible heat due to lowering the flue gas exit temperature.
Additionally, harmful acids released from the stack can be
reduced in a condensing heat exchanger by acid condensation. reduced in a condensing heat exchanger by acid condensation.
Condensation of vapors in flue gas is a complicated
phenomenon since heat and mass transfer of water vapor and
various acids simultaneously occur in the presence of noncondensable
gases such as nitrogen and oxygen. Design of a
condenser depends on the knowledge and understanding of the
heat and mass transfer processes. A computer program for
numerical simulations of water (H2O) and sulfuric acid (H2SO4)
condensation in a flue gas condensing heat exchanger was
developed using MATLAB. Governing equations based on
mass and energy balances for the system were derived to
predict variables such as flue gas exit temperature, cooling
water outlet temperature, mole fraction and condensation rates
of water and sulfuric acid vapors. The equations were solved
using an iterative solution technique with calculations of heat
and mass transfer coefficients and physical properties.
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low. Since the information flow due to the interaction of cells, the speed can be
achieved up to THz. The dimensions of QCA cells will be very less, in nanometer so
higher device density can be achieved. [4]. Basically QCA consists of the array of
cells in which information hold and transfer from source to destination with the help
of the Coulombic interaction between cell to cell [5].
Due to the nanostructure of the cells of QCA, there is possibility of the occurrence
of defects in the QCA devices and circuits. At nanoscale, there are chances of defects
in QCA devices and systems. The survey on various defects is carried out in [6]. It is
discussed in section III. So it important to analyzed the defects in the QCA devices
and circuits. This analysis will helpful to decide fault model and testing of QCA
circuits. In this paper the QCA combinational circuit is implemented using Hardware
Description Language for QCA (HDLQ) [7]. Also the defects and fault effects on the
output of the QCA combinational circuit is analyzed using HDLQ.
The sections of paper is arranged as follows, section II contents the background of
the concepts of QCA. The defect classification and earlier work done is carried out in
section III. About the HDLQ and its features given in section IV. Defect analysis of
QCA combinational circuit is discussed in section V. Paper is concluded in section
VI.
2. BACKGROUND
QCA consists of array of cells in which each cell contains four, five or six quantum
dots depending upon the types. Two electrons are free to tunnel between the quantum
dots. The arrangement of quantum dot cell is shown in. Fig. 1. [8]. Four quantum dot
cell is shown in Fig.1. All four dots are positioned at the corners of a square cell.
(a) (b)
Figure 1 Four-dot QCA cell
Because of the Coulombic repulsion the electrons in the cell occupy antipodal
sites as shown in Fig. 1. Polarization of shown configuration is calculated using
equation 1 given below
4321
4231
P
1
According equation 1, the polarization for Fig.1. (a) is P=+1 and for Fig.1. (b) is
P=-1. Polarizations P=+1 and P=-1 are encoded as binary ‘1’ and ‘0’ respectively.
According to the material used for quantum dot to make QCA cell the types of
QCA are decided. The available types of QCA are magnetic, metal-islands, molecular
and semiconductor [8] [9] [10] [11]. Molecular QCA is the most capable type in
which single molecular can act as a cell. Small size molecular QCA cells are
fabricated using self-assembly process [12]. Magnetic and metal-island QCA can
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achieve the speed up to MHz while semiconductor and molecular QCA can achieve
the speed up to THz.
The basic building blocks of QCA are majority voter, inverter, binary wire, 450
inverter chain [13]. A majority gate is basic element which works as a logic gate in
QCA. It consists of three inputs and one output, as shown in Fig. 2. The Boolean
function of the majority gate is given as F = AB + BC + AC. The output of the
majority gate, as indicated by the name, is determined by the majority of its three
inputs. For example, if two of the inputs are low, the output will be a low. If two of
the inputs are high, then output will be a high. Here high refers to the polarization
state P = +1, and low refers to the polarization state P = -1. The truth table of a
majority gate covering all possible combination of inputs and corresponding output is
shown in Table 1.
Figure 2 QCA Majority Gate
Table 1 Truth table of majority gate
QCA inverter is shown in Fig.3, is another fundamental logic gate in QCA with
one input and one output. It takes the input logic and produces its inverse logic on
output. The truth table of it is given in Table 2. If the input is logic High, the output
will be Low. If the input is logic Low, the output will be high. So many
implementations are possible for inverter but the given one is robust implementation.
Figure 3 QCA Inverter
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Table 2 Truth table for QCA inverter
One can have conventional logic gates such as AND and OR gate using majority
gate. An AND gate and an OR gate can be easily built using a majority gate by fixing
one of its input to either low or high respectively. Fig. 4(a) shows a QCA design of a
two-input AND gate and Fig. 4(b) shows a QCA design of a two-input OR gate. The
truth tables of AND gate and OR gate are shown in Table 3(a) and (b) respectively.
Figure 4 QCA (a) AND gate (b) OR gate
Table 3 Truth table for AND and OR gate
A binary wire is used to transfer information from one part of the circuit to
another. In a QCA circuit, a wire not only helps in information transfer, it actually can
performs some computational operation on the information to be transferred. The two
basic types of wire in QCA are the normal wire and the inverter chain.
Figure 5 Binary QCA Wire
Figure 6 An Inverter 45o
chain
Coplanar wire crossing is possible in QCA unlike conventional CMOS. It enables
the QCA wire to cross in the plane without changing the value being transmitted on
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either wires. Coplanar wire crossing needs wires to be of different orientation, i.e.,
one of them should be of 90-degree orientation and other of 45-degree orientation.
Fig. 7. shows an example of coplanar wire crossing, where value of Input1 flows
towards Output1 and Output 2 determines the value of Input2.
Figure 7 Coplanar QCA wire crossing
Clocking in QCA provides the power gain. It is important in QCA circuit. In
clocking of QCA, clock signal is given to each cell [14]. Two types of clocking
schemes are possible for QCA one is abrupt clocking scheme and another is adiabatic
clocking scheme.
QCA has a clocking mechanism that consists of four clock signals with equal
frequencies. One of the clock signals can be considered the reference (phase = 0) and
the others are delayed one (phase = π/2), two (phase = π) and three (phase = 3π/2)
quarters of a period as shown in Fig. 8.
Figure 8 Clocking scheme
3. DEFECTS IN QCA
The defect classification is shown in Fig. 9. There are possibility of defect during
synthesis and deposition phase. In synthesis phase single cell is fabricated while in
deposition phase the cells are placed on substrate at desired location [15].
In synthesis phase dot size variation can occur. Also there is change in size of cell
in the synthesis phase. In the deposition phase cell misalignment, missing cell and
additional cell deposition defects can occur. In the cell misalignment deposition
defect, the cell can be misplaced from its defect free structure. In this defect cell can
be displaced from its original location in the QCA basic devices discussed in the
section II.
In the missing cell deposition defect the single or multiple cell can be missed in
the QCA device. In the additional cell deposition defects the extra cell is going to be
deposited nearer to the QCA device.
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Figure 9 Types of defect
The deposition defects are analyzed in molecular QCA devices and circuits in
[15]. This deposition may cause the missing cell or an additional cell which are nearer
to the layout or placed within the layout of a device. Extensive simulation and the
impact of missing cell and additional cell defects were evaluated for in the devices
like majority voter, inverter, different wire types like straight, L-shape, coplanar
crossing and fanout.
The misalignment and displacement defects are analyzed in [16, 17].
4. HARDWARE DESCRIPTION LANGUAGE FOR QCA
The layout design and simulator tool is available to observe the response of QCA
circuits named QCADesigner [18, 19]. The single missing cell defects can be
analysed using QCADesigner. To support and describe the logical behavior of the
circuit and system, hardware description language must be available. VHDL and
Verilog are two widely used HDLs. Synthesis using these languages consists basic,
universal gates since they are available as primitives. In QCA circuit and system the
basic elements are MV, inverter. QCA circuit is basically network of MVs and
inverters. So primitives of MV must be available. The hardware description language
for this kind of primitives of QCA is developed in [7]. This is known as HDLQ.
Apart from the QCA logical circuit synthesis which gives the combinations of
MVs and inverter using HDLQ, there has to be provision of analysis of defects or
faults discussed in section III. The developed HDLQ [7] also support this feature.
HDLQ allows the designer to verify the logic characteristics of a QCA system and the
unique features of QCA such as bidirectionality and timing/clocking partitioning as
well.
As given in [20] fault-injection involves the deliberate insertion of faults or errors
into a computer system to determine its response. Fault injection using HDLQ would
be done at the logical level.
1. Majority Voter primitive in HDLQ with fault injection capability Consider the
majority voter shown in Fig. 10.
Defects
Synthesis
Phase
Dot Size
Cell
Size/SpaceClock
Circuitary
Deposition
Phase
Misalignment
Lateral
Displacement
Rotation
Missing Cell
Additional Cell
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Figure 10 Majority voter
MV implements the function F (A, B, C) = AB+BC+AC. The single missing cell
and additional cell deposition defects carried in [15], MV has faults stuck_ at_ B
(s_a_B) and F (A’, B, C’). Two auxiliary inputs fault0 and fault1 are available in the
HDLQ MV primitive as shown in Fig. 11.
Fig.11. shows the synthesis result of HDLQ MV using Xillinx ISE tool. If fault0 =
0, fault1 = 0 then it is considered as the fault-free configuration. If fault0 = 0, fault1 =
1 then it is considered as the stuck-at-B fault. If fault0 = 1 and fault1 = 0 then it is
considered as the fault F (A’, B, C’).
Figure 11 Majority voter primitive synthesis using HDLQ
Simulation can be done by setting the values of auxiliary inputs fault0 and fault1
for the corresponding fault injection. Simulation results for fault S_a_B is shown in
Fig.12. Here the value of auxiliary inputs are, fault0=0 and fault1=1.
When input A=0, B=1 and C=0 the out (F) which is the majority of these must be
logic 0. Since the presence of S_a_B fault the out (F) is at logic 1.
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Figure 12 Simulation result for MV at S_a_B fault
The Table 4 shows the effect of output due to S_a_B fault for the various
combinations of input.
Table 4 Effect of S_a_B fault
A B C
F
Fault Free
F
Faulty
0 0 0 0 0
0 0 1 0 0
0 1 0 0 1
0 1 1 1 1
1 0 0 0 0
1 0 1 1 0
1 1 0 1 1
1 1 1 1 1
HDLQ supports the fault injection capabilities for all basic building blocks. Using
this feature of HDLQ, effects of faults can be analyzed in QCA circuits and systems.
In this way the defect analysis and fault effects could be carried out for QCA basic
building blocks MV, inverter, binary wire, L-Shaped wire and fanout.
5. DEFECT ANALYSIS OF QCA COMBINATIONAL CIRCUITS
The given combinational circuit or its Boolean function must be synthesis into QCA
MV and inverter network. Synthesis tools reported in [21] are used to convert the
given Boolean function into QCA MV and inverter network.
In this paper 2X1 multiplexer, adder are implemented using HDLQ. Single
missing cell defect analysis and fault effects are carried out using HDLQ. This
analysis will further helpful for the development of testing methods for QCA circuits
and systems.
The single missing cell deposition defect analysis also possible using
QCADesigner [18] at the layout level. The single missing cell deposition defect
analysis are carried out in [16] using QCADesigner. Also in [22] the defect analysis
of adder is carried out layout level using QCADesigner and at logic level using
HDLQ. Both the results are compared and found equivalent.
The Fig.13. shows QCA 2x1 multiplexer using MVs and inverter. Here AND and
OR gates are implemented by keeping one of the inputs of MV at logic 0 and logic 1
respectively.
Figure 13 QCA 2X1 Multiplexer
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MV1out = I0S0
MV2out = I1S1
Where S1=S0’
MV3out = out = I0S0+ I1S1
The 2X1 multiplexer shown in Fig. 13. is implemented in HDLQ for the defect
and fault analysis. The instantiations of all HDLQ modules for MV and inverter are
taken. The testbench is also developed. Xillinx 13.1 ISE tool is used.
Here one by one fault is injected in the HDLQ to observe the response of the QCA
2X1 multiplexer.
For Example
Consider the Majority Voter 1 (MV1). As discuss in section IV, the S_a_B fault is
injected by setting the values of fault0 and fault 1 as logic 0 and logic 1 respectively.
The snap shot of HDLQ simulation of 2X1 multiplexer for MV1 at s_a_B is shown in
Fig. 14.
Figure 14 Simulation of 2X1 multiplexer for MV1 at s_a_B
For fault free condition, if I0=0 and I1=1 the output must be logic 0. In case of
presence of S_a_B fault, the out=1. This is because MV1 S_a_B means the output of
MV1 is S0 instead of I0S0.
MV1out = S0 (due to S_a_B)
MV2out = I1S1
Where S1=S0’
MV3out = out = S0+ I1S1
If I0=0 and I1=1 out will be logic 1 instead of 0.
The all possible defects and faults are analysed for QCA 2X1 multiplexer in all
basic devices like MV and inverter.
The fault caused by the defects and its effects on output is summarized in Table 5.
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Table 5 Analysis of defects and faults on 2X1 multiplexer
Input
Fault
Free
output
MV1 MV2 MV3
Inverte
r
I0 I1 S0 S1 out S_a_B F(A’BC’) S_a_B F(A’BC’) S_a_B F(A’BC’) S_a_A
out
0 0 0 1 0 0 0 1 1 0 0 0
0 0 1 0 0 1 1 0 0 0 0 0
0 1 0 1 0 1 1 1 1 1 0 0
0 1 1 0 1 1 1 0 1 0 0 1
1 0 0 1 1 1 1 1 1 0 0 0
1 0 1 0 0 1 1 1 1 0 0 1
1 1 0 1 1 1 1 1 1 1 0 0
1 1 1 0 1 1 1 1 1 0 0 1
6. CONCLUSION
The defects in the future nanotechnology is more likely to occur. The defect analysis
for deposition missing cell and additional cell in the QCA circuit can be done using
Hardware Description Language for QCA, HDLQ. In this paper the analysis of defect
and faults are done for 2X1 multiplexer using HDLQ. The fault free and faulty
outputs are observed which will be useful for the test generation and the testing.
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