The document presents a detailed overview of the 8085 microprocessor instruction set, covering various instruction types and their related opcodes, including data transfer, arithmetic, logical, stack, branch, I/O, and interrupt instructions. It explains the addressing modes, such as immediate, register, absolute, register indirect, and implied addressing, as well as providing examples and execution results for specific mnemonics like MVI, MOV, LDA, and STA. Additionally, it discusses how opcodes are constructed and emphasizes that although 256 distinct opcodes are theoretically possible, only 246 are implemented in the 8085 architecture.

1. Presented by:
Engr Zeeshan Ahmed Lodro
Lecturer-Department of Electronics Engineering Technology
BBS University of Technology and Skill Development Khairpur Mirs
1
Lecture-2

2. 2

3. ❑Classification of 8085 Instructions
❑Number of Instructions in 8085
 Instruction type MVI r,d8
 Instruction type MOV r1,r2
 Instruction type MOV r,M
 Instruction type M,r
 Instruction type LXI rp, d16
3

4.  Instruction type MVI M,d8
 Instruction type LDA a16
 Instruction type STA a16
 Instruction type XCHG
❑ Addressing Modes of 8085
❑ Register codes
4

5.  Immediate addressing mode
 Register addressing mode
 Absolute addressing mode
 Register indirect addressing mode
 Implied addressing mode
 InstructionType LDAX rp
 Instruction type STAX rp
 Instruction type LHLD a16
 Instruction type SHLD a16
5

6. Description No. of opcodes No. of instruction types
Data transfer instruction 83 13
Arithmetic instruction 62 14
Logical instruction 43 15
Stack instruction 15 9
Branch instruction 36 8
I/O instruction 2 2
Interrupt instruction 5 5
Total 246 66
6

7. ❑With 8 bits for the opcode, 2^8=256 distinct
opcodes are possible.
❑In hexadecimal, the opcodes can be from 00H
to FFH.
❑Each opcode corresponds to instruction thus
theoretically 256 instructions are possible in
the instruction set of 8085.
❑However only 246 opcodes are implemented
in 8085.
7

8.  Of the 246 opcodes we have:
 202 opcodes that are 1-byte long
 18 opcodes that are 2-byte long
 26 opcodes are 3 bytes long.
8

9.  MVI is a mnemonic, which stands for ‘MoVe
Immediate’.This is an instruction to load a
register with 8-bit value.This instruction uses
immediate addressing for specifying the data.
 In this instruction d8 stands for any 8-bit data
and r stands for any of the following registers.
 R=A,B,C,D,E,H or L
 As r can have any of seven values, there are
seven opcodes for this type of instruction. It
occupies 2 bytes in the memory.
9

10. ❑The result of execution is shown below.
Summary:
MVI r,d8( 2-byte; MVI E,8DH; 7 opcodes)
10
Register Before After
E 45 8D

11.  MOV is a mnemonic, which stands for ‘MOVe’.This is
an instruction to load a register r1 with 8-bit value
register r2. Notice that in 8085 instructions the first
operand specifies the destination and the second the
source.This instruction uses register addressing for
specifying the data.
 In this instruction r1 and r2 stands for any of the
following registers.
 R=A,B,C,D,E,H or L
 As r1 can have any of seven values and r2 can have
any of seven values there are 7x7=49 opcodes for this
type of instruction. It occupies 1 bytes in the memory.
11

12. ❑The result of execution is shown below.
Summary:
MOV r1,r2( 1-byte; MOV E,H; 49 opcodes)
12
Register Before After
E 45 8D
H 8D 8D

13.  Notice that H register content is not altered
at all.
 Another thing to note is that there are
instructions like MOV D,D.
 This instruction moves contents of D register
to D register itself.
 It is of no use anybody, such useless
instructions are provided in the instruction
set of 8085.
13

14.  MOV is a mnemonic, which stands for ‘MOVe’.
This is an instruction to load a register r with 8-
bit value in memory location. But from which
memory location?The address of memory
location is understood to be provided in HL
register pair.This instruction uses register
indirect addressing for specifying the data. As r
can have any seven values, there are seven
opcodes for this type of instruction. It occupies
only 1-byte in memory. MOV E,M is an example
of this instruction.
14

15. ❑The result of execution is shown below.
Summary:
MOV r,M( 1-byte; MOV E,M; 7 opcodes)
15
Register Before After
E 45 8D
HL F850 F850
F850 8D 8D

16.  Another thing to note is that there are
instructions like MOV H,M.
 This instruction moves contents of a memory
location pointed by HL register pair to H
register itself.
 It is of no use anybody, such useless
instructions are provided in the instruction
set of 8085.
16

17.  This is an instruction to load memory location
with 8-bit value in register r. But which
memory location?The address of memory
location is understood to be provided in HL
register pair.This instruction uses register
indirect addressing for specifying the data.As
r can have any seven values, there are seven
opcodes for this type of instruction. It
occupies only 1-byte in memory. MOV M,E is
an example of this instruction.
17

18. ❑The result of execution is shown below.
Summary:
MOV M,r( 1-byte; MOV M,E; 7 opcodes)
18
Register Before After
E 45
HL F850
F850 8D 45

19.  Another thing to note is that there are
instructions like MOV M,H.
 This instruction moves contents of H register
to memory location pointed by HL register
pair .
 It is of no use anybody, such useless
instructions are provided in the instruction
set of 8085.
19

20.  So far we have seen that whenever M is used in an
instruction mnemonic, we are referring to the
contents of memory location whose address is given
in HL register pair.Thus, if MOV E,M is executed,
register E receives contents of memory pointed by
HL.
 Suppose we want E to receive contents of memory
location FF00H.Then we have to make sure that HL
will have FF00H, before MOV E,M is executed.Thus
any instruction involving M like MOV E,M, should
generally be preceded by instructions to load H and L
registers with the desired memory address.
20

21.  How to ensure that HL register pair will have
the value of FF00H?
 One method is to use the following two
instructions: MVI H,FFH and MVI L,00H
 These two instructions occupy a total of 4
bytes in memory. A simpler alternative is to
use the 3 byte instruction ‘LXI H, FF00H’, of
the type LXI rp,d16.
21

22.  LXI is a mnemonic that stands for Load
eXtended register Immediate. Here, a
register pair is termed as extended register. It
is an instruction that loads register pair rp
with the 16 bit data denoted as d16. this
instruction uses immediate addressing for
specifying the data. In this type ,rp stands for
any of the following register pair.
 rp=BC, DE,HL
22

23.  As rp can have any of the three values, there
are three opcodes for this type of instruction.
It occupies 3 bytes in memory.
 First byte specify the opcode, next tow bytes
specify the 16 bit data.
 LXI H, F850H is an example of this type of
instruction. It is a 3-byte instruction.This
result of this instruction is shown next
23

24. ❑The result of execution is shown below.
Summary:
LXI rp,d16( 3-bytes; LXI H, F850H; 3 opcodes)
24
Register Before After
HL FABCH F850H

25.  Notice that when specifying the register pair,
we specify only the MS register in the
instruction mnemonic.The X in the
mnemonic indicates that it is a register pair,
and so if the MS register is specified the
register pair is identified.
 LXI H,F850H is stored in reverse order.
 Code for LXI H
 50
 F8
25

26.  This is an instruction to load a memory
location pointed by HL pair with 8-bit value.
This instruction uses immediate addressing
for specifying the data.
 It occupies two bytes in memory.
 MVI M, 8DH is an example instruction of this
type. It is a 2 bytes in a memory.
26

27. ❑The result of execution is shown below.
Summary:
MVI M,d8( 2-byte; MVI M,8DH; 1 opcode)
27
Register Before After
HL F845
F845 AC 8D

28.  LDA is mnemonic that stands for LoaD
Accumulator contents from memory.This is an
instruction to load accumulator with the
contents of memory location whose 16 bit
address is indicated in the instruction as 16.This
instruction uses absolute addressing for
specifying the data.
 It occupies 3 bytes in memory, first byte specifies
opcode, the successive 2 bytes provide the 16 bit
address.
 LDA F850H is an example instruction of this
type.
28

29. ❑The result of execution is shown below.
Summary:
LDA a16( 3-bytes; LDA F850H, 1 opcode)
29
Register Before After
F850 BCH
A 12H BCH

30.  LDA F850H is stored in memory with F850
stored in byte reversal as shown below.
 Code for LDA
50
F8
 There is no instruction like LDB a16,LDC a16
etc.
30

31.  STA is a mnemonic that stands for Store
Accumulator contents in memory.This is an
instruction to storeAccumulator contents in a
memory location whose 16 bit address is
indicated in the instruction as a16.This
instruction uses absolute addressing for
specifying the destination.
 It is 3 byte instruction. First byte specify the
opcode, successive 2 bytes provides the 16 bit
address.
 STA F850H is example of this type.
31

32. ❑The result of execution is shown below.
Summary:
STA a16( 3-bytes; STA F850H, 1 opcode)
32
Register Before After
A 12H
F850H BCH 12H

33.  There are no instructions in 8085 like STB
a16,STD a16 etc.
 STA F80H is stored in memory with F850
stored in byte reversal as shown below.
 Code for STA
 50
 F8
33

34.  XCHG is a mnemonic, which stands for
eXCHanGe.This is an instruction to exchange
contents of HL pair with DE pair.
 This instruction used implied addressing.
 It occupies only one byte in memory.
34

35. ❑The result of execution is shown below.
Summary:
XCHG( 1-byte; XCHG, 1 opcode)
35
Register Before After
HL 1234H 5678h
DE 5678 1234H

36.  Shown below are the sizes of few instruction
types.
 MOV r1,r2 1 byte
 MOV r,M 1 byte
 MOV r,d8 2 bytes
 Let us discuss reasons
36

37. 37
 The 8085 sends out 16-bit address to access one of
the 2^16=64K locations. But for convenience, we
indicate memory address using four hexadecimal
digits. Similarly, for convenience we indicate registers
as A,B,C etc. But the microprocessor must specify
these registers using 0s and 1s only.

38.  With only seven registers in 8085, 3 bits are
enough to specify a register.Three bit codes
are specified in table mentioned in previous
slide.
38

39.  Now let us see how intel has arrived at the opcode for MOV E,H.
Six bits are needed to specify the two registers E and H.
 Still two bits are needed to specify the two registers E and H. Still
two bits are left in a byte.Theses two bits are needed to indicate
the code for MOV.The template chose by Intel for instruction type
MOV r1,r2 is shown in the following. Intel chose 0 1 as the code for
MOV
 0 1 r1 code r2 code
 From the previous table the opcode for MOV E,H will be
 01 011 100=5CH
 This can be verified from the opcode chart given in the previous
lecture.
 Similarly the code for MOV A,B will be:
 01 111 000=78H
39

40.  Now let us see how intel has arrived at the opcode for
MOV E,M.
 How to specify M? Intel solved this problem by choosing
110, which was not used to specify any register as the code
for M.
 Thus although M stands for the contents of memory
location pointed by HL pair. It has 110 as the register code.
Six bits are needed to specify E and M.The remaining two
bits in the byte indicate the code for MOV.The opcode for
MOV E,M will be
 01 011 110=5EH
 This can be verified from opcode chart given in previous
slide. Similarly the code for MOV A,M will be : 01 111 110
with is 7EH.
40

41.  Now let us see how intel has arrived at the opcode for
MVI E,34H. It will be a 2-byte instruction with 34H as
the second byte. In the first byte,3 bits are needed to
specify the registers E, still 5 bits are left in the first
byte.These five bits indicate the code for MVI.The
template chosen by ‘intel for instruction type MVI r,d8
is shown below.
 00 r code 110
 From table:
 00 011 110=1EH
 This can be verified from opcode chart. Similarly the
code for MVI M will be:
 00 110 110 = 36H
41

42.  A user would like to have the ability to access data in
different ways for some reasons of convenience.
These different ways of accessing the data is called
the addressing modes. It is very similar the way
teacher in classro0m call his particular students in one
of the following ways.
 By mentioning the name of student.
 By indicating the position of his seat in the class.
 By indicating the features of student.
 Consider the execution of following four instructions.
In each of these instructions we move 25H to the
accumulator using different addressing modes.
42

43. 43

44.  In the previous examples, only MVI A,25H
clearly indicates that 25H has to be moved to
the A register.This instruction occupies two
bytes in memory as follows.
 Opcode for MVIA
 25H
 As the data moved is immediately after the
opcode in the instruction.This kind of
addressing is called immediate addressing
mode.
44

45.  In the previous examples, MOV A,B indicates
that contents of the B register have to be
moved to the A register. It does not directly
say that 25H has to be moved.
 The instruction only provides the address of
the data. In the case, the address is register B,
provided in the opcode using 3 bits.This kind
of addressing where the data is specified in a
register is called Register addressing mode.
45

46.  In the previous examples, LDA F850H indicates that
content of the memory location F850H have to be moved
to the A register. It does not directly say that 25H has to be
moved.This instruction only provides the address of the
data. In this case, the memory address is F850H, provided
in the instruction using 2 bytes.This kind of addressing
where the data is specified in a memory location is called
absolute addressing mode. It is called absolute addressing
because a full 16 bit memory address is given as part of
the instruction, in comparison with register addressing
where only a 3 bit register address is provided as part of
the instruction.
 This type of addressing is sometimes called direct
addressing.
46

47.  In the previous examples, MOV A, M indicates
that contents of the memory location pointed by
HL register pair has to be moved to A register. It
does not directly say that 25H has to be moved.
 If HL content is F850H, we are not moving F850H
to accumulator.
 We have to take F850H as the memory address
and so move contents of F850H.
 This is an indirect way of using register pair HL.
 Hence this instruction is said to use Register
indirect addressing.
47

48.  Consider the instruction XCHG. It exchanges the
contents of HL pair with DE pair. But the
instruction mnemonic does not explicitly specify
that HL and DE are to be exchanged. In other
words we do no write the instruction as XCHG
HL,DE. It is just implied that we have to
exchange HL and DE. So this type of addressing
is called implied addressing mode. It is also
called implicit addressing mode sometimes.
 These are the only addressing modes available
in 8085.
48

49.  LDAX is a mnemonic that stands for LoaD
Accumulator from memory pointed by
eXtended register denoted as rp.This
instruction uses register indirect addressing
for specifying the data. It occupied only 1
byte in memory.
 LDAX B is an example instruction of this type.
It is a 1-byte instruction.The result of the
execution is shown below.
49

50. ❑The result of execution is shown below.
Summary:
LDAX rp( 1-byte; LDAX B, 2 opcodes)
50
Register Before After
BC F2BCH
F2BCH DCH
A 12H DCH

51.  Only other instruction of this type is LDAX D.
Note that LDAX H is not provided in 8085.
This is because LDAX H is the same as MOV
A, M in its function.
 Also note that there are no instructions in
8085 like LDBX rp, LDCX rp etc.
51

52.  STAX is a mnemonic that stands for Store
Accumulator contents in memory pointed by
eXtended register denoted as ‘rp’.This
instruction uses register indirect addressing
for specifying the destination. It occupies 1
byte in memory.
 STAX B is an example instruction of this type.
It is a 1-byte instruction.The result of this
instruction is shown below with an example.
52

53. ❑The result of execution is shown below.
Summary:
STAX rp( 1-byte; STAX B, 2 opcodes)
53
Register Before After
BC F2BCH
A 12H
F2BCH DCH 12H

54.  Only other instruction of this type is STAX D.
Note that STAX H is not provided in 8085.
This is because, STAX H is the same as MOV
M,A in its function.
 Also note that there is no instruction like
STBX rp, STCX rp etc.
54

55.  LHLD is mnemonic that stands for load HL pair
using Direct addressing from memory location
whose 16 bit address is denoted as 16. As HL pair
has to be loaded, the data comes from two
consecutive locations starting at the address
a16.This instruction uses absolute addressing
for specifying the data. It occupies 3 bytes in
memory.
 LHLD F2BCH is an example of instruction. It is a
3-byte instruction.
55

56. ❑The result of execution is shown below.
Summary:
LHLD a16( 3-bytes; LHLD F2BCH, 1 opcode)
56
Register Before After
F2BC DCH
F2BD ABH
H 12H ABH
L 34H DCH

57.  SHLD is a mnemonic, which stands for Store
HL pair using Direct addressing in memory
location whose 16 bit address is denoted as
16. As HL pair has to be stored, it has to be
stored in two consecutive locations starting
at the address a16.This instruction uses
absolute addressing for specifying the
destination. It occupies 3 bytes in memory.
57

58. ❑The result of execution is shown below.
Summary:
SHLD a16( 3-bytes; SHLD F2BCH, 1 opcode)
58
Register Before After
H 12H
L 34H
F2BC DCH 34H
F2BD ABH 12H

59.  SHLD F2BCH is stored in memory with F2BC
stored in byte reversal form.
 Code for SHLD
▪ BC
▪ F2
 Note that there are no instructions like SBCD
a16 and SDED a16.
59

60. 60