SlideShare a Scribd company logo
UNIT – 2
(BY: SANDEEP GANGWAR SIR)
INSTRUCTION SET AND EXECUTION IN 8085
An instruction is a command to the microprocessor to perform a given task on a specified data. Each
instruction has two parts: one is task to be performed, called the operation code (opcode), and the
second is the data to be operated on, called the operand. The operand (or data) can be specified in
various ways. It may include 8-bit (or 16-bit) data, an internal register, a memory location, or 8-bit (or
16-bit) address. In some instructions, the operand is implicit.
Classification based on functionality:
I. Data transfer operations: This group of instructions copies data from source to destination.
The content of the source is not altered.
II. Arithmetic operations: Instructions of this group perform operations like addition,
subtraction, increment & decrement. One of the data used in arithmetic operation is stored
in accumulator and the result is also stored in accumulator.
III. Logical operations: Logical operations include AND, OR, EXOR, COMPARE, ROTATE. The
operations like AND, OR and EXOR uses two operands, one is stored in accumulator and
other can be any register or memory location. The result is stored in accumulator. NOT
operation requires single operand, which is stored in accumulator.
IV. IV. Branching operations: Instructions in this group (JUMP, CALL, RETURN) can be used to
transfer program sequence from one memory location to another either conditionally or
unconditionally.
1. Jump Instructions – The jump instruction transfers the program sequence to the memory
address given in the operand based on the specified flag. Jump instructions are 2 types:
Unconditional Jump Instructions and Conditional Jump Instructions.
(a) Unconditional Jump Instructions: Transfers the program sequence to the described
memory address.
JMP address Jumps to the address Ex- JMP 2050
(b) Conditional Jump Instructions: Transfers the programs sequence to the described
memory address only if the condition in satisfied.
2. Call Instructions – The call instruction transfers the program sequence to the memory
address given in the operand. Before transferring, the address of the next instruction after
CALL is pushed onto the stack. Call instructions are 2 types: Unconditional Call Instructions
and Conditional Call Instructions.
(a) Unconditional Call Instructions: It transfers the program sequence to the memory
address given in the operand.
CALL address Unconditionally calls Ex - CALL 2050
(b) Unconditional Call Instructions: It transfers the program sequence to the memory
address given in the operand.
3. Return Instructions – The return instruction transfers the program sequence from the
subroutine to the calling program. Return instructions are 2 types: Unconditional Jump
Instructions and Conditional Jump Instructions.
(a) Unconditional Return Instruction: The program sequence is transferred unconditionally
from the subroutine to the calling program.
RET Return from the subroutine unconditionally Ex – RET
(b) Conditional Return Instruction: The program sequence is transferred unconditionally
from the subroutine to the calling program only is the condition is satisfied.
V. Machine control operations: Instruction in this group (HLT, EI, DI) control execution of other
instructions and control operations like interrupt, halt etc.
Classification based on length:
I. One-byte instructions: Instruction having one byte in machine code. (MOV B,C)
II. I. Two-byte instructions: Instruction having two byte in machine code. (MVI B,23H)
III. II. Three-byte instructions: Instruction having three byte in machine code. (LDA 1234H)
Addressing Modes
The process of specifying the data to be operated on by the instruction is called addressing. The various
formats for specifying operands are called addressing modes. The 8085 has the following five types of
addressing:
1. Immediate addressing
2. Direct addressing
3. Register direct addressing
4. Indirect addressing
5. Implicit addressing
Immediate Addressing:
In this mode, the operand given in the instruction - a byte or word – transfers to the destination register
or memory location.
Ex: MVI A, 9AH
The operand is a part of the instruction.
The operand is stored in the register mentioned in the instruction.
Direct addressing:
Memory direct addressing moves a byte or word between a memory location and register. The memory
location address is given in the instruction.
Ex: LDA 850FH
This instruction is used to load the content of memory address 850FH in the accumulator.
Register Direct Addressing:
Register direct addressing transfer a copy of a byte or word from source register to destination register.
Ex: MOV B, C
It copies the content of register C to register B.
Indirect Addressing:
Indirect addressing transfers a byte or word between a register and a memory location.
Ex: MOV A, M
Here the data is in the memory location pointed to by the contents of HL pair. The data is moved to the
accumulator.
Implicit Addressing:
In this addressing mode the data itself specifies the data to be operated upon.
Ex: CMA
The instruction complements the content of the accumulator. No specific data or operand is mentioned
in the instruction.
NOTE: Some special instructions of 8085
PUSH - Push Two bytes of Data onto the Stack
POP - Pop Two Bytes of Data off the Stack
XTHL - Exchange Top of Stack with H & L
SPHL - Move content of H & L to Stack Pointer
IN - Initiate Input Operation
OUT - Initiate Output Operation
EI - Enable Interrupt System
DI - Disable Interrupt System
HLT – Halt
NOP - No Operation
INSTRUCTION EXECUTION:
Each instruction in 8085 microprocessor consists of two part- operation code (opcode) and operand. The
opcode is a command such as ADD and the operand is an object to be operated on, such as a byte or the
content of a register.
Instruction Cycle: The time taken by the processor to complete the execution of an instruction. An
instruction cycle consists of one to six machine cycles.
Machine Cycle: The time required to complete one operation; accessing either the memory or I/O
device. A machine cycle consists of three to six T-states.
T-State: Time corresponding to one clock period. It is the basic unit to calculate execution of instructions
or programs in a processor.
To execute a program, 8085 performs various operations as:
Opcode fetch
Operand fetch
Memory read/write
I/O read/write
External communication functions are:
Memory read/write
I/O read/write
Interrupt request acknowledge
NOTE:
The 8085 microprocessor has 5 (seven) basic machine cycles. They are
Opcode fetch cycle (4T)
Memory read cycle (3 T)
Memory write cycle (3 T)
I/O read cycle (3 T)
I/O write cycle (3 T)
Interrupts in 8085
Interrupts are the signals generated by the external devices to request the microprocessor to perform a
task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
Interrupt are classified into following groups based on their parameter –
• Vector interrupt − In this type of interrupt, the interrupt address is known to the processor. For
example: RST7.5, RST6.5, RST5.5, TRAP.
• Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to the processor
so, the interrupt address needs to be sent externally by the device to perform interrupts. For example:
INTR.
• Maskable interrupt − In this type of interrupt, we can disable the interrupt by writing some
instructions into the program. For example: RST7.5, RST6.5, RST 5.5
• Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt by writing some
instructions into the program. For example: TRAP.
• Software interrupt − In this type of interrupt, the programmer has to add the instructions into the
program to execute the interrupt. There are 8 software interrupts in 8085, i.e. RST0, RST1, RST2, RST3,
RST4, RST5, RST6, and RST7.
• Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware interrupts, i.e. TRAP, RST7.5,
RST6.5, RST5.5, INTA.
Note –
INTA is not an interrupt; it is used by the microprocessor for sending acknowledgement.
TRAP has the highest priority, then RST7.5 and so on.
Programs:
Problem – Write an assembly language program to add two 8 bit numbers stored at
address 2050 and address 2051 in 8085 microprocessor. The starting address of the
program is taken as 2000.
Ans.
Explanation –
1. LDA 2050 moves the contents of 2050 memory location to the accumulator.
2. MOV H, A copies contents of Accumulator to register H to A
3. LDA 2051 moves the contents of 2051 memory location to the accumulator.
4. ADD H adds contents of A (Accumulator) and H register (F9). The result is stored in A
itself. For all arithmetic instructions A is by default an operand and A stores the
result as well
5. MOV L, A copies contents of A (34) to L
6. MVI A 00 moves immediate data (i.e., 00) to A
7. ADC A adds contents of A(00), contents of register specified (i.e A) and carry (1). As
ADC is also an arithmetic operation, A is by default an operand and A stores the result
as well
8. MOV H, A copies contents of A (01) to H
9. SHLD 3050 moves the contents of L register (34) in 3050 memory location and
contents of H register (01) in 3051 memory location
10. HLT stops executing the program and halts any further execution
Problem – Multiply two 8 bit numbers stored at address 2050 and 2051. Result is stored
at address 3050 and 3051. Starting address of program is taken as 2000.
Ans.
Explanation – Registers used: A, H, L, C, D, E
1. LHLD 2050 loads content of 2051 in H and content of 2050 in L
2. XCHG exchanges contents of H with D and contents of L with E
3. MOV C, D copies content of D in C
4. MVI D 00 assigns 00 to D
5. LXI H 0000 assigns 00 to H and 00 to L
6. DAD D adds HL and DE and assigns the result to HL
7. DCR C decrements C by 1
8. JNZ 200A jumps program counter to 200A if zero flag = 0
9. SHLD stores value of H at memory location 3051 and L at 3050
10. HLT stops executing the program and halts any further execution
Problem - Write an assembly language program to add two 16 bit numbers by using 8 bit
operation.
Ans.
Explanation –
1. LDA 2050 stores the value at 2050 in A (accumulator)
2. MOV B, A stores the value of A into B register
3. LDA 2052 stores the value at 2052 in A
4. ADD B add the contents of B and A and store in A
5. STA 3050 stores the result in memory location 3050
6. LDA 2051 stores the value at 2051 in A
7. MOV B, A stores the value of A into B register
8. LDA 2053 stores the value at 2053 in A
9. ADC B add the contents of B, A and carry from the lower bit addition and store in A
10. STA 3051 stores the result in memory location 3051
11. HLT stops execution
Problem – Write an assembly language program in 8085 microprocessor to find sum of
digit of an 8 bit number.
Ans.
Explanation – Registers used A, B, C
1. LDA 2050 –loads the content of memory location 2050 in accumulator A
2. MOV B, A –moves the value of accumulator A in register B
3. ANI 0F –performs AND operation in value of accumulator A and 0F
4. MOV C, A –moves the value of accumulator A in register C
5. MOV A, B –moves the value of register B in accumulator A
6. RLC –instruction rotate the value of accumulator A, left by 1 bit. Since it is performed 4
times therefore this will reverse the number i.e swaps the lower order nibble with
higher order nibble
7. Repeat step 3
8. ADD C –add the content of register of C in accumulator A
9. STA 3050 –stores value of A in 3050
10. HLT –stops executing the program and halts any further execution

More Related Content

Similar to MPMC UNIT-2.pdf

Microprocessor and Microcontroller.pptx
Microprocessor and Microcontroller.pptxMicroprocessor and Microcontroller.pptx
Microprocessor and Microcontroller.pptx
pvg123456
 
Micro overview
Micro overviewMicro overview
Micro overview
lamamokalled
 
Important questions
Important questionsImportant questions
microprocessor
 microprocessor microprocessor
microprocessor
ATTO RATHORE
 
timing_diagram_of_8085.pptx
timing_diagram_of_8085.pptxtiming_diagram_of_8085.pptx
timing_diagram_of_8085.pptx
BhagyarajKosamia
 
Assembly language i
Assembly language iAssembly language i
Assembly language i
Vivek Kumar
 
Bca examination 2016 csa
Bca examination 2016 csaBca examination 2016 csa
Bca examination 2016 csa
Anjaan Gajendra
 
Ree602 microprocessor unit ii
Ree602  microprocessor unit iiRee602  microprocessor unit ii
Ree602 microprocessor unit ii
MAHMOOD ilahi
 
5th unit Microprocessor 8085
5th unit Microprocessor 80855th unit Microprocessor 8085
5th unit Microprocessor 8085
Mani Afranzio
 
c++
c++ c++
c++
Arun Nair
 
Lecture 10
Lecture 10Lecture 10
Lecture 10
talhashahid40
 
module-3.pptx
module-3.pptxmodule-3.pptx
module-3.pptx
Ambika Naik
 
the-cpu-design-central-processing-unit-design-1
the-cpu-design-central-processing-unit-design-1the-cpu-design-central-processing-unit-design-1
the-cpu-design-central-processing-unit-design-1
Basel Mansour
 
3-addressingmodes-181203034235.pptx
3-addressingmodes-181203034235.pptx3-addressingmodes-181203034235.pptx
3-addressingmodes-181203034235.pptx
MdAsaduzzaman257266
 
Addressing Modes
Addressing ModesAddressing Modes
Addressing Modes
Mayank Garg
 
Computer Organization : CPU, Memory and I/O organization
Computer Organization : CPU, Memory and I/O organizationComputer Organization : CPU, Memory and I/O organization
Computer Organization : CPU, Memory and I/O organization
AmrutaMehata
 
T-states in microprocessor 8085
T-states in microprocessor 8085T-states in microprocessor 8085
T-states in microprocessor 8085
yedles
 
Architecture of 8085
Architecture of 8085Architecture of 8085
Architecture of 8085
ShivamSood22
 
instruction
instruction instruction
instruction
Asif Iqbal
 
8085_Microprocessor(simar).ppt
8085_Microprocessor(simar).ppt8085_Microprocessor(simar).ppt
8085_Microprocessor(simar).ppt
KanikaJindal9
 

Similar to MPMC UNIT-2.pdf (20)

Microprocessor and Microcontroller.pptx
Microprocessor and Microcontroller.pptxMicroprocessor and Microcontroller.pptx
Microprocessor and Microcontroller.pptx
 
Micro overview
Micro overviewMicro overview
Micro overview
 
Important questions
Important questionsImportant questions
Important questions
 
microprocessor
 microprocessor microprocessor
microprocessor
 
timing_diagram_of_8085.pptx
timing_diagram_of_8085.pptxtiming_diagram_of_8085.pptx
timing_diagram_of_8085.pptx
 
Assembly language i
Assembly language iAssembly language i
Assembly language i
 
Bca examination 2016 csa
Bca examination 2016 csaBca examination 2016 csa
Bca examination 2016 csa
 
Ree602 microprocessor unit ii
Ree602  microprocessor unit iiRee602  microprocessor unit ii
Ree602 microprocessor unit ii
 
5th unit Microprocessor 8085
5th unit Microprocessor 80855th unit Microprocessor 8085
5th unit Microprocessor 8085
 
c++
c++ c++
c++
 
Lecture 10
Lecture 10Lecture 10
Lecture 10
 
module-3.pptx
module-3.pptxmodule-3.pptx
module-3.pptx
 
the-cpu-design-central-processing-unit-design-1
the-cpu-design-central-processing-unit-design-1the-cpu-design-central-processing-unit-design-1
the-cpu-design-central-processing-unit-design-1
 
3-addressingmodes-181203034235.pptx
3-addressingmodes-181203034235.pptx3-addressingmodes-181203034235.pptx
3-addressingmodes-181203034235.pptx
 
Addressing Modes
Addressing ModesAddressing Modes
Addressing Modes
 
Computer Organization : CPU, Memory and I/O organization
Computer Organization : CPU, Memory and I/O organizationComputer Organization : CPU, Memory and I/O organization
Computer Organization : CPU, Memory and I/O organization
 
T-states in microprocessor 8085
T-states in microprocessor 8085T-states in microprocessor 8085
T-states in microprocessor 8085
 
Architecture of 8085
Architecture of 8085Architecture of 8085
Architecture of 8085
 
instruction
instruction instruction
instruction
 
8085_Microprocessor(simar).ppt
8085_Microprocessor(simar).ppt8085_Microprocessor(simar).ppt
8085_Microprocessor(simar).ppt
 

Recently uploaded

Recycled Concrete Aggregate in Construction Part III
Recycled Concrete Aggregate in Construction Part IIIRecycled Concrete Aggregate in Construction Part III
Recycled Concrete Aggregate in Construction Part III
Aditya Rajan Patra
 
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsKuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
Victor Morales
 
Understanding Inductive Bias in Machine Learning
Understanding Inductive Bias in Machine LearningUnderstanding Inductive Bias in Machine Learning
Understanding Inductive Bias in Machine Learning
SUTEJAS
 
Engine Lubrication performance System.pdf
Engine Lubrication performance System.pdfEngine Lubrication performance System.pdf
Engine Lubrication performance System.pdf
mamamaam477
 
Iron and Steel Technology Roadmap - Towards more sustainable steelmaking.pdf
Iron and Steel Technology Roadmap - Towards more sustainable steelmaking.pdfIron and Steel Technology Roadmap - Towards more sustainable steelmaking.pdf
Iron and Steel Technology Roadmap - Towards more sustainable steelmaking.pdf
RadiNasr
 
Casting-Defect-inSlab continuous casting.pdf
Casting-Defect-inSlab continuous casting.pdfCasting-Defect-inSlab continuous casting.pdf
Casting-Defect-inSlab continuous casting.pdf
zubairahmad848137
 
Unit-III-ELECTROCHEMICAL STORAGE DEVICES.ppt
Unit-III-ELECTROCHEMICAL STORAGE DEVICES.pptUnit-III-ELECTROCHEMICAL STORAGE DEVICES.ppt
Unit-III-ELECTROCHEMICAL STORAGE DEVICES.ppt
KrishnaveniKrishnara1
 
Textile Chemical Processing and Dyeing.pdf
Textile Chemical Processing and Dyeing.pdfTextile Chemical Processing and Dyeing.pdf
Textile Chemical Processing and Dyeing.pdf
NazakatAliKhoso2
 
basic-wireline-operations-course-mahmoud-f-radwan.pdf
basic-wireline-operations-course-mahmoud-f-radwan.pdfbasic-wireline-operations-course-mahmoud-f-radwan.pdf
basic-wireline-operations-course-mahmoud-f-radwan.pdf
NidhalKahouli2
 
Question paper of renewable energy sources
Question paper of renewable energy sourcesQuestion paper of renewable energy sources
Question paper of renewable energy sources
mahammadsalmanmech
 
Generative AI leverages algorithms to create various forms of content
Generative AI leverages algorithms to create various forms of contentGenerative AI leverages algorithms to create various forms of content
Generative AI leverages algorithms to create various forms of content
Hitesh Mohapatra
 
TIME DIVISION MULTIPLEXING TECHNIQUE FOR COMMUNICATION SYSTEM
TIME DIVISION MULTIPLEXING TECHNIQUE FOR COMMUNICATION SYSTEMTIME DIVISION MULTIPLEXING TECHNIQUE FOR COMMUNICATION SYSTEM
TIME DIVISION MULTIPLEXING TECHNIQUE FOR COMMUNICATION SYSTEM
HODECEDSIET
 
Manufacturing Process of molasses based distillery ppt.pptx
Manufacturing Process of molasses based distillery ppt.pptxManufacturing Process of molasses based distillery ppt.pptx
Manufacturing Process of molasses based distillery ppt.pptx
Madan Karki
 
Embedded machine learning-based road conditions and driving behavior monitoring
Embedded machine learning-based road conditions and driving behavior monitoringEmbedded machine learning-based road conditions and driving behavior monitoring
Embedded machine learning-based road conditions and driving behavior monitoring
IJECEIAES
 
Properties Railway Sleepers and Test.pptx
Properties Railway Sleepers and Test.pptxProperties Railway Sleepers and Test.pptx
Properties Railway Sleepers and Test.pptx
MDSABBIROJJAMANPAYEL
 
哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样
哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样
哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样
insn4465
 
5214-1693458878915-Unit 6 2023 to 2024 academic year assignment (AutoRecovere...
5214-1693458878915-Unit 6 2023 to 2024 academic year assignment (AutoRecovere...5214-1693458878915-Unit 6 2023 to 2024 academic year assignment (AutoRecovere...
5214-1693458878915-Unit 6 2023 to 2024 academic year assignment (AutoRecovere...
ihlasbinance2003
 
ISPM 15 Heat Treated Wood Stamps and why your shipping must have one
ISPM 15 Heat Treated Wood Stamps and why your shipping must have oneISPM 15 Heat Treated Wood Stamps and why your shipping must have one
ISPM 15 Heat Treated Wood Stamps and why your shipping must have one
Las Vegas Warehouse
 
Eric Nizeyimana's document 2006 from gicumbi to ttc nyamata handball play
Eric Nizeyimana's document 2006 from gicumbi to ttc nyamata handball playEric Nizeyimana's document 2006 from gicumbi to ttc nyamata handball play
Eric Nizeyimana's document 2006 from gicumbi to ttc nyamata handball play
enizeyimana36
 
Recycled Concrete Aggregate in Construction Part II
Recycled Concrete Aggregate in Construction Part IIRecycled Concrete Aggregate in Construction Part II
Recycled Concrete Aggregate in Construction Part II
Aditya Rajan Patra
 

Recently uploaded (20)

Recycled Concrete Aggregate in Construction Part III
Recycled Concrete Aggregate in Construction Part IIIRecycled Concrete Aggregate in Construction Part III
Recycled Concrete Aggregate in Construction Part III
 
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsKuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
 
Understanding Inductive Bias in Machine Learning
Understanding Inductive Bias in Machine LearningUnderstanding Inductive Bias in Machine Learning
Understanding Inductive Bias in Machine Learning
 
Engine Lubrication performance System.pdf
Engine Lubrication performance System.pdfEngine Lubrication performance System.pdf
Engine Lubrication performance System.pdf
 
Iron and Steel Technology Roadmap - Towards more sustainable steelmaking.pdf
Iron and Steel Technology Roadmap - Towards more sustainable steelmaking.pdfIron and Steel Technology Roadmap - Towards more sustainable steelmaking.pdf
Iron and Steel Technology Roadmap - Towards more sustainable steelmaking.pdf
 
Casting-Defect-inSlab continuous casting.pdf
Casting-Defect-inSlab continuous casting.pdfCasting-Defect-inSlab continuous casting.pdf
Casting-Defect-inSlab continuous casting.pdf
 
Unit-III-ELECTROCHEMICAL STORAGE DEVICES.ppt
Unit-III-ELECTROCHEMICAL STORAGE DEVICES.pptUnit-III-ELECTROCHEMICAL STORAGE DEVICES.ppt
Unit-III-ELECTROCHEMICAL STORAGE DEVICES.ppt
 
Textile Chemical Processing and Dyeing.pdf
Textile Chemical Processing and Dyeing.pdfTextile Chemical Processing and Dyeing.pdf
Textile Chemical Processing and Dyeing.pdf
 
basic-wireline-operations-course-mahmoud-f-radwan.pdf
basic-wireline-operations-course-mahmoud-f-radwan.pdfbasic-wireline-operations-course-mahmoud-f-radwan.pdf
basic-wireline-operations-course-mahmoud-f-radwan.pdf
 
Question paper of renewable energy sources
Question paper of renewable energy sourcesQuestion paper of renewable energy sources
Question paper of renewable energy sources
 
Generative AI leverages algorithms to create various forms of content
Generative AI leverages algorithms to create various forms of contentGenerative AI leverages algorithms to create various forms of content
Generative AI leverages algorithms to create various forms of content
 
TIME DIVISION MULTIPLEXING TECHNIQUE FOR COMMUNICATION SYSTEM
TIME DIVISION MULTIPLEXING TECHNIQUE FOR COMMUNICATION SYSTEMTIME DIVISION MULTIPLEXING TECHNIQUE FOR COMMUNICATION SYSTEM
TIME DIVISION MULTIPLEXING TECHNIQUE FOR COMMUNICATION SYSTEM
 
Manufacturing Process of molasses based distillery ppt.pptx
Manufacturing Process of molasses based distillery ppt.pptxManufacturing Process of molasses based distillery ppt.pptx
Manufacturing Process of molasses based distillery ppt.pptx
 
Embedded machine learning-based road conditions and driving behavior monitoring
Embedded machine learning-based road conditions and driving behavior monitoringEmbedded machine learning-based road conditions and driving behavior monitoring
Embedded machine learning-based road conditions and driving behavior monitoring
 
Properties Railway Sleepers and Test.pptx
Properties Railway Sleepers and Test.pptxProperties Railway Sleepers and Test.pptx
Properties Railway Sleepers and Test.pptx
 
哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样
哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样
哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样
 
5214-1693458878915-Unit 6 2023 to 2024 academic year assignment (AutoRecovere...
5214-1693458878915-Unit 6 2023 to 2024 academic year assignment (AutoRecovere...5214-1693458878915-Unit 6 2023 to 2024 academic year assignment (AutoRecovere...
5214-1693458878915-Unit 6 2023 to 2024 academic year assignment (AutoRecovere...
 
ISPM 15 Heat Treated Wood Stamps and why your shipping must have one
ISPM 15 Heat Treated Wood Stamps and why your shipping must have oneISPM 15 Heat Treated Wood Stamps and why your shipping must have one
ISPM 15 Heat Treated Wood Stamps and why your shipping must have one
 
Eric Nizeyimana's document 2006 from gicumbi to ttc nyamata handball play
Eric Nizeyimana's document 2006 from gicumbi to ttc nyamata handball playEric Nizeyimana's document 2006 from gicumbi to ttc nyamata handball play
Eric Nizeyimana's document 2006 from gicumbi to ttc nyamata handball play
 
Recycled Concrete Aggregate in Construction Part II
Recycled Concrete Aggregate in Construction Part IIRecycled Concrete Aggregate in Construction Part II
Recycled Concrete Aggregate in Construction Part II
 

MPMC UNIT-2.pdf

  • 1. UNIT – 2 (BY: SANDEEP GANGWAR SIR) INSTRUCTION SET AND EXECUTION IN 8085 An instruction is a command to the microprocessor to perform a given task on a specified data. Each instruction has two parts: one is task to be performed, called the operation code (opcode), and the second is the data to be operated on, called the operand. The operand (or data) can be specified in various ways. It may include 8-bit (or 16-bit) data, an internal register, a memory location, or 8-bit (or 16-bit) address. In some instructions, the operand is implicit. Classification based on functionality: I. Data transfer operations: This group of instructions copies data from source to destination. The content of the source is not altered. II. Arithmetic operations: Instructions of this group perform operations like addition, subtraction, increment & decrement. One of the data used in arithmetic operation is stored in accumulator and the result is also stored in accumulator. III. Logical operations: Logical operations include AND, OR, EXOR, COMPARE, ROTATE. The operations like AND, OR and EXOR uses two operands, one is stored in accumulator and other can be any register or memory location. The result is stored in accumulator. NOT operation requires single operand, which is stored in accumulator.
  • 2. IV. IV. Branching operations: Instructions in this group (JUMP, CALL, RETURN) can be used to transfer program sequence from one memory location to another either conditionally or unconditionally. 1. Jump Instructions – The jump instruction transfers the program sequence to the memory address given in the operand based on the specified flag. Jump instructions are 2 types: Unconditional Jump Instructions and Conditional Jump Instructions. (a) Unconditional Jump Instructions: Transfers the program sequence to the described memory address. JMP address Jumps to the address Ex- JMP 2050 (b) Conditional Jump Instructions: Transfers the programs sequence to the described memory address only if the condition in satisfied. 2. Call Instructions – The call instruction transfers the program sequence to the memory address given in the operand. Before transferring, the address of the next instruction after CALL is pushed onto the stack. Call instructions are 2 types: Unconditional Call Instructions and Conditional Call Instructions. (a) Unconditional Call Instructions: It transfers the program sequence to the memory address given in the operand. CALL address Unconditionally calls Ex - CALL 2050 (b) Unconditional Call Instructions: It transfers the program sequence to the memory address given in the operand. 3. Return Instructions – The return instruction transfers the program sequence from the subroutine to the calling program. Return instructions are 2 types: Unconditional Jump Instructions and Conditional Jump Instructions.
  • 3. (a) Unconditional Return Instruction: The program sequence is transferred unconditionally from the subroutine to the calling program. RET Return from the subroutine unconditionally Ex – RET (b) Conditional Return Instruction: The program sequence is transferred unconditionally from the subroutine to the calling program only is the condition is satisfied. V. Machine control operations: Instruction in this group (HLT, EI, DI) control execution of other instructions and control operations like interrupt, halt etc. Classification based on length: I. One-byte instructions: Instruction having one byte in machine code. (MOV B,C) II. I. Two-byte instructions: Instruction having two byte in machine code. (MVI B,23H) III. II. Three-byte instructions: Instruction having three byte in machine code. (LDA 1234H)
  • 4. Addressing Modes The process of specifying the data to be operated on by the instruction is called addressing. The various formats for specifying operands are called addressing modes. The 8085 has the following five types of addressing: 1. Immediate addressing 2. Direct addressing 3. Register direct addressing 4. Indirect addressing 5. Implicit addressing Immediate Addressing:
  • 5. In this mode, the operand given in the instruction - a byte or word – transfers to the destination register or memory location. Ex: MVI A, 9AH The operand is a part of the instruction. The operand is stored in the register mentioned in the instruction. Direct addressing: Memory direct addressing moves a byte or word between a memory location and register. The memory location address is given in the instruction. Ex: LDA 850FH This instruction is used to load the content of memory address 850FH in the accumulator. Register Direct Addressing: Register direct addressing transfer a copy of a byte or word from source register to destination register. Ex: MOV B, C It copies the content of register C to register B. Indirect Addressing: Indirect addressing transfers a byte or word between a register and a memory location. Ex: MOV A, M Here the data is in the memory location pointed to by the contents of HL pair. The data is moved to the accumulator. Implicit Addressing: In this addressing mode the data itself specifies the data to be operated upon. Ex: CMA The instruction complements the content of the accumulator. No specific data or operand is mentioned in the instruction.
  • 6. NOTE: Some special instructions of 8085 PUSH - Push Two bytes of Data onto the Stack POP - Pop Two Bytes of Data off the Stack XTHL - Exchange Top of Stack with H & L SPHL - Move content of H & L to Stack Pointer IN - Initiate Input Operation OUT - Initiate Output Operation EI - Enable Interrupt System DI - Disable Interrupt System HLT – Halt NOP - No Operation INSTRUCTION EXECUTION: Each instruction in 8085 microprocessor consists of two part- operation code (opcode) and operand. The opcode is a command such as ADD and the operand is an object to be operated on, such as a byte or the content of a register. Instruction Cycle: The time taken by the processor to complete the execution of an instruction. An instruction cycle consists of one to six machine cycles. Machine Cycle: The time required to complete one operation; accessing either the memory or I/O device. A machine cycle consists of three to six T-states. T-State: Time corresponding to one clock period. It is the basic unit to calculate execution of instructions or programs in a processor. To execute a program, 8085 performs various operations as: Opcode fetch Operand fetch Memory read/write I/O read/write External communication functions are:
  • 7. Memory read/write I/O read/write Interrupt request acknowledge NOTE: The 8085 microprocessor has 5 (seven) basic machine cycles. They are Opcode fetch cycle (4T) Memory read cycle (3 T) Memory write cycle (3 T) I/O read cycle (3 T) I/O write cycle (3 T) Interrupts in 8085 Interrupts are the signals generated by the external devices to request the microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. Interrupt are classified into following groups based on their parameter – • Vector interrupt − In this type of interrupt, the interrupt address is known to the processor. For example: RST7.5, RST6.5, RST5.5, TRAP. • Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to the processor so, the interrupt address needs to be sent externally by the device to perform interrupts. For example: INTR. • Maskable interrupt − In this type of interrupt, we can disable the interrupt by writing some instructions into the program. For example: RST7.5, RST6.5, RST 5.5 • Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt by writing some instructions into the program. For example: TRAP. • Software interrupt − In this type of interrupt, the programmer has to add the instructions into the program to execute the interrupt. There are 8 software interrupts in 8085, i.e. RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7. • Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware interrupts, i.e. TRAP, RST7.5, RST6.5, RST5.5, INTA.
  • 8. Note – INTA is not an interrupt; it is used by the microprocessor for sending acknowledgement. TRAP has the highest priority, then RST7.5 and so on.
  • 9. Programs: Problem – Write an assembly language program to add two 8 bit numbers stored at address 2050 and address 2051 in 8085 microprocessor. The starting address of the program is taken as 2000. Ans. Explanation – 1. LDA 2050 moves the contents of 2050 memory location to the accumulator. 2. MOV H, A copies contents of Accumulator to register H to A 3. LDA 2051 moves the contents of 2051 memory location to the accumulator. 4. ADD H adds contents of A (Accumulator) and H register (F9). The result is stored in A itself. For all arithmetic instructions A is by default an operand and A stores the result as well 5. MOV L, A copies contents of A (34) to L 6. MVI A 00 moves immediate data (i.e., 00) to A
  • 10. 7. ADC A adds contents of A(00), contents of register specified (i.e A) and carry (1). As ADC is also an arithmetic operation, A is by default an operand and A stores the result as well 8. MOV H, A copies contents of A (01) to H 9. SHLD 3050 moves the contents of L register (34) in 3050 memory location and contents of H register (01) in 3051 memory location 10. HLT stops executing the program and halts any further execution Problem – Multiply two 8 bit numbers stored at address 2050 and 2051. Result is stored at address 3050 and 3051. Starting address of program is taken as 2000. Ans. Explanation – Registers used: A, H, L, C, D, E 1. LHLD 2050 loads content of 2051 in H and content of 2050 in L 2. XCHG exchanges contents of H with D and contents of L with E 3. MOV C, D copies content of D in C 4. MVI D 00 assigns 00 to D 5. LXI H 0000 assigns 00 to H and 00 to L
  • 11. 6. DAD D adds HL and DE and assigns the result to HL 7. DCR C decrements C by 1 8. JNZ 200A jumps program counter to 200A if zero flag = 0 9. SHLD stores value of H at memory location 3051 and L at 3050 10. HLT stops executing the program and halts any further execution Problem - Write an assembly language program to add two 16 bit numbers by using 8 bit operation. Ans. Explanation – 1. LDA 2050 stores the value at 2050 in A (accumulator) 2. MOV B, A stores the value of A into B register 3. LDA 2052 stores the value at 2052 in A 4. ADD B add the contents of B and A and store in A 5. STA 3050 stores the result in memory location 3050 6. LDA 2051 stores the value at 2051 in A 7. MOV B, A stores the value of A into B register
  • 12. 8. LDA 2053 stores the value at 2053 in A 9. ADC B add the contents of B, A and carry from the lower bit addition and store in A 10. STA 3051 stores the result in memory location 3051 11. HLT stops execution Problem – Write an assembly language program in 8085 microprocessor to find sum of digit of an 8 bit number. Ans. Explanation – Registers used A, B, C 1. LDA 2050 –loads the content of memory location 2050 in accumulator A 2. MOV B, A –moves the value of accumulator A in register B 3. ANI 0F –performs AND operation in value of accumulator A and 0F 4. MOV C, A –moves the value of accumulator A in register C 5. MOV A, B –moves the value of register B in accumulator A
  • 13. 6. RLC –instruction rotate the value of accumulator A, left by 1 bit. Since it is performed 4 times therefore this will reverse the number i.e swaps the lower order nibble with higher order nibble 7. Repeat step 3 8. ADD C –add the content of register of C in accumulator A 9. STA 3050 –stores value of A in 3050 10. HLT –stops executing the program and halts any further execution