This lecture describes the Princeton and Harvard architectures, steps in instruction execution and differences between CISC and RISC computers.

1. General Aspects of Computer Organization
(Lecture-3)
R S Ananda Murthy
Associate Professor
Department of Electrical & Electronics Engineering,
Sri Jayachamarajendra College of Engineering,
Mysore 570 006
R S Ananda Murthy General Aspects of Computer Organization

2. Specific Learning Outcomes
After completing this lecture the student should be able to –
Describe Von Neumann (Princeton) architecture.
Describe Harvard architecture.
Describe the function of MAR and MDR in the CPU.
Explain steps involved in executing an instruction.
Describe features of CISC and RISC computers.
R S Ananda Murthy General Aspects of Computer Organization

3. Von Neumann (Princeton) Architecture
CPU
Program
Memory
Data
Memory
Address Bus
Control Bus
Data Bus
Program and data memory share the same address space,
address and data buses.
Speed is limited because simultaneous access of program
and data memory by CPU is impossible.
Preferred in general purpose microprocessors where CPU
and memory are separate chips.
R S Ananda Murthy General Aspects of Computer Organization

4. Harvard Architecture
CPU
Data
Memory
Address Bus
Control Bus
Data Bus
Program
Memory
Address Bus
Data Bus
Control Bus
Program and data memory have different address space,
address and data buses.
Execution speed is increased because simultaneous
access of program and data memory by CPU is possible.
Preferred in microcontrollers where program memory, data
memory and CPU are in a single chip.
R S Ananda Murthy General Aspects of Computer Organization

5. MAR and MDR in CPU
MAR
PC
MDR
R0
R1
R2
:
Rn
IR
CU
ALU
Program
Memory
Data
Memory
Address Bus
Control Bus
Data Bus
Memory Address Register (MAR) stores the address of the
operand to be fetched from memory to execute the
instruction.
Memory Data Register (MDR) stores the operand (data)
after it is fetched from memory.
R S Ananda Murthy General Aspects of Computer Organization

6. Steps Followed by CPU in Instruction Execution
1 Fetch the instruction from the program memory location
pointed by PC into IR.
2 Determine the type of instruction present in the IR. This is
done by CU.
3 If the instruction uses an operand in memory, determine its
address and place it in MAR.
4 Fetch the operand and put it in MDR, and if needed, copy it
into a CPU register.
5 Execute the instruction. This is done by the CU.
6 Change the PC to point to the next instruction.
7 Go to Step 1 to begin executing the next instruction.
R S Ananda Murthy General Aspects of Computer Organization

7. An Imaginary Computer
MAR
PC
MDR
R0
R1
R2
:
R7
IR
CU
ALU
Address Bus
Control Bus
Data Bus
CPU
0x0000
0x0001
0x0002
0xFFFF
MEMORY Address in Hex
16 bits
16 bits
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
16 bits
8 bits
:
Blocks in side CPU are interconnected by internal address,
data, and control buses.
There are eight internal registers R0 to R7, each of 8 bits
width.
When we want to add two numbers, one number must be
present in R0 and the other one should be present in any
other register. The sum is placed in R0.
Instructions can be 1-byte, 2-bytes, or 3-bytes long.
R S Ananda Murthy General Aspects of Computer Organization

8. Instructions Recognized by Imaginary Computer
LDR Rn, MemAdr -- A three-byte instruction
1010 0 NNN
MemAdr Low Byte
MemAdr High Byte
n NNN
0 000
1 001
2 010
3-bit Code for
Registers
3 011
4 100
5 101
6 110
7 111
Opcode
Copies the data present at MemAdr
to the register Rn
ADD R0,Rn -- A one-byte instruction
11000 NNN
Adds contents of R0 and Rn and places
the sum in the register R0
Opcode
Operands
R S Ananda Murthy General Aspects of Computer Organization

9. Instructions Recognized by Imaginary Computer
MVI Rn, NextByte -- A two-byte instruction
1010 1 NNN
Data Byte
n NNN
0 000
1 001
2 010
3-bit Code for
Registers
3 011
4 100
5 101
6 110
7 111
Opcode
Copies the next data byte to the register Rn.
HALT -- A one-byte instruction
00000000
Stops incrementing of program counter.
Opcode
Operand
R S Ananda Murthy General Aspects of Computer Organization

10. Adding Two Numbers using Imaginary Computer
Memory
C1
00
:
A0
30
10
A1
31
10
LDR R0,0x1030
LDR R1,0x1031
ADD R0,R1
HALT
Hex Address
CD
EF
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x1030
:
0x1031
Augend
Addend
Data
How is opcode A0 obtained?
How is opcode A1 obtained?
How is opcode C1 obtained?
How many bytes in program?
Trace through the program
using steps given earlier.
After storing the program and data in the memory as
shown above we have to initialize PC with the starting
address 0x0000 and then give a command to the computer
to start execution of the program.
R S Ananda Murthy General Aspects of Computer Organization

11. Adding Two Numbers Another Way
Memory
A8
CD
A9
EF
C1
00
MVI R0,0xCD
ADD R0,R1
HALT
Hex Address
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
How is opcode A8 obtained?
How is opcode C1 obtained?
How many bytes in program?
MVI R1,0xEF How is opcode A9 obtained?
After storing the program and data in the memory as
shown above we have to initialize PC with the starting
address 0x0000 and then give a command to the computer
to start execution of the program.
Trace through the program using the steps given earlier.
R S Ananda Murthy General Aspects of Computer Organization

12. CISC and RISC
On the basis of type of instructions and how they are
executed, computers are roughly classified into two types –
Complex Instruction Set Computers (CISC) and Reduced
Instruction Set Computers (RISC).
CISC and RISC both have their merits and demerits.
Present trend is to incorporate the best features of both
CISC and RISC in processor design to get optimum
performance at optimum cost.
R S Ananda Murthy General Aspects of Computer Organization

13. Features of CISC
Traditionally most of the processors made in 1970s and
1980s were CISC adopting Princeton architecture.
Variable instruction length. For eg., there may be 1-byte,
2-byte, or 3-byte instructions as in case of Intel 8051 MCU.
As compared to RISC, CISC processors generally have
lesser number of internal registers in the CPU.
Variable instruction cycle time. Instruction cycle is the time
taken to execute an instruction. More complex instructions
take longer time to execute.
Large number of instructions in the instruction set.
Typically there can be more than 200 instructions in the
instruction set.
R S Ananda Murthy General Aspects of Computer Organization

14. Features of CISC
Generally, in CISC a portion of R/WM is used as stack to
store data while branching to subroutines.
Generally, in CISC instructions are available to operate on
data present in the memory directly without bringing it into
a register in side the CPU.
For a given task, a program in CISC results in smaller code
size.
Typically in CISC instructions are decoded by a
microprogram which is stored in CU. Microprogram
implementation requires more number of transistors to be
integrated on the chip.
Decoding of instructions using microprogram in CISC
slows down execution.
R S Ananda Murthy General Aspects of Computer Organization

15. Features of RISC
Traditionally RISC implementation is becoming popular
since 1990s.
Fixed instruction size. For eg. in AVR MCU which is a
RISC processor, almost all instructions are 2-bytes in
length with only a few 4-byte instructions.
Large number of internal registers in the CPU. For eg. AVR
MCU has 32 internal registers.
Because of large number of internal registers, usage of
stack to store data may not be essential as in CISC.
Smaller and simpler instruction set. Typically instruction
set may have less than 200 instructions.
For a given task, assembly language programming of RISC
machines generally requires more effort as compared to
CISC processors.
R S Ananda Murthy General Aspects of Computer Organization

16. Features of RISC
Due to the reason mentioned above, it is more convenient
to program RISC processors using higher level languages
like C or C++.
Fixed instruction cycle time for most of the instructions.
Many modern RISC processors adopt Harvard architecture
to speed up program execution.
Generally, in RISC it is not possible to perform arithmetic
and logical operations on data present in the memory
directly without bringing it into a register in side the CPU.
In RISC, instruction decoding in CU is done using
hardware and not by using a microprogram to speed up
instruction execution.
R S Ananda Murthy General Aspects of Computer Organization

17. License
This work is licensed under a
Creative Commons Attribution 4.0 International License.
R S Ananda Murthy General Aspects of Computer Organization