L16 usart-atmega328 p

Serial Communication in Atmega328P
(Lecture-16)
R S Ananda Murthy
Associate Professor
Department of Electrical & Electronics Engineering,
Sri Jayachamarajendra College of Engineering,
Mysore 570 006
R S Ananda Murthy Serial Communication in Atmega328P

Serial and Parallel Communication
Sender Receiver
Sender Receiver
D0
D7
:
:
:
:
:
D0D1..D7
Serial Communication
Parallel Communication

Serial versus Parallel Communication
Serial Communication
Bit-by-bit transmission.
Requires parallel-to-serial conversion at the sending end
and serial-to-parallel conversion at the receiving end.
Requires lesser number of wires as compared to parallel
communication.
Serial high-speed communication is becoming possible
now-a-days with improved hardware.
RS232, RS485, SPI, USB, I2C and CAN – all these
methods of communication employ serial communication.
Parallel Communication
Byte-by-byte transmission on eight data lines.
Was popular in 1990s because of its then higher speed as
compared serial communication.
Not suitable for long distance communication as number of
wires required is more.

Types of Serial Communication
Synchronous
Sender and receiver are driven by the same clock signal.
SPI and I2C communication protocols are very common
examples of synchronous serial communication.
Transfers a block of data (several characters) in one
operation.
Asynchronous
Sender and receiver are not driven by the same clock
signal.
Sender and receiver have to agree to operate at the same
baud rate.
Synchronization of sender and receiver is achieved by
inserting START and STOP bits along with the data bits to
form a data frame.
Typically used to transmit a single character at a time.

Technical Terms Related to Serial Communication
Baud Rate Bits per second.
Simplex One-way communication. For example, Device-1
can send data to Device-2 and not vice versa.
Full-duplex Two-way communication. Device-1 and 2 can both
send and receive data simultaneously.
Half-duplex Two-way communication, but not simultaneously.
USART Universal Synchronous Asynchronous Receiver
Transmitter. In most of the modern MCUs like
Atmega328P this block is integrated on the chip.
Data Frame Data bits along with START bit, STOP bit, and
optional parity bit is called a data frame.
Modem A device which converts 1s and 0s to audio tones
used for serial communication on telephone lines.

Data Frame
0 1 0 0 0 0 0Stop Start1
D0D1D2D3D4D5D6D7
Mark
Direction of transmission
Framing of ASCII Charater `A' (0x41) for serial communication
When there is no data transfer, the status of signal is 1
(high) which is also referred to as Mark.
Transmission begins with a Start bit which is 0 (low), also
called as Space.
After this the data bits are transmitted in the order LSB to
MSB and a STOP bit which is high (1).
In some systems, a parity bit for even or odd parity is
included in the data frame for data integrity.

RS232C Standard for Serial Communication
Proposed by Electronics Industries Association in 1960s.
Widely used for short distance serial communication even
today.
As per this standard, a voltage in the range −3 V to −25 V
represents a logical high (1) and a voltage level in the
range +3 V to +25 V represents a logical low (0).
Since the voltage levels of this standard are not compatible
with TTL levels used by MCUs such as Atmega328P, we
need to use a voltage converter chip such as MAX232 or
MAX233.

MAX232 Converter Chip

PC Serial Port Communication with MAX232

Block Diagram of USART0 in Atmega328P

USART0 Pins of Atmega328P
TxD On this pin serial data is transmitted by the
USART0
RxD On this pin serial data is received by the USART0
XCK This pin is used for clock signal only during
synchronous serial communication.

Serial Peripheral Interface (SPI)
SPI
Master
SPI
Slave
SDO
MOSI
SDI
SDI SDO
SCLK SCLK
SCK
CE CE
SS
MISO
MOSI – Master Out Slave In; MISO – Master In Slave Out;
SCK – Serial Clock; SS – Slave Select
SPI interface is typically used for short distance
communication between two devices.

Serial Peripheral Interface (SPI)
SPI, originally proposed by Motorola (now Freescale), uses
four wires – SDI (also called MOSI), SDO (also called
MISO), SCLK (also called SCK) , and CE (also called SS).
In SPI, one device will be master and the other device/s
will be slave/s.
Master always starts the communication by activating SS
and SCK.
SPI Communication is full-duplex.
In some systems SPI uses a common wire for both
MOSI/MISO, thus reducing the number of wires to three.
But such systems follow a different protocol for data
transmission as compared to 4-wire SPI systems.

SPI Architecture
When master wants to send a byte it places it in its shift
register and issues 8 clock pulses.
Then, the contents of the shift registers in the master and
slave are interchanged.
Clock input to the shift registers can be falling- or
rising-edge triggered.

SPI Modes of Operation
Write Operation (indicated by D7 = 1 of the ﬁrst byte)
Single-byte – write a byte to the slave.
Multi-byte – write multiple bytes to the slave.
Read Operation (indicated by D7 = 0 of the ﬁrst byte)
Single-byte – read a byte from the slave.
Multi-byte – read multiple bytes from the slave
Multi-byte operations are also known as burst mode operations.

Single-byte SPI Write Operation
1 Master places the bit pattern 1A6A5A4A3A2A1A0 in its shift
register, makes SS = 0 to select the slave, and then issues
8 pulses of SCK to transfer it to the slave on the MOSI line.
2 Master issues 8 more pulses of SCK to shift a byte of data
to the slave on the MOSI line and then makes SS = 1 to
deselect the slave.

Single-byte SPI Read Operation
1 Master places the bit pattern 0A6A5A4A3A2A1A0 in its shift
register, makes SS = 0 to select the slave, and then issues
8 pulses of SCK to transfer it to the slave on the MOSI line.
2 Master issues 8 more pulses of SCK to shift a byte of data
from the slave on the MISO line and then makes SS = 1 to
deselect the slave.

SPI Burst Mode Operations
SPI Burst Mode Write Operation
SPI Burst Mode Read Operation.
In this mode, the address is automatically updated in the slave
and the byte count is maintained in the master.

License
This work is licensed under a
Creative Commons Attribution 4.0 International License.

L16 usart-atmega328 p

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