International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Hands On Data Communications, Networking and TCP/IP TroubleshootingLiving Online
More and more people who work in plants need to understand how data from the field is transmitted to the control room and even to Manufacturing Execution Systems located in head offices situated considerable distances from the plant. It is a technological marvel and this manual helps you to understand the flow of information and the various techniques involved in it.
MORE INFORMATION: http://www.idc-online.com/content/hands-data-communications-networking-and-tcpip-troubleshooting-30?id=37
Practical Data Communications & Networking for Engineers & Technicians Living Online
Practical data communications and networking for engineers and technicians is a comprehensive workshop. It covers RS-232, RS-422, RS-485, industrial protocols, industrial networks and the communications requirements for 'smart' instrumentation. It will equip you with the tools to analyse, specify and debug data communications and networking systems in the instrumentation and control environment.
This workshop is designed to benefit people who are involved in specifying, commissioning and debugging data communications and networking systems for instrumentation and control, but who have little previous experience in this area. It has been structured to cover the main concepts of data communications, to clarify their meaning and to describe their applications in modern process control and automation systems.
The 7" TFT LCD 1024x600 Touch TFT Display Supports raspberry pi lcd display. Use GUI design software, and custom instruction set as communication protocol.
High speed customized serial protocol for IP integration on FPGA based SOC ap...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
Serial Communication Interface with Error Detectioniosrjce
UART is used for serial data communication. UART is a piece of computer hardware that translates
between parallel bits of data and serial bits. UART is usually an integrated circuit used for serial
communications over a computer or peripheral device serial port. Bits have to be moved from one place to
another using wires or some other medium. Over many miles, the expense of the wires becomes large. To reduce
the expense of long communication links carrying several bits in parallel, data bits are sent sequentially. Errors
may occur either internally or externally while we transmit information from source to destination. The errors
generated during the transmission would affect the performance of the overall system. In order to reduce the
errors we should incorporate any error detecting schemes like hamming decoder, check parity systems etc.
Different serial communication devices are available.
Design and Implementation of Low Power High Speed Symmetric Decoder Structure...Dr. Amarjeet Singh
The key objective of this project is to design a
decoder which can be used for hardware purposes.
Hardware, here accompanies with software which is more
we can discuss as a Software Defined Radio application. The
decoder implemented here offers to new radio equipment
(SDR), the flexibility of a programmable system. Nowadays,
the behavior of a communication system can be modified by
simply changing its software. Large tree decoder is made by
reusing smaller similar sub-modules. Thus the structure is
symmetric. The symmetric and regular structure of tree
decoder makes the system a less complexity one. The
structure obeys regularity and modularity concepts of VLSI
circuit, thus is easy to fabricate using cell library elements.
Design a Tree Decoder proposed architecture for SDR
application on FPGA. The Structures made here are
hardware synthesizable on FPGA board and are done in a
respective manner. The design to be implementing by using
Verilog-HDL language. The Simulation and Synthesis by
using Xilinx Vivado design suite.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Hands On Data Communications, Networking and TCP/IP TroubleshootingLiving Online
More and more people who work in plants need to understand how data from the field is transmitted to the control room and even to Manufacturing Execution Systems located in head offices situated considerable distances from the plant. It is a technological marvel and this manual helps you to understand the flow of information and the various techniques involved in it.
MORE INFORMATION: http://www.idc-online.com/content/hands-data-communications-networking-and-tcpip-troubleshooting-30?id=37
Practical Data Communications & Networking for Engineers & Technicians Living Online
Practical data communications and networking for engineers and technicians is a comprehensive workshop. It covers RS-232, RS-422, RS-485, industrial protocols, industrial networks and the communications requirements for 'smart' instrumentation. It will equip you with the tools to analyse, specify and debug data communications and networking systems in the instrumentation and control environment.
This workshop is designed to benefit people who are involved in specifying, commissioning and debugging data communications and networking systems for instrumentation and control, but who have little previous experience in this area. It has been structured to cover the main concepts of data communications, to clarify their meaning and to describe their applications in modern process control and automation systems.
The 7" TFT LCD 1024x600 Touch TFT Display Supports raspberry pi lcd display. Use GUI design software, and custom instruction set as communication protocol.
High speed customized serial protocol for IP integration on FPGA based SOC ap...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
Serial Communication Interface with Error Detectioniosrjce
UART is used for serial data communication. UART is a piece of computer hardware that translates
between parallel bits of data and serial bits. UART is usually an integrated circuit used for serial
communications over a computer or peripheral device serial port. Bits have to be moved from one place to
another using wires or some other medium. Over many miles, the expense of the wires becomes large. To reduce
the expense of long communication links carrying several bits in parallel, data bits are sent sequentially. Errors
may occur either internally or externally while we transmit information from source to destination. The errors
generated during the transmission would affect the performance of the overall system. In order to reduce the
errors we should incorporate any error detecting schemes like hamming decoder, check parity systems etc.
Different serial communication devices are available.
Design and Implementation of Low Power High Speed Symmetric Decoder Structure...Dr. Amarjeet Singh
The key objective of this project is to design a
decoder which can be used for hardware purposes.
Hardware, here accompanies with software which is more
we can discuss as a Software Defined Radio application. The
decoder implemented here offers to new radio equipment
(SDR), the flexibility of a programmable system. Nowadays,
the behavior of a communication system can be modified by
simply changing its software. Large tree decoder is made by
reusing smaller similar sub-modules. Thus the structure is
symmetric. The symmetric and regular structure of tree
decoder makes the system a less complexity one. The
structure obeys regularity and modularity concepts of VLSI
circuit, thus is easy to fabricate using cell library elements.
Design a Tree Decoder proposed architecture for SDR
application on FPGA. The Structures made here are
hardware synthesizable on FPGA board and are done in a
respective manner. The design to be implementing by using
Verilog-HDL language. The Simulation and Synthesis by
using Xilinx Vivado design suite.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and implementation of log domain decoder IJECEIAES
Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs a high data rate with very low BER.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
BLH Nobel has been recognized as a leader in weighing technology, process weighing and force measurement. They design and deliver innovative, accurate industry-leading weighing and force measurement solutions and supply both standardized and custom systems and serve customers from a wide range of industries.
The following document is an exhaustive compilation of technical terms used in process weighing, courtesy of BLH Nobel.
Convolutional encoding with Viterbi decoding is a good forward error correction technique suitable for channels affected by noise degradation. Fangled Viterbi decoders are variants of Viterbi decoder (VD) which decodes quicker and takes less memory with no error detection capability. Modified fangled takes it a step further by gaining one bit error correction and detection capability at the cost of doubling the computational complexity and processing time. A new efficient fangled Viterbi algorithm is proposed in this paper with less complexity and processing time along with 2 bit error correction capabilities. For 1 bit error correction for 14 bit input data, when compared with Modified fangled Viterbi decoder, computational complexity has come down by 36-43% and processing delay was halved. For a 2 bit error correction, when compared with Modified fangled decoder computational complexity decreased by 22-36%.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
-Study of the functionality of 2MB mother board, providing E1 data interfaces
-CMS LAB,TEST EQUIPMENT, QUALITY CONTROL. - ABOUT BEL,ROTATIONAL PROGRAM.-FPGA,ADSP,DSO,VHDL.
-E1 EUROPEAN DATA FORMAT , LINK, SPECIFICATION
ENCODING TECHNIQUES- HDB3, AMI
OPTICAL SWITCHING CONTROLLER USING FPGA AS A CONTROLLER FOR OCDMA ENCODER SYSTEMEditor IJCATR
This paper proposed a design of optical switching controller using FPGA for OCDMA encoder system. The encoder is one
of the new technologies that use to transmit the coded data in the optical communication system by using FPGA and optical switches.
It is providing a high security for data transmission due to all data will be transmitting in binary code form. The output signals from
FPGA are coded with a binary code that given to an optical switch before it signal modulate with the carrier and transmit to the
receiver. In this paper, AA and 55 data were used for source 1 and source 2. It is generated sample data and sent packet data to the
FPGA and stored it into RAM. The simulation results have done by using software Verilog Spartan 2 programming to simulate. After
that the output will produces at waveform to display the output. The main function of FPGA controlling unit is producing single pulse
and configuring optical switching system.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and implementation of log domain decoder IJECEIAES
Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs a high data rate with very low BER.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
BLH Nobel has been recognized as a leader in weighing technology, process weighing and force measurement. They design and deliver innovative, accurate industry-leading weighing and force measurement solutions and supply both standardized and custom systems and serve customers from a wide range of industries.
The following document is an exhaustive compilation of technical terms used in process weighing, courtesy of BLH Nobel.
Convolutional encoding with Viterbi decoding is a good forward error correction technique suitable for channels affected by noise degradation. Fangled Viterbi decoders are variants of Viterbi decoder (VD) which decodes quicker and takes less memory with no error detection capability. Modified fangled takes it a step further by gaining one bit error correction and detection capability at the cost of doubling the computational complexity and processing time. A new efficient fangled Viterbi algorithm is proposed in this paper with less complexity and processing time along with 2 bit error correction capabilities. For 1 bit error correction for 14 bit input data, when compared with Modified fangled Viterbi decoder, computational complexity has come down by 36-43% and processing delay was halved. For a 2 bit error correction, when compared with Modified fangled decoder computational complexity decreased by 22-36%.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
-Study of the functionality of 2MB mother board, providing E1 data interfaces
-CMS LAB,TEST EQUIPMENT, QUALITY CONTROL. - ABOUT BEL,ROTATIONAL PROGRAM.-FPGA,ADSP,DSO,VHDL.
-E1 EUROPEAN DATA FORMAT , LINK, SPECIFICATION
ENCODING TECHNIQUES- HDB3, AMI
OPTICAL SWITCHING CONTROLLER USING FPGA AS A CONTROLLER FOR OCDMA ENCODER SYSTEMEditor IJCATR
This paper proposed a design of optical switching controller using FPGA for OCDMA encoder system. The encoder is one
of the new technologies that use to transmit the coded data in the optical communication system by using FPGA and optical switches.
It is providing a high security for data transmission due to all data will be transmitting in binary code form. The output signals from
FPGA are coded with a binary code that given to an optical switch before it signal modulate with the carrier and transmit to the
receiver. In this paper, AA and 55 data were used for source 1 and source 2. It is generated sample data and sent packet data to the
FPGA and stored it into RAM. The simulation results have done by using software Verilog Spartan 2 programming to simulate. After
that the output will produces at waveform to display the output. The main function of FPGA controlling unit is producing single pulse
and configuring optical switching system.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
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Design and Implementing Novel Independent Real-Time Software Programmable DAQ...Editor IJCATR
The crucial features of many demanding applications like industry and aerospace are data acquisition and telemetry. It is
vital to observe and analyse the real time performance, in launch vehicle systems,so that designs can be certified and tuneablefactors
could be regulated to intensification the act and competence. At present used DAQ structures are of augmented size, weight and turn out
to be exorbitant and power hungry. This article introduce a new mission-independent real time software programmable DAQ system
using multipurpose MCU and sigma delta ADCs are planned,taking into account size, weight, costand act without compromiseon
precision, firmness and drift act. Additional digital filtering steps are also added to progress the system act. This system isproficientfor
directconnectionswithdiverse pressure and temperature sensors whichinterfaces 32 low frequency channel and two high frequency
channels. The system planned operates in two modes; one is data acquisition mode and another is program mode. Operativepower
lesseningmethods and wireless interface protocol between diverse data acquisition modules is also affected upon as avenues for future
work.
Design &Implementation of I2C Master Controller Interfaced With RAM Using VHDLIJERA Editor
In most of the applications, the physical systems require a real-time operation to interface high speed constraints. In most of the applications, the physical systems require a real-time operation to interface high speed constraints. The Inter Integrated Circuits (I2C) is a 2-wireed communication bus. Physically, it consists of 2 active wires: SDA (Serial Data), SCL (Serial Clock) and a ground connection. All I2C-bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the I2C-bus.
This paper focuses on the software implementation for I2C Driver and its interfacing with RAM. Specifically, this paper describes in detail an I2C Master connected to I 2C Slave using an I2C bus. The I2C protocol was given by Philips Semiconductors for faster devices to communicate with slower devices and each other without data loss. The complete module is designed in VHDL and simulated in Xilinx ISE 14.5.
Turbo codes are error-correcting codes with performance that is close to the
Shannon theoretical limit (SHA). The motivation for using turbo codes is
that the codes are an appealing mix of a random appearance on the channel
and a physically realizable decoding structure. The communication systems
have the problem of latency, fast switching, and reliable data transfer. The
objective of the research paper is to design and turbo encoder and decoder
hardware chip and analyze its performance. Two convolutional codes are
concatenated concurrently and detached by an interleaver or permuter in the
turbo encoder. The expected data from the channel is interpreted iteratively
using the two related decoders. The soft (probabilistic) data about an
individual bit of the decoded structure is passed in each cycle from one
elementary decoder to the next, and this information is updated regularly.
The performance of the chip is also verified using the maximum a posteriori
(MAP) method in the decoder chip. The performance of field-programmable
gate array (FPGA) hardware is evaluated using hardware and timing
parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers
a better global rate for the same component code performance, and reduced
delay, low hardware complexity, and higher frequency support.
Communication Protocols Augmentation in VLSI Design ApplicationsIJERA Editor
With the advancement in communication System, the use of various protocols got a sharp rise in the different applications. Especially in the VLSI design for FPGAs, ASICS, CPLDs, the application areas got expanded to FPGA based technologies. Today, it has moved from commercial application to the defence sectors like missiles & aerospace controls. In this paper the use of FPGAs and its interface with various application circuits in the communication field for data (textual & visual) & control transfer is discussed. To be specific, the paper discusses the use of FPGA in various communication protocols like SPI, I2C, and TMDS in synchronous mode in Digital System Design using VHDL/Verilog.
SMaRT is a 16-bit 2.5-address RISC-type single-cycl
e processor, which was recently designed
and successfully mapped into a FPGA chip in our ECE
department. In this paper, we use
SMaRT to run the well-known encryption algorithm, D
ata Encryption Standard. For
information security purposes, encryption is a must
in today’s sophisticated and ever-increasing
computer communications such as ATM machines and SI
M cards. For comparison and
evaluation purposes, we also map the same algorithm
on the HC12, a same-size but CISC-type
off-the-shelf microcontroller, Our results show tha
t compared to HC12, SMaRT code is only
14% longer in terms of the static number of instruc
tions but about 10 times faster in terms of the
number of clock cycles, and 7% smaller in terms of
code size. Our results also show that 2.5-
address instructions, a SMaRT selling point, amount
to 45% of the whole R-type instructions
resulting in significant improvement in static numb
er of instructions hence code size as well as
performance. Additionally, we see that the SMaRT sh
ort-branch range is sufficiently wide in
90% of cases in the SMaRT code. Our results also re
veal that the SMaRT novel concept of
locality of reference in using the MSBs of the regi
sters in non-subroutine branch instructions
stays valid with a remarkable hit rate of 95%!
SMaRT is a 16-bit 2.5-address RISC-type single-cycle processor, which was recently designed and successfully mapped into a FPGA chip in our ECE department. In this paper, we use SMaRT to run the well-known encryption algorithm, Data Encryption Standard. For information security purposes, encryption is a must in today’s sophisticated and ever-increasing computer communications such as ATM machines and SIM cards. For comparison and evaluation purposes, we also map the same algorithm on the HC12, a same-size but CISC-type off-the-shelf microcontroller, Our results show that compared to HC12, SMaRT code is only 14% longer in terms of the static number of instructions but about 10 times faster in terms of the number of clock cycles, and 7% smaller in terms of code size. Our results also show that 2.5- address instructions, a SMaRT selling point, amount to 45% of the whole R-type instructions resulting in significant improvement in static number of instructions hence code size as well as performance. Additionally, we see that the SMaRT short-branch range is sufficiently wide in 90% of cases in the SMaRT code. Our results also reveal that the SMaRT novel concept of locality of reference in using the MSBs of the registers in non-subroutine branch instructions stays valid with a remarkable hit rate of 95%!
Implementation of Algorithms For Multi-Channel Digital Monitoring ReceiverIOSR Journals
Abstract: Monitoring Receivers form an important constituent of the Electronic support. In Monitoring
Receiver we can monitor, demodulate or scan the multiple channels.
In this project, the Implementation of algorithm for multi channel digital monitoring receiver. The
implementation will carry out the channelization by the way of Digital down Converters (DDCs) and Digital
Base band Demodulation. The Intermediate Frequency (IF) at 10.7 MHz will be digitalized using Analog to
Digital Converter (ADC) with sampling frequency 52.5 MHz and further converted to Base band using DDCs.
Virtually all the digital receivers perform channel access using a DDC. The Base band data will be streamed to
the appropriate demodulators. Matlab Simulink will be used to simulate the logic modules before the
implementation. This system will be prototyped on an FPGA based COTS (Commercial-off-the-shelf)
development board. Xilinx System Generator will be used for the implementation of the algorithms.
Keywords: DDC, ADC, Digital Base band demodulation, IF, Monitoring Receiver.
This design consists of two communication protocols integrated in SoC and are UART & SPI. -Single bit input is provided for user to select either UART or SPI. In UART protocol TRANSMITTER passes the 32 bit data serially with parity bit to RECEIVER. In SPI protocol, RECEIVER passes the data to another RECEIVER which finally returns data back to TRANSMITTER and the TRANSMITTER passes data to TOP MODULE.
VoCoRoBo: Remote Speech Recognition and Tilt Sensing Multi-Robotic SystemSagun Man Singh Shrestha
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- These are slides of the talk given at IEEE International Conference on Software Testing Verification and Validation Workshop, ICSTW 2022.
1. Nagendra Sah, Gaurav Khurana / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.1796-1800
1796 | P a g e
Implementation of Serial Communication between PC and DSP
Processor Using Modbus Protocol
Nagendra Sah1
, Gaurav Khurana2
1
(Sr. Asstt. Professor, Electronics and Electrical Communication Department, PEC University of Technology,
Chandigarh
2
(M.E., Electronics and Electrical Communication Department, PEC University of Technology, Chandigarh
ABSTRACT
This paper described the principle,
application and implementation of serial
communication between PC and a Digital Signal
Processor (DSP). The TMS320F28031 which is a
type of DSPs made by Texas Instruments (TI) is
used in this implementation. This DSP processor
has serial communication interface (SCI) module
for serial communication. The SCI is a two− wire
asynchronous serial port, commonly known as a
UART (Universal Asynchronous
Receiver/Transmitter). The standard of Modbus
protocol is implemented for this serial
communication. The Modbus protocol provides an
industrial standard method that Modbus devices
use for parsing messages. PC (Personal
Computer) can read/write one or more registers of
DSP processor using Modbus communication. This
paper highlights the basics of Modbus protocol
and also explains the software detail of Modbus
implementation.
Keywords - DSP processor, Modbus protocol,
UART, serial communication
I. INTRODUCTION
Although all the real time signals are
analogue in nature but due to the huge advancement
in digital signal processing, all the signals are
processed in digital form. As we all know, Digital
signal processing has number of advantages over
analogue signal processing. To process the real time
signal in digital domain, first of all we have to convert
that analogue signal into digital signal using ADC
(Analog to Digital Converter) and after signal
processing; we have to convert digital output back
into analogue form by using DAC (Digital to Analog
Converter).
Due to huge advancement in the field of
VLSI (Very Large Scale Integration) in the past few
years, there are number of digital Integrated Chips
(IC’s) are available in the market for performing the
above task more efficiently and accurately. These
digital IC’s are commonly known as digital signal
processor (DSP). DSP has been used widely in auto
controller, image process, communication, network,
home electrical appliances, and so on. Currently, the
most widely used product come from Texas
instruments (TI) which takes up almost 60 % of the
market [1]. TMS320F28031 is a chip which is a
product made by TI. Unlike some other chips, it uses
an advanced Havard type architecture that maximizes
processing power by maintaining two separate
memory bus structures, one memory section for
storing program and other for storing data. This will
increase the program execution speed. This chip has
several integrated peripherals like ADC, SCI, Timer
and PWM (Pulse Width Modulator) etc. [2].
The Modbus is one of the most common
serial communication protocol used in industrial
application for process control. Using Modbus
protocol a number of controllers and intelligent
devices and communication with each other over any
network. Actually Modbus protocol defines a
messaging structure which is universally accepted and
used. In this paper, we have established a serial
communication between PC and DSP processor using
Modbus protocol. The master sends a command in
hexadecimal and slave responds with its response in
hexadecimal too. In order to display the result,
software called Modbus tester is used. Same software
is also used to configure the communication
parameters like communication mode, baud rate, start
bits, stop bits and parity bits etc.
II. HARDWARE STRUCTURE
A. SCI
TMS320F28031 DSP processor has an on
chip serial communication interface (SCI) as one of
its peripheral in its core. SCI is a two−wire
asynchronous serial port and it supports digital
communications between the CPU (Central
Processing Unit) and other asynchronous peripherals
that use the standard non-return-zero (NRZ) format.
The SCI receiver and transmitter are double-buffered
and each has a 4-level deep FIFO (First in First Out)
for reducing servicing overhead. Both have their own
separate enable and interrupt bits and both can be
operated independently for half-duplex
communication, or simultaneously for full duplex
communication. To ensure data integrity, the SCI
checks received data for break detection, parity,
overrun, and framing errors. The bit rate is
programmable to over 65000 different speeds through
a 16-bit baud select register [3].
SCI module has two external pins for serial
communication that is SCITXD (SCI transmit output
2. Nagendra Sah, Gaurav Khurana / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.1796-1800
1797 | P a g e
pin) and SCIRXD (SCI receive input pin). Serial
Transmission and reception operations can be
accomplished through interrupt driven or polled
algorithms. Here interrupt driven technique is used for
communication in full duplex mode.
Major elements of SCI module is shown in figure 1
and it includes:
TXD pin
RXD pin
Fig. 1 Internal Device Structure
A transmitter (TX) and its major registers
(upper half of Figure 1) are:
SCITXBUF register (SCI transmitter data
buffer register) - it Contains data (loaded by the
processor) to be transmitted to the remote PC.
TXSHF register (SCI transmitter shift register) - It
accepts data from register SCITXBUF and shifts data
onto the SCITXD pin, one bit at a time.
A receiver (RX) and its major registers
(lower half of Figure 1) include:
RXSHF register (SCI receiver shift register) - It
shifts in the data from SCIRXD pin, one bit at a time.
SCIRXBUF register (SCI receiver data buffer
register) - It contains data to be read by the DSP
processor. Data from a remote PC is loaded into
register RXSHF and then into registers SCIRXBUF.
III. MODBUS PROTOCOL
The Modbus is a serial communications
protocol published by Modicon in 1979. Modbus
protocol defines a standard message structure with
universal recognition and usage regardless of the type
of networks over which any two devices
communicate. It is a master slave communication
protocol. It describes the process a master uses to
request an access to slave, and how the slave will
respond to these requests, and how errors will be
detected and reported. Master can initiate transactions
(called ‘queries’) and slave respond by supplying the
requested data to the master, or by taking the action
requested in the query. The master can address
individual slaves, or can initiate a broadcast message
to all slaves. Slaves return a message (called a
‘response’) to queries that are addressed to them
individually. Responses are not returned to broadcast
queries from the master. Figure 2 shows the query
response cycle of Modbus communication.
Fig. 2 Modbus master-slave query-response cycle
As shown in figure 2, master’s query consists
of slave device (or broadcast) address, a function code
defining the requested action, any data to be sent, and
an error checking field. The slave’s response contains
fields confirming the action taken, any data to be
returned, and an error–checking field. Slave confirms
the action taken by sending the echo of function code
sent by the master.
Table I shows the Application Data Unit
(ADU) and Protocol Data Unit (PDU) of Modbus
protocol. PDU is consisting of function field (1 byte)
and data field (variable bytes) and ADU is consisting
of address field (1 byte), PDU and error checking
field (2 bytes) [4].
Table I Modbus data format
Protocol data unit
(PDU )
Application Data unit(ADU)
1 byte 1 byte Variable 2 bytes
Address
field
Function
field
Data field Error
checking
field
If the slave makes a normal response, the
function code in the response is an echo of the
function code in the query. If an error occurred in
receipt of the message, or if the slave is unable to
perform the requested action, the slave will construct
an error message by modifying the function code (set
the MSB (Most significant Bit) of function code) to
indicate that the response is an error response, and the
data bytes contain a code that describes the error [5].
Some of the commonly used function codes are
shown in table II.
SCITXBUF
Transmitter
section
SCIRXBUF Receiver
section
3. Nagendra Sah, Gaurav Khurana / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.1796-1800
1798 | P a g e
Table II List of commonly used function
codes in Modbus protocol
Code Name
01 Read single coil status
02 Read input status
03 Read multiple holding registers
04 Read multiple input registers
05 Write single coil
07 Read Exception Status
15 Write multiple coils
16 Write multiple registers
23 Read/Write multiple registers
Modbus protocol can be established in two kinds of
transmission mode: ASCII (American Standard Code
for Information Interchange) mode or RTU (Remote
Terminal Unit) mode. In ASCII mode, each 8–bit byte
in a message is sent as two ASCII characters. In RTU
mode, each 8–bit byte in a message contains two 4–bit
hexadecimal characters. The main advantage of RTU
mode is that its greater character density allows better
data throughput than ASCII for the same baud rate.
Modbus protocol has the parity check, besides, the
ASCII mode uses the LRC (Longitudinal Redundancy
Check) and the RTU mode uses 16 CRC (Cyclical
Redundancy Check).
Table III is a comparison between ASCII mode and
RTU mode.
Table III Comparison of ASCII and RTU
mode
According to Table III, the data transmission rate
of ASCII mode is a little lower than RTU mode. So,
when need to send large data, user always uses RTU
mode. The standard Modbus protocol is to use a RS-
232C compatible serial interface, which defines the
port pin, cable, digital signal transmission baud rate,
parity.
IV. IMPLEMENTATION OF COMMUNICATION
A. Configuration Setting
In order to implement the Modbus protocol
communication between PC and DSP processor, first
of all we should configure both PC and DSP
processor for the same communication mode and
same baud rate that is 9600 bps (bits per second) [6].
As explained earlier, there are two modes of serial
communication in Modbus protocol that is ASCII
mode and RTU mode. In this implementation we have
used the later one. Configuration used in this
implementation is shown in table IV.
Table IV PC and DSP processor communication
Configuration
Communication
Mode
Remote Terminal Unit
(RTU)
Baud Rate 9600 bps
Data bit 8 bits
Stop bit 1 bit
Parity bit None
Baud rate is nothing but data transfer rate which must
be same at both the terminals (PC and DSP
Processor). PC baud rate is configured by using
Modbus communication interface software named
Modbus tester and DSP processor’s baud rate is
configured by using its control registers. Following
formulas are in this process:
Baud rate = Sysclk / (BRR+1) × 8 (1)
BRR = Sysclk ( aud rate ) 1
(2)
In “Eq. (1)”, the Sysclk stands for system clock
frequency and the RR in “Eq. (2)” is the value of
SCIHBAUD and SCILBAUD registers that you
should configure.
After setting the proper baud rate, the serial
communication is established by using two wire
communication method. Modbus protocol is
master/slave protocol and communication can be
initiated by master only and here PC is working as
master and DSP Processor is working as slave. So PC
will initiate this communication and sends a command
to read DSP Processor’s 7 input registers. Each
register is of 2 bytes. But data field in Modbus
protocol is of 8 bits so each register is represented by
two data bytes. First byte represents higher byte and
second byte represents lower byte. Hence 7 register is
equal to 14 bytes. Slave address is 8 bit long and it is
settable. In this project, we have used only one slave
and its address is 01.
B. Software Flow
This communication is implemented in TI
tool code compose studio. Code Composer Studio™
(CCStudio) is an integrated development environment
(IDE) for Texas Instruments (TI) embedded processor
families. CCStudio comprises a suite of tools used to
develop and debug embedded applications. Timer 0
interrupt service routine of TMS320F28031 is used in
this implementation. Timer 0 is configured to generate
an interrupt after every 20 microsecond. In timer 0
ISR (interrupt service routine), we check the flag bit
showing the reception of data byte. If this flag bit is
Mode Begi
nnin
g
mar
ks
Endi
ng
mar
ks
Check Trans
missio
n
efficien
cy
Progra
m
Process
ing
ASCI
I
:
(col
on)
CR,
LF
LRC low
Direct,
easy to
debuggi
ng
RTU Non Non CRC High
Indirect,
slightly
comple
x
4. Nagendra Sah, Gaurav Khurana / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.1796-1800
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set, it shows that byte has been received. Then we
process the received the data to extract the useful
information form this data [7].
First byte is slave ID (slave address). So first
of all, we compare the received byte with the address
of that slave. It received byte matches with the slave
ID. It means that next whole data frame is addressed
to this slave and we will process the whole data frame
otherwise we will ignore the whole data frame. Then
we go for CRC check. It will tell about the frame
validity. If frame is invalid, program will generate a
response showing error in received frame using
exception code. Next step is extracting the
information from function code. List of commonly
used function code is shown in table II. Then create
the slave response according the function code.
C. Read Input Registers of DSP Processor
Here PC is master and will initiate the
communication so it is working as transmitter and
DSP Processor’s response is received by the PC [8].
The communication traffic is shown in figure 3.
Fig. 3 Modbus communication traffic
As shown in figure 3, TX (Transmitter)
represents the command sent by PC to DSP processor
and RX (Receiver) is the response sent by DSP
processor to PC. Analysis of TX data is given in table
V.
Table V Data sent from PC to DSP
Processor
Code (Hex) Meaning
01 Slave Address.
04 Function code( read multiple
input register)
00 Starting address of input
registers(higher)
00 Starting address of input register
(lower)
00 Number of registers (higher)
07 Number of registers ( lower)
B1 CRC (higher)
C8 CRC (lower)
From table V it is clear that, PC wants to
read multiple input registers of slave whose address is
01. Starting address (16 bits) of these registers is
0000h is also given by the master in its command and
number register is 0007h. Last two bytes are CRC
check bits for detecting the error in the transmitted
code.
RX is the response sent by DSP Processor to
PC and analysis of Rx is given in table VI:
Table VIData sent from DSP Processor to PC
Code (Hex) Meaning
01 Slave Address.
04 Function code (echo of function
code sent by master, as no error is
detected by slave in Tx code. If
slave detect some error in Tx code
then it exception code which is
also echo of original function code
with its MSB is equal to logic 1)
0E 14 bytes(2*7 registers) in data
field
00 Content of first register (higher)
00 Content of first register (lower)
00 Content of second register (higher)
96 Content of second register (lower)
00 Content of third register (higher)
B9 Content of third register (lower)
00 Content of fourth register (higher)
5A Content of fourth register (lower)
00 Content of fifth register (higher)
D2 Content of fifth register (lower)
00 Content of sixth register (higher)
91 Content of sixth register (lower)
00 Content of seventh register
(higher)
71 Content of seventh register (lower)
C2 CRC (higher)
E4 CRC (lower)
It is clear from table VI that, each 16 bit register is
represented by two data fields each of 8 bit long.
Hence content each register is shown in hexadecimal
and decimal in table VII.
Table VII 16 bit register content in hexadecimal
and decimal format
Register
number
Content in
Hex
Content in
Decimal
01 0000h 00
02 0096h 150
03 00B9h 185
04 005Ah 90
05 00D2h 210
06 0091h 145
07 0071h 113
5. Nagendra Sah, Gaurav Khurana / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 4, Jul-Aug 2013, pp.1796-1800
1800 | P a g e
V. RESULTS AND DISCUSSION
Results are shown in figure 4. It is clear from
figure 4 that master (PC) send a command to read 7
input registers (14 bytes) of DSP processor and then
DSP processor create a response message consist of
19 bytes (1 byte slave ID, 1 byte function code, 1 byte
to show number of bytes in data unit (that is 14 in this
example), 14 bytes of data and 2 bytes of CRC).
Modbus tester software check integrity of slave
response if response is found to be valid then it extract
14 byte data unit from 19 byte slave response and
display the result in decimal as shown in figure 4.
Fig. 4 results display in Modbus tester
VI. CONCLUSION
Modbus protocol is implemented and serial
communication between PC and DSP Processor is
established and results are displayed using Modbus
tester software. Thus, we can easily interface a
number of digital IC’s like DSP processors with our
PC using Modbus protocol. So this communication
technique can be one of well choice in industrial
control applications.
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