This work is based on the implementation of real-time speech recognition using DSP algorithms such as Chebyshev IIR filters, accelerometer for tilt-sensing and establishment of short-range wireless secure link with ARC4 cipher, all using low-cost 8-bit ATmega microcontrollers. The robot implements a simple but effective algorithm for comparing the spoken word with a dictionary of fingerprints using a modified Euclidean distance calculation. It also includes the ability to securely control the navigation of multiple robots located at remote locations wirelessly from the Control Module and also gather the various environmental data collected by the Robot Modules and display them in the back to Control. Considering the time-critical algorithms actually requiring large computations as well as a variety of sensors interfaced in the system, this project can demonstrate how one can build an expansible multi-robotic system from cheap and ubiquitous electronics.
This document discusses serial communication using the 8051 microcontroller. It contrasts serial versus parallel communication and asynchronous versus synchronous transmission. It describes how to program the baud rate using Timer 1 registers and explains data transfer using the SBUF, SCON, TI and RI registers. It also discusses connecting the 8051 to RS-232 via a MAX232 chip and programming the 8051 to transmit and receive data using interrupts instead of polling flags.
The document discusses serial port programming for the 8051 microcontroller. It describes how serial communication works using one bit at a time instead of parallel communication which transfers all bits at once. It explains the registers and pins used for serial communication on the 8051 including the serial data buffer (SBUF) register, serial control (SCON) register, and MAX232 voltage converter. It provides details on programming the 8051 for serial data transmission and reception, including using the TI and RI flags to indicate when data has been sent or received.
Multiple Channel Serial I/O Interfacing using FPGA Kitijsrd.com
This document discusses the development of an FPGA unit to interface between a main processing unit (MPU) and multiple digital input/output (DIO) boards via serial communication. The FPGA unit automatically reads and writes data from the DIO boards via serial protocols and shares this data with the MPU via registers. This reduces the communication burden on the MPU and allows it to connect to more DIO boards. The FPGA unit is implemented using VHDL and includes features like error checking, addressing individual DIO boards, and handling the serial communication protocol to efficiently transfer data between the MPU and DIO boards via the FPGA unit.
This presentation discusses the Serial Communication features in 8051, the support for UART. It also discusses serial vs parallel communication, simplex, duplex and full-duplex modes, MAX232, RS232 standards
This document describes the development and implementation of the SPI and UART serial communication protocols in Verilog HDL. Both protocols were implemented considering different operating modes like master/slave and transmit/receive modes. Verilog was used to simulate the protocols in Xilinx ISE Design Suite and Modelsim. A single pin allows selecting between the SPI and UART modes.
This document discusses serial communication basics and the 8051 microcontroller's serial port functionality. It describes asynchronous and synchronous serial transmission modes, with asynchronous being character-oriented and using start and stop bits, while synchronous transfers data in blocks. It also outlines the 8051's SBUF, SCON, and PCON registers which control serial communication and data rates. The SCON register controls the serial port mode which can be set to modes 0-3, each with different bit length, clocking, and baud rate determination. The PCON register allows doubling the baud rate by setting the SMOD bit and puts the chip into low power modes.
This document discusses serial vs parallel data transfer and describes serial communication methods. It explains that serial communication requires converting data to serial bits and transmitting them one bit at a time over a single line, while parallel communication transfers all bits at once over multiple lines. It also describes synchronous and asynchronous serial communication, UART/USART chips used for serial interfaces, and registers involved in serial data transfer on the 8051 microcontroller.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
This document discusses serial communication using the 8051 microcontroller. It contrasts serial versus parallel communication and asynchronous versus synchronous transmission. It describes how to program the baud rate using Timer 1 registers and explains data transfer using the SBUF, SCON, TI and RI registers. It also discusses connecting the 8051 to RS-232 via a MAX232 chip and programming the 8051 to transmit and receive data using interrupts instead of polling flags.
The document discusses serial port programming for the 8051 microcontroller. It describes how serial communication works using one bit at a time instead of parallel communication which transfers all bits at once. It explains the registers and pins used for serial communication on the 8051 including the serial data buffer (SBUF) register, serial control (SCON) register, and MAX232 voltage converter. It provides details on programming the 8051 for serial data transmission and reception, including using the TI and RI flags to indicate when data has been sent or received.
Multiple Channel Serial I/O Interfacing using FPGA Kitijsrd.com
This document discusses the development of an FPGA unit to interface between a main processing unit (MPU) and multiple digital input/output (DIO) boards via serial communication. The FPGA unit automatically reads and writes data from the DIO boards via serial protocols and shares this data with the MPU via registers. This reduces the communication burden on the MPU and allows it to connect to more DIO boards. The FPGA unit is implemented using VHDL and includes features like error checking, addressing individual DIO boards, and handling the serial communication protocol to efficiently transfer data between the MPU and DIO boards via the FPGA unit.
This presentation discusses the Serial Communication features in 8051, the support for UART. It also discusses serial vs parallel communication, simplex, duplex and full-duplex modes, MAX232, RS232 standards
This document describes the development and implementation of the SPI and UART serial communication protocols in Verilog HDL. Both protocols were implemented considering different operating modes like master/slave and transmit/receive modes. Verilog was used to simulate the protocols in Xilinx ISE Design Suite and Modelsim. A single pin allows selecting between the SPI and UART modes.
This document discusses serial communication basics and the 8051 microcontroller's serial port functionality. It describes asynchronous and synchronous serial transmission modes, with asynchronous being character-oriented and using start and stop bits, while synchronous transfers data in blocks. It also outlines the 8051's SBUF, SCON, and PCON registers which control serial communication and data rates. The SCON register controls the serial port mode which can be set to modes 0-3, each with different bit length, clocking, and baud rate determination. The PCON register allows doubling the baud rate by setting the SMOD bit and puts the chip into low power modes.
This document discusses serial vs parallel data transfer and describes serial communication methods. It explains that serial communication requires converting data to serial bits and transmitting them one bit at a time over a single line, while parallel communication transfers all bits at once over multiple lines. It also describes synchronous and asynchronous serial communication, UART/USART chips used for serial interfaces, and registers involved in serial data transfer on the 8051 microcontroller.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
This document discusses serial communication with the 8051 microcontroller. It begins by contrasting serial and parallel communication, listing advantages of serial. It then explains asynchronous serial communication protocols. Next, it describes half and full duplex transmission, data framing, transfer rates, and the RS-232 standard. Finally, it provides examples of initializing and programming the 8051 for serial communication using timers, registers, and algorithms.
This document summarizes the interfacing of a Polaroid Ultrasonic Ranging Kit (PURK) to an Intel System Development Kit-85 (SDK-85) microprocessor to provide distance sensing capabilities for an autonomous robot. The interface required modifying the PURK circuitry to synchronize its signals with the SDK-85. A hardware interface was developed using CMOS and TTL logic devices to translate signal levels. Software was also developed to input the PURK's distance readings, synchronizing with its status signals under microprocessor control. The interface allows the microprocessor to access the PURK's distance measurements for further processing and autonomous robot control.
This document provides an overview of RS232 and E1 communication standards. It discusses the classification of communication, RS232 data format including baud rate, transfer modes, cabling and pinouts. It then describes the E1 frame structure including timeslots and frame alignment. The document includes block diagrams of an RS232 to E1 converter.
This document discusses serial communication concepts and programming on 8051 microcontrollers. It explains the basics of serial vs parallel communication and asynchronous transmission using start and stop bits. It describes the SCON and SMOD registers used for serial communication and the various modes of operation including fixed and variable baud rates. The document provides code examples for transmitting and receiving data over serial in 8051 assembly language and demonstrates using Keil simulator.
Serial data communication involves transmitting digital data between a source and receiver using a communications link. It requires a transmitter to encode the digital data, a communications link to carry the signal, and a receiver to decode the signal. Common components are computers, modems, cables. Transmission can be simplex, half duplex, or full duplex. Formats define start/stop bits, data/parity bits, and transmission speed. Protocols establish rules for data exchange, flow control, error checking, and more. Troubleshooting tools like breakout boxes, null modems, and protocol analyzers help test and diagnose serial communication circuits and connections.
A universal asynchronous receiver-transmitter is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable.
Total slides: 73
Universal Asynchronous Receiver Transmitter (UART)
Introduction to Serial Communication
Types of Transmission
Simplex Communication
Duplex Communication
Half Duplex Communication
Full Duplex Communication
Methods of Serial data Transmission
Synchronous serial data transfer
Asynchronous serial data transfer
Differences Synchronous Asynchronous
Data Transfer Rate
Calculation of Baud Rate
SCON Register
SBUF Register
Writing to the Serial port
Reading the Serial port
PCON Register
Programming of transmission byte serially
Programming of reception of byte serially
Examples
The Universal Asynchronous Receiver/Transmitter (UART) converts parallel data from a microprocessor into serial data for transmission and vice versa. It uses start, stop and optional parity bits to synchronize the sending and receiving units for asynchronous serial communication. Common UART models include 8250, 16450 and 16550 which have improved capabilities like FIFO buffers and higher transmission speeds. The UART uses a set of registers to control communication parameters and transfer data. It can detect errors like overrun, framing and parity during serial transmission and reception.
This Masterclass is divided in two parts. The first one presents a brief outline of the UHF passive RFID technology (air interface, protocol and new Gen2V2 features). The second one, devoted to Privacy Impact Assessment, presents the European Recommendation and the recently published EN 16571 standard.
A Network-on-chip (NOC) is a new paradigm in complex system-on-chip (SOC) designs that provide efficient on chip communication networks. The data is routed through the networks in terms of packets. The routing of data is mainly done by routers. So the architecture of router must be an efficient one with a lower latency and higher throughput. In this project we designed, implemented and analyzed crossbar router architectures for a network on chip communication in a FPGA. The routers have five ports, four ports connected to other ports in four different directions and the fifth port connected to the processing element through a network interface. Our Proposed architecture contains 4x4 crossbar switch, switch allocator, path and channel request, data ram and 4 i/o ports. The datas ere sent through the routers in order to prevent congestion. The swich allocator and VC allocator are used to allocate the datas in priority order. The switch allocator will allocate the datas according to the path and channel request. The XY algorithm with a scheduler is used in this project for proper destination of the datas.
The document discusses UART (Universal Asynchronous Receiver/Transmitter) communication. It describes how UARTs allow for asynchronous serial communication between devices using only 2 wires by converting parallel data to serial and vice versa. The UART communication process involves a transmitting UART adding start, stop and optionally parity bits to data before transmitting it serially bit-by-bit to a receiving UART which reconstructs the parallel data. It also discusses the TTL and RS-232 physical layer standards for UART.
This document discusses serial communication using the 8051 microcontroller. It describes the basics of serial vs parallel communication and asynchronous vs synchronous serial communication. It then discusses the specifics of the 8051 serial port, including the use of a UART, duplex modes, start/stop bits, parity bits, and data transfer rates. It also covers the RS-232 standard for serial communication and how to interface the 8051 to RS-232 using a line driver chip like the MAX232.
The document discusses an RFID authentication protocol based on Generation 2 (Gen2) standards that aims to provide security and privacy. It summarizes the Gen2 protocol, introduces Duc's CRC-based protocol, and proposes a secured Gen2 protocol. This secured Gen2 protocol uses a central key stored in the backend database to authenticate tags and provides defense against tracing, skimming, and spoofing attacks through random selection of key segments and use of access passwords. Future work could focus on implementing encryption on passive tags and adapting protocols from active tags to passive tags with low computational cost.
The document describes overhead bytes in the Synchronous Optical Networking (SONET) and Synchronous Digital Hierarchy (SDH) protocols. It explains that certain bytes, such as J0 and B1, are used for regenerator section trace and byte interleaved parity to ensure connection integrity and identify individual signals after multiplexing. Other bytes, like D1-D3 and E1, are used for embedded operations channels and orderwires. The document also describes pointer bytes H1-H3 that indicate the offset of the synchronous payload envelope and compensate for timing variations, and Maintenance overhead bytes like B2, K1-K2, and S1 that provide automatic protection switching, additional data communications, and
In telecommunication and computer science, serial communication is the process of sending data one bit at a time, sequentially, over a communication channel or computer bus. This is in contrast to parallel communication, where several bits are sent as a whole, on a link with several parallel channels.
Serial communication is used for all long-haul communication and most computer networks, where the cost of cable and synchronization difficulties make parallel communication impractical. Serial computer buses are becoming more common even at shorter distances, as improved signal integrity and transmission speeds in newer serial technologies have begun to outweigh the parallel bus's advantage of simplicity (no need for serializer and deserializer, or SerDes) and to outstrip its disadvantages (clock skew, interconnect density). The migration from PCI to PCI Express is an example.
This document provides an overview of computer architecture and microprocessor concepts including:
1. It discusses different number systems such as binary, decimal, hexadecimal and their conversions. It also covers logic gates, Boolean algebra and other digital logic concepts.
2. It introduces microprocessors and their general architecture. It discusses microprocessor operations such as memory reads/writes and I/O reads/writes.
3. It covers computer languages from machine language to assembly and high-level languages. It also discusses compilers and interpreters.
This document describes a summer internship project to design a universal asynchronous receiver transmitter (UART) using an FPGA. The objectives are to gain experience working with mentors on real-world hardware and software projects. The assigned project is to create a UART device using HDL that can establish serial communication between two devices. It will include data generation, transmission, reception, and error checking blocks. Designing the UART will provide an understanding of serial communication principles like framing, baud rates, and throughput. Completing the project will help develop teamwork and industry skills over the 2 month internship period.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The document discusses analog to digital conversion. It explains that analog signals are continuous while digital signals are discrete in both time and amplitude. It describes how analog signals are converted to digital using sample and hold circuits, quantization, and encoding. The conversion process filters the analog signal, takes samples at regular time intervals, rounds samples to the nearest digital value, and encodes samples into binary format. The document also provides examples of analog to digital converters and discusses considerations like resolution, dynamic range, and signal conditioning.
This document describes the implementation of a Viterbi decoder using VHDL. It begins with background on convolutional encoding, the Viterbi algorithm for decoding convolutional codes, and the basic structure of a Viterbi decoder. It then discusses the design and simulation of a rate 1/2 constraint length 3 Viterbi decoder in VHDL targeting the Spartan-3A FPGA. Simulation results and comparisons to other FPGA devices are presented.
Design and Implementation of Low Power High Speed Symmetric Decoder Structure...Dr. Amarjeet Singh
The key objective of this project is to design a
decoder which can be used for hardware purposes.
Hardware, here accompanies with software which is more
we can discuss as a Software Defined Radio application. The
decoder implemented here offers to new radio equipment
(SDR), the flexibility of a programmable system. Nowadays,
the behavior of a communication system can be modified by
simply changing its software. Large tree decoder is made by
reusing smaller similar sub-modules. Thus the structure is
symmetric. The symmetric and regular structure of tree
decoder makes the system a less complexity one. The
structure obeys regularity and modularity concepts of VLSI
circuit, thus is easy to fabricate using cell library elements.
Design a Tree Decoder proposed architecture for SDR
application on FPGA. The Structures made here are
hardware synthesizable on FPGA board and are done in a
respective manner. The design to be implementing by using
Verilog-HDL language. The Simulation and Synthesis by
using Xilinx Vivado design suite.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This document discusses serial communication with the 8051 microcontroller. It begins by contrasting serial and parallel communication, listing advantages of serial. It then explains asynchronous serial communication protocols. Next, it describes half and full duplex transmission, data framing, transfer rates, and the RS-232 standard. Finally, it provides examples of initializing and programming the 8051 for serial communication using timers, registers, and algorithms.
This document summarizes the interfacing of a Polaroid Ultrasonic Ranging Kit (PURK) to an Intel System Development Kit-85 (SDK-85) microprocessor to provide distance sensing capabilities for an autonomous robot. The interface required modifying the PURK circuitry to synchronize its signals with the SDK-85. A hardware interface was developed using CMOS and TTL logic devices to translate signal levels. Software was also developed to input the PURK's distance readings, synchronizing with its status signals under microprocessor control. The interface allows the microprocessor to access the PURK's distance measurements for further processing and autonomous robot control.
This document provides an overview of RS232 and E1 communication standards. It discusses the classification of communication, RS232 data format including baud rate, transfer modes, cabling and pinouts. It then describes the E1 frame structure including timeslots and frame alignment. The document includes block diagrams of an RS232 to E1 converter.
This document discusses serial communication concepts and programming on 8051 microcontrollers. It explains the basics of serial vs parallel communication and asynchronous transmission using start and stop bits. It describes the SCON and SMOD registers used for serial communication and the various modes of operation including fixed and variable baud rates. The document provides code examples for transmitting and receiving data over serial in 8051 assembly language and demonstrates using Keil simulator.
Serial data communication involves transmitting digital data between a source and receiver using a communications link. It requires a transmitter to encode the digital data, a communications link to carry the signal, and a receiver to decode the signal. Common components are computers, modems, cables. Transmission can be simplex, half duplex, or full duplex. Formats define start/stop bits, data/parity bits, and transmission speed. Protocols establish rules for data exchange, flow control, error checking, and more. Troubleshooting tools like breakout boxes, null modems, and protocol analyzers help test and diagnose serial communication circuits and connections.
A universal asynchronous receiver-transmitter is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable.
Total slides: 73
Universal Asynchronous Receiver Transmitter (UART)
Introduction to Serial Communication
Types of Transmission
Simplex Communication
Duplex Communication
Half Duplex Communication
Full Duplex Communication
Methods of Serial data Transmission
Synchronous serial data transfer
Asynchronous serial data transfer
Differences Synchronous Asynchronous
Data Transfer Rate
Calculation of Baud Rate
SCON Register
SBUF Register
Writing to the Serial port
Reading the Serial port
PCON Register
Programming of transmission byte serially
Programming of reception of byte serially
Examples
The Universal Asynchronous Receiver/Transmitter (UART) converts parallel data from a microprocessor into serial data for transmission and vice versa. It uses start, stop and optional parity bits to synchronize the sending and receiving units for asynchronous serial communication. Common UART models include 8250, 16450 and 16550 which have improved capabilities like FIFO buffers and higher transmission speeds. The UART uses a set of registers to control communication parameters and transfer data. It can detect errors like overrun, framing and parity during serial transmission and reception.
This Masterclass is divided in two parts. The first one presents a brief outline of the UHF passive RFID technology (air interface, protocol and new Gen2V2 features). The second one, devoted to Privacy Impact Assessment, presents the European Recommendation and the recently published EN 16571 standard.
A Network-on-chip (NOC) is a new paradigm in complex system-on-chip (SOC) designs that provide efficient on chip communication networks. The data is routed through the networks in terms of packets. The routing of data is mainly done by routers. So the architecture of router must be an efficient one with a lower latency and higher throughput. In this project we designed, implemented and analyzed crossbar router architectures for a network on chip communication in a FPGA. The routers have five ports, four ports connected to other ports in four different directions and the fifth port connected to the processing element through a network interface. Our Proposed architecture contains 4x4 crossbar switch, switch allocator, path and channel request, data ram and 4 i/o ports. The datas ere sent through the routers in order to prevent congestion. The swich allocator and VC allocator are used to allocate the datas in priority order. The switch allocator will allocate the datas according to the path and channel request. The XY algorithm with a scheduler is used in this project for proper destination of the datas.
The document discusses UART (Universal Asynchronous Receiver/Transmitter) communication. It describes how UARTs allow for asynchronous serial communication between devices using only 2 wires by converting parallel data to serial and vice versa. The UART communication process involves a transmitting UART adding start, stop and optionally parity bits to data before transmitting it serially bit-by-bit to a receiving UART which reconstructs the parallel data. It also discusses the TTL and RS-232 physical layer standards for UART.
This document discusses serial communication using the 8051 microcontroller. It describes the basics of serial vs parallel communication and asynchronous vs synchronous serial communication. It then discusses the specifics of the 8051 serial port, including the use of a UART, duplex modes, start/stop bits, parity bits, and data transfer rates. It also covers the RS-232 standard for serial communication and how to interface the 8051 to RS-232 using a line driver chip like the MAX232.
The document discusses an RFID authentication protocol based on Generation 2 (Gen2) standards that aims to provide security and privacy. It summarizes the Gen2 protocol, introduces Duc's CRC-based protocol, and proposes a secured Gen2 protocol. This secured Gen2 protocol uses a central key stored in the backend database to authenticate tags and provides defense against tracing, skimming, and spoofing attacks through random selection of key segments and use of access passwords. Future work could focus on implementing encryption on passive tags and adapting protocols from active tags to passive tags with low computational cost.
The document describes overhead bytes in the Synchronous Optical Networking (SONET) and Synchronous Digital Hierarchy (SDH) protocols. It explains that certain bytes, such as J0 and B1, are used for regenerator section trace and byte interleaved parity to ensure connection integrity and identify individual signals after multiplexing. Other bytes, like D1-D3 and E1, are used for embedded operations channels and orderwires. The document also describes pointer bytes H1-H3 that indicate the offset of the synchronous payload envelope and compensate for timing variations, and Maintenance overhead bytes like B2, K1-K2, and S1 that provide automatic protection switching, additional data communications, and
In telecommunication and computer science, serial communication is the process of sending data one bit at a time, sequentially, over a communication channel or computer bus. This is in contrast to parallel communication, where several bits are sent as a whole, on a link with several parallel channels.
Serial communication is used for all long-haul communication and most computer networks, where the cost of cable and synchronization difficulties make parallel communication impractical. Serial computer buses are becoming more common even at shorter distances, as improved signal integrity and transmission speeds in newer serial technologies have begun to outweigh the parallel bus's advantage of simplicity (no need for serializer and deserializer, or SerDes) and to outstrip its disadvantages (clock skew, interconnect density). The migration from PCI to PCI Express is an example.
This document provides an overview of computer architecture and microprocessor concepts including:
1. It discusses different number systems such as binary, decimal, hexadecimal and their conversions. It also covers logic gates, Boolean algebra and other digital logic concepts.
2. It introduces microprocessors and their general architecture. It discusses microprocessor operations such as memory reads/writes and I/O reads/writes.
3. It covers computer languages from machine language to assembly and high-level languages. It also discusses compilers and interpreters.
This document describes a summer internship project to design a universal asynchronous receiver transmitter (UART) using an FPGA. The objectives are to gain experience working with mentors on real-world hardware and software projects. The assigned project is to create a UART device using HDL that can establish serial communication between two devices. It will include data generation, transmission, reception, and error checking blocks. Designing the UART will provide an understanding of serial communication principles like framing, baud rates, and throughput. Completing the project will help develop teamwork and industry skills over the 2 month internship period.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The document discusses analog to digital conversion. It explains that analog signals are continuous while digital signals are discrete in both time and amplitude. It describes how analog signals are converted to digital using sample and hold circuits, quantization, and encoding. The conversion process filters the analog signal, takes samples at regular time intervals, rounds samples to the nearest digital value, and encodes samples into binary format. The document also provides examples of analog to digital converters and discusses considerations like resolution, dynamic range, and signal conditioning.
This document describes the implementation of a Viterbi decoder using VHDL. It begins with background on convolutional encoding, the Viterbi algorithm for decoding convolutional codes, and the basic structure of a Viterbi decoder. It then discusses the design and simulation of a rate 1/2 constraint length 3 Viterbi decoder in VHDL targeting the Spartan-3A FPGA. Simulation results and comparisons to other FPGA devices are presented.
Design and Implementation of Low Power High Speed Symmetric Decoder Structure...Dr. Amarjeet Singh
The key objective of this project is to design a
decoder which can be used for hardware purposes.
Hardware, here accompanies with software which is more
we can discuss as a Software Defined Radio application. The
decoder implemented here offers to new radio equipment
(SDR), the flexibility of a programmable system. Nowadays,
the behavior of a communication system can be modified by
simply changing its software. Large tree decoder is made by
reusing smaller similar sub-modules. Thus the structure is
symmetric. The symmetric and regular structure of tree
decoder makes the system a less complexity one. The
structure obeys regularity and modularity concepts of VLSI
circuit, thus is easy to fabricate using cell library elements.
Design a Tree Decoder proposed architecture for SDR
application on FPGA. The Structures made here are
hardware synthesizable on FPGA board and are done in a
respective manner. The design to be implementing by using
Verilog-HDL language. The Simulation and Synthesis by
using Xilinx Vivado design suite.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This document describes the design of a DS-CDMA transmitter using VHDL and an FPGA. It discusses the design of the transmitter's key components like the PN code generator and BPSK modulator. The PN code generator uses a 16-stage linear feedback shift register with a specific feedback polynomial to generate codes. The transmitter blocks were designed separately in VHDL and then combined and implemented on an FPGA board. The transmitter is capable of transmitting data at rates up to 2 Mbps using a 40 MHz carrier frequency.
International Refereed Journal of Engineering and Science (IRJES) is a peer reviewed online journal for professionals and researchers in the field of computer science. The main aim is to resolve emerging and outstanding problems revealed by recent social and technological change. IJRES provides the platform for the researchers to present and evaluate their work from both theoretical and technical aspects and to share their views.
www.irjes.com
This document describes the design and implementation of a serial communication protocol conversion system and circular buffer in an FPGA for monitoring a Tesla meter. The system includes controllers for RS232 and RS485 serial communication, a protocol conversion unit between the two interfaces, and a circular buffer. The controllers are designed using Verilog HDL and implemented on a Spartan FPGA. Simulation and hardware results demonstrate that the system successfully converts between the RS232 and RS485 protocols in real-time and stores data in the circular buffer for offline analysis.
Implementation of Algorithms For Multi-Channel Digital Monitoring ReceiverIOSR Journals
Abstract: Monitoring Receivers form an important constituent of the Electronic support. In Monitoring
Receiver we can monitor, demodulate or scan the multiple channels.
In this project, the Implementation of algorithm for multi channel digital monitoring receiver. The
implementation will carry out the channelization by the way of Digital down Converters (DDCs) and Digital
Base band Demodulation. The Intermediate Frequency (IF) at 10.7 MHz will be digitalized using Analog to
Digital Converter (ADC) with sampling frequency 52.5 MHz and further converted to Base band using DDCs.
Virtually all the digital receivers perform channel access using a DDC. The Base band data will be streamed to
the appropriate demodulators. Matlab Simulink will be used to simulate the logic modules before the
implementation. This system will be prototyped on an FPGA based COTS (Commercial-off-the-shelf)
development board. Xilinx System Generator will be used for the implementation of the algorithms.
Keywords: DDC, ADC, Digital Base band demodulation, IF, Monitoring Receiver.
This document describes a final project to create a serial to Morse code converter. The project was completed by two students for a digital electronics course. Their system takes serial input from an AD2 board at 9,600 bits/sec, stores up to 100 characters in a buffer, and outputs the corresponding Morse code signals for each character using light and sound. The system is made up of several blocks including SCI receivers and transmitters, a character checker, buffer, Morse code translator, interpreter, and oscillator. Each block was designed and tested individually before integrating the full system. However, during testing the integrated system did not function correctly, possibly due to wiring issues.
Design of Adjustable Reconfigurable Wireless Single Core CORDIC based Rake Re...IOSR Journals
In wireless communication system transmitted signals are subjected to multiple reflections,
diffractions and attenuation caused by obstacles such as buildings and hills, etc. At the receiver end, multiple
copies of the transmitted signal are received that arrive at clearly distinguishable time instants and are faded by
signal cancellation. Rake receiver is a technique to combine these so called multi-paths [2] by utilizing multiple
correlation receivers allocated to those delay positions on which the significant energy arrives which achieves a
significant improvement in the SNR of the output signal. This paper shows how the rake, including dispreading
and descrambling could be replaced by a receiver that can be implemented on a CORDIC based hardware
architecture. The performance in conjunction with the computational requirements of the receiver is widely
adjustable which is significantly better than that of the conventional rake receiver
Design of Adjustable Reconfigurable Wireless Single Core CORDIC based Rake Re...IOSR Journals
Abstract : In wireless communication system transmitted signals are subjected to multiple reflections, diffractions and attenuation caused by obstacles such as buildings and hills, etc. At the receiver end, multiple copies of the transmitted signal are received that arrive at clearly distinguishable time instants and are faded by signal cancellation. Rake receiver is a technique to combine these so called multi-paths [2] by utilizing multiple correlation receivers allocated to those delay positions on which the significant energy arrives which achieves a significant improvement in the SNR of the output signal. This paper shows how the rake, including dispreading and descrambling could be replaced by a receiver that can be implemented on a CORDIC based hardware architecture. The performance in conjunction with the computational requirements of the receiver is widely adjustable which is significantly better than that of the conventional rake receiver. Keywords - Rake receiver, Multi-paths, CORDIC
Generation and Implementation of Barker and Nested Binary codesIOSR Journals
This document discusses the generation and implementation of Barker and nested binary codes for use in radar applications. It begins with background on Barker codes and nested binary codes, which are types of phase coded waveforms used for pulse compression. Barker codes have the optimal autocorrelation sidelobe properties but are limited in length. Nested binary codes are formed by taking the Kronecker product of two Barker codes, which allows the generation of longer codes while maintaining good autocorrelation. The document then presents the methodology for implementing Barker and nested binary codes using linear feedback shift registers (LFSRs). Finally, it discusses measures for comparing signal performance such as merit factor and proposes an efficient VLSI architecture using LFSRs to generate these codes for implementation
A NOVEL APPROACH FOR LOWER POWER DESIGN IN TURBO CODING SYSTEMVLSICS Design
Low Power is an extremely important issue for future mobile communication systems; The focus of this paper is to implementat turbo codes for low power solutions. The effect on performance due to variation in parameters like frame length, number of iterations, type of encoding scheme and type of the interleave in the presence of additive white Gaussian noise is studied with the floating point model. In order to obtain the effect of quantization and word length variation, a fixed point model of the application is also developed.. The application performance measure, namely bit-error rate (BER) is used as a design constraint while optimizing for power and area coverage. Low power Optimization is Performed on Implementation levels by the use of Voltage scaling. With those Techniques we can reduced the power 98.5%and Area(LUT) is 57% and speed grade is Increased .This type of Power maneger is proposed and implemented based on the timing details of the turbo decoder in the VHDL model.
Ijeee 33-36-surveillance system for coal mines based on wireless sensor networkKumar Goud
Abstract: The foremost critical task for coal mine is of keeping track of miners spread out across a large mining areas .It becomes even difficult when mine tunnels collapse. Many mines use a radio system to track miners, but when a collapse occurs, the base stations connected by a thin wire often are rendered useless. In this project to overcome the demerits of radio system we used wireless technology for tracking the miners. For this purpose a small RF transmitter module is equipped to each person entering a mine. Each transceiver placed in the mine look after the location of miners. The transceivers communicate with base stations through Zigbee module. In addition of tracking the location of miners we also include sensors such as temperature & humidity to intimate the base station & miners when some atmosphere changes occur. Mine operators are now able to monitor the real-time locations of each miner to better pinpoint their locations in the event of an emergency. Even after a full-day of use, mine operators can locate an individual miner within ten feet.
Key Words: Wireless sensor networks (WSN), ZIGBEE, and LPC2148.
Implementation of XOR Based Pad Generation Mutual Authentication Protocol for...IOSR Journals
This document describes the implementation of an XOR-based pad generation mutual authentication protocol for RF links. It begins with an introduction to the need for security in RF data transmission and describes existing protocols. It then presents the design of a new XOR pad generation function to securely transmit access passwords for authentication. Random numbers generated by a linear feedback shift register are input to the pad generation function along with passwords to produce encoded pads. The protocol is implemented on an FPGA for hardware verification. Simulation results demonstrate the protocol generating pads for authentication.
Implementation of XOR Based Pad Generation Mutual Authentication Protocol for...IOSR Journals
In RF link, without security the messages exchange between the two devices are monitoring by an
eavesdropper. So the exclusive-OR (XOR) based pad generation protocol is used to safely transfer the data to
the other point with necessary security and it maintaining confidentiality. This protocol produce the cover
coding pad to mask the access password before the datas are transmitted. A specially designed pad generation
will be implemented in digital domain to solve the insecurity problem in data communication RF link. This
protocol developed under regulation of ISO 18000 – 6 type C protocol also known as EPC C1G2 RFID
protocol. The linear feed back shift register (LFSR) generate the pseudo random binary sequence (PRBS) and it
is used as data source to the pad generation function. The Xilinx 13.x software is used for synthesize and
modelsim SE6.0 is used for simulating the result. The pad generation algorithm has been implemented in FPGA
Spartan 3 PQ208-4 board to verify the result
Software Design of Digital Receiver using FPGAIRJET Journal
This document describes the design and implementation of a digital receiver using an FPGA. It involves sampling an analog signal from a radar target using an ADC at a high sampling rate. This sampled signal is then sent to a digital down converter (DDC) which performs frequency translation and decimation. The DDC is implemented using IP cores on an FPGA. It translates the sampled signal to a lower frequency and outputs I and Q signals at a lower sampling rate. This provides a digital signal with higher precision and stability for extracting information from radar targets.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This document provides an overview of simulation of a turbo encoder and decoder. It discusses the key components of a turbo encoder including two convolutional encoders separated by an interleaver. It describes convolutional encoding, interleaving, puncturing, and different decoding techniques like SOVA and MAP decoding. It lists applications of turbo codes in areas like mobile radio, digital video, and deep space communications. Finally, it concludes that turbo codes can achieve remarkable performance with low complexity encoding and decoding algorithms, making them well-suited for applications like deep space communications.
Design and Implement Any Digital Filters in Less than 60 SecondsMike Ellis
The document describes ElecFilDes, a digital filter design software program. ElecFilDes can design both infinite impulse response (IIR) and finite impulse response (FIR) filters and generate coefficient files to implement the filters on a Motorola MC56F84789VLL digital signal controller evaluation board. The board includes an A/D converter, DAC, and DSP to run filter code generated by ElecFilDes. ElecFilDes can design many filter types and generate code to implement the filters on the board in under 60 seconds.
Design of a Digital Baseband Processor for UWB Transceiver on RFID Tagtheijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
call for paper 2012, hard copy of journal, research paper publishing, where to publish research paper,
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals
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VoCoRoBo: Remote Speech Recognition and Tilt Sensing Multi-Robotic System
1. VoCoRoBo: Remote Speech Recognition and Tilt
Sensing Multi-Robotic System
Sagun Man Singh Shrestha1
, Labu Manandhar2
, Ritesh Bhattarai3
Department of Electronics and Computer Engineering,
Tribhuvan University – Kathmandu Engineering College, Nepal
Gmail: 1
sagunms, 2
laburocks, 2
reittes | github.com/sagunms/vocorobo
Abstract: This work is based on the implementation of real-time speech recognition using DSP
algorithms such as Chebyshev IIR filters, accelerometer for tilt-sensing and establishment of short-
range wireless secure link with ARC4 cipher, all using low-cost 8-bit ATmega microcontrollers.
The robot implements a simple but effective algorithm for comparing the spoken word with a
dictionary of fingerprints using a modified Euclidean distance calculation. It also includes the ability
to securely control the navigation of multiple robots located at remote locations wirelessly from the
Control Module and also gather the various environmental data collected by the Robot Modules and
display them in the back to Control. Considering the time-critical algorithms actually requiring large
computations as well as a variety of sensors interfaced in the system, this project can demonstrate
how one can build an expansible multi-robotic system from cheap and ubiquitous electronics.
Keywords: Speech Recognition, Chebyshev, Digital Signal Processing, Euclidean Distance, ARC4
Cryptography, ATMega16/32, nRF24L01+ Wireless Transceiver, MMA7260Q Accelerometer
I. INTRODUCTION
VoCoRoBo stands for Voice Controlled RoBot in
which the user is capable of wirelessly controlling
multiple robots with either a voice command or
tilting the controls towards the desired direction. In
addition to this, each robot also relays temperature
and light sensor data securely back to the user station.
1.1 HARDWARE
A microcontroller is an integrated circuit composed
of a microprocessor unit, memory, and input/output
peripheral devices. Atmel ATmega32/16 is a low-
power CMOS 8-bit microcontroller based on the
AVR RISC architecture which is used to implement
the voice recognition, tilt-sensing, wireless and
cryptography algorithms. An accelerometer measures
proper magnitude and direction of acceleration
experienced relative to freefall, and can be used to
sense orientation. Controlling the robots with fun and
intuitive tilt gestures was possible using the Freescale
MMA7260Q 3-axis accelerometer. The two parts of
the system – control and robot modules are linked
wirelessly using the popular Nordic nRF24L0+ radio
transceiver. It operates on 2.4 - 2.5 GHz ISM band,
with air data rate up to 2Mbps, has ultra low power
operation and is ideally suited for remote control and
data acquisition. L293D H-bridge IC is a quad push-
pull driver capable of delivering output currents up to
600mA per channel. To control each robot turning
speeds simply by speed difference between wheels on
either side, differential drive technique was used.
1.2 SOFTWARE
Speech recognition is the process of converting an
acoustic signal captured by microphone and then
identifying the word from the sound. Due to speaker
dependence, the system needs to be trained before
use. Digital signal processing is concerned with the
representation of signals by a sequence of numbers
and their processing. Infinite impulse response is a
property of signal processing systems having impulse
response function that is non-zero over infinite length
of time. An example of IIR filter are Chebyshev II
filters having a steeper roll-off and more stop band
ripple than Butterworth filters. They minimize the
error between the idealized and the actual filter
characteristic over the range of the filter.
2. 1.2.1 Speech Analysis
In speech recognition, the frequency content of the
detected word has to be analyzed. Several 4th
order
Chebyshev band pass filters are created by cascading
two 2nd
order filters using the following Direct Form
II Transposed realization of difference equations.
( ) ( ) ( )
( ) ( )
( ) ( ) ( )
( ) ( )
( ) ( )
Coefficients a’s and b’s used in the above equations
was obtained using the following syntax in Matlab.
[B,A] = cheby2(2,40,[Freq1, Freq2]);
cheby2 designs Chebyshev Type II digital filter using
the given specifications, 2 defines a 4th
order filter, 40
defines the stop band ripple in dB, and Freq1 and
Freq2 are the normalized cutoff frequencies. The
tf2sos function is then used to convert the transfer
function of the filter to a 2nd
order section version.
1.2.2 Voice-fingerprint Calculation
Due to the limited RAM on the ATMega32, the
relevant information of each spoken word had to be
encoded in the form of a ‘fingerprint’. To compare
fingerprints, the following pseudo Euclidean distance
formula was used between the fingerprint of stored
and sampled word to find correct word.
∑| |
where, P = (p1, p2, ..., pn) is the dictionary fingerprint
and, Q = (q1, q2, ..., qn) is sampled word fingerprint.
pi and qi are the fingerprint data points. To see if two
words are the same, the distance between them are
computed and the words with the minimum distance
in the database are considered to be the matching
word. Original Euclidean distance requires squaring
the difference between two points. Fixed point
arithmetic produces too large a number, causing the
variables to overflow. Thus a modified formula was
used by neglecting the square root and the square
which practically showed satisfactory results.
1.2.3 ARC4 Cryptography
ARC4 is one of the most widely used software stream
ciphers in many encryption schemes, including WEP,
WPA, and SSL. The main factors in ARC4's success
over such a wide range of applications are its speed,
simplicity and efficiency in software and hardware.
3. DESIGN AND IMPLEMENTATION
3.1 HARDWARE ARCHITECTURE
Figure 3.1: Overall Hardware Architecture
2.4 GHz
wireless link
with 2 bytes
(control byte
+ count byte)
payload
ATmega16 @ 8 MHz
(nRF24L01+ wireless
interface with ARC4
Cryptography)
ATmega32 @ 16 MHz
(Speech Recognition and
MMA7260Q Tilt
Sensing)
Port C
PB0-PB3
ADC
(Port A)
PD3-PD5
x y
z
Port C
SPI
(Port B)
PA0-PA2
nRF24L01
Module
LCD LEDs
Port C
SPI
(Port B)
PD0-PD3
LEDs
L293D
H-Bridge
M
M
nRF24L01
Module
ATmega16 @ 8 MHz
(nRF24L01+ with
ARC4 and H-Bridge
interface)
3. The system is divided into two broad sub-
subsystems: Control Module and Multi-Robot
Module. The Control Module is further divided into
two layers: the topmost layer and the second layer.
3.1.1 Control Module
The topmost layer of the control module consists of
ATMega32, where speech recognition, MMA7260Q
accelerometer sensing, output to 16x2 text LCD are
handled. The 2nd
layer consists of ATMega16 where
the nRF24L01 wireless routine as well as encryption
and decryption with ARC4 cipher are implemented.
The bridge protocol between the 1st
and 2nd
layers in
the control module (Fig. 3.1 and 3.2) is designed such
the three output pins of PORTD of ATMega32 viz.
PD2, PD3 and PD4 are connected to the respective
input pins of PORTA of ATMega16 viz. PA0, PA1
and PA3. When the 1st
layer recognizes the spoken
word (front, back, left, right or stop), the equivalent
bit combination is inputted to PORTA of the 2nd
layer
via these bridge lines. The 2nd
layer then sends out
the corresponding control byte wirelessly via SPI
port. When the one of the robot receives this control
byte, it will be decoded into its matching differential
drive motor combinations that will move the robot
physically in the commanded direction.
FUNCTION
Equivalent
received
control byte
PIN A
(Connected to Layer 1)
BINARY HEX
PA2 PA1 PA0
STOP S 0 0 0 00H
FRONT F 0 0 1 01H
BACK B 0 1 0 02H
LEFT L 0 1 1 03H
RIGHT R 1 0 0 04H
SPD_UP U 1 0 1 06H
SPD_DN D 1 1 1 07H
Table 3.1: Function control byte to be sent out via Wireless
(SPI port) and corresponding bit combination inputted to
the second layer of Control Module (PINA).
3.1.2 Robot Module
It consists of two identical robots (A and B) which
can be positioned at different locations, provided they
are within the signal range of the Control Module.
Each robot consists of an ATMega16 with sensors
that take environmental data specifically, LM35
temperature sensor and a light dependent resistor. A
2.4 GHz wireless transceiver nRF24L01 is also
available on-board to receive control data and
transmit the remote data for data acquisition. With
L293D H-Bridge driver, two differential drive motors
are controlled independently so that the robot can
navigate front, back, left or right. Four input pins of
the L293D viz. IN1, IN2, IN3 and IN4 are connected
to four output pins of PORTD of ATMega16 viz.
PD0, PD1, PD2 and PD3 respectively.
FUNCTION
Equivalent
received
control byte
PORT D
(Connected to H-
bridge)
BINARY HEX
(LSB)
IN4 IN3 IN2 IN1
STOP S 0 0 0 0 00H
FRONT F 0 1 1 0 06H
BACK B 1 0 0 1 09H
LEFT L 0 0 1 1 03H
RIGHT R 1 1 0 0 04H
SPD_UP U
SPD_DN D
Table 3.2: Function control byte received via Wireless
(SPI port) and corresponding bit combinations outputted to
H-bridge (PORTD).
3.2 SOFTWARE ARCHITECTURE
3.2.1 Input, Processing, Output
Figure 3.2: Input, Processing and Output block diagram for
speech recognition
At a rate of 4 KHz, the algorithm checks the ADC
input for audio signal. If the ADC value exceeds the
threshold value, it is taken as the start of half a
second long word. The sampled word passes through
Speech ADC Band Pass
Filters
Generate Voice
Fingerprints
Fingerprint
Templates
Control
Signals
Output to
the Robot
COMPA
RE
4. 8 band pass filters to be encoded into a fingerprint.
The words to be matched are stored as fingerprints in
a dictionary so that newly generated sampled
fingerprints can be compared with them later. The
modified Euclidean distance calculation finds the
fingerprint that is the closest match and then sends a
control signal ultimately to the robot to perform
operations like left, right, front, back and stop.
3.2.2 Initial-Threshold Calculation
All the background sound at the startup is considered
to be a base value which improves the accuracy of
the speech recognition. At the start up, the algorithm
reads the ADC input using ATMega32 timercounter0
and accumulates its value 256 times. By interpreting
the reading of the ADC value as a number between 1
to 1/256 in fixed point, and accumulating 256 times,
the average ADC value is calculated without doing a
multiply or divide. Three average values are taken
each with a 16.4 ms delay between the samples. After
this, the threshold value is to be four times the value
of the median number. The threshold value is useful
to detect whether a word has been spoken or not.
3.2.3 Voice-fingerprint Generation
Figure 3.3: Filter implementation block diagram for the
generation of fingerprints
The program considers a word detected if a sample
value from the ADC is greater than the threshold
value. Every sample of ADC stored in an integer
variable Ain which again passes through eight 4th
order band pass filters for 2000 samples (half a
second) once a word has been detected. When a filter
is used its output is squared and that value is
accumulated with the previous squares of the filter
output. After 125 samples the accumulated value is
stored as a data point in the fingerprint of that word.
The accumulator is then cleared and the process is
begun again. After 2000 samples 16 points have
been generated from each filter, thus every sampled
word is divided up into 16 parts. Our assembly
language code is based around using 8 filters and
since each one gives an output of 16 data points and
every fingerprint is made up of 128 data points.
3.2.4 Filter Design and Implementation
Figure 3.4: Band pass Filter 200-400 Hz
Figure 3.5: Band pass Filter 1600-1800 Hz
3.2.5 Digital Filter Implementation
The 4th
order Chebyshev digital filter with 40 dB stop
band was chosen due to very sharp transitions after
the cutoff frequency. Most of the important
frequency content in speech is found to be within the
first 2 KHz as it usually contains the first and second
speech formants. Thus 8 BPFs of frequencies ranging
from .2 to 1.8 KHz were designed as shown in the
magnitude and phase plot. This also permitted the
sampling at 4 KHz (to satisfy the Nyquist criteria for
sampling first 2 KHz voice frequencies) and enough
time to implement 8 filters. For sufficient frequency
resolution to properly identify words, bandwidth of
each filter is set to 200 Hz.
Each 4th
order filter is created in assembly code by
cascading two 2nd
order IIR filters whose coefficients
ADC FILTER 2
FILTER 9
ACCUMULATOR
ACCUMULATOR
VOICE
FINGERPRINT
5. are generated using Matlab (Listing 1.2.1). Floating
point coefficients are converted to fixed point by
multiplying them by 256 and rounding off to nearest
integer in real-time. Fixed point was used instead of
floating point (which would have been more
accurate) as floating point calculations of ATMega32
is too slow to call all the filters within 4 KHz.
The ATMega32 only has 2 KB of RAM and a word
sampled at 4 KHz for a half a second would require
entire 2 KB. In order to make a fingerprint then from
a word the ADC output has to pass through all the
filters faster than the ADC sample time of 250 µs.
The output of the filter was squared in order to store
the intensity of the sound rather than just the
amplitude. Since the lowest and highest frequencies
could be neglected without noticeable degradation in
accuracy of speech recognition and that the memory
and cycle time of ATMega32 wouldn’t be sufficient
to implement all ten filters, only 8 BPFs was
sufficient to compartmentalize frequencies between
200 Hz - 1.8 KHz.
3.2.7.1 Chebyshev II filter coefficients
# Filter 1 Filter 2 Filter 3 Filter 4
f,KHz
0.2 – 0.4 0.4 – 0.6 0.6 – 0.8 0.8 – 1
1st
2nd
-order
coeff.
A112:451
A113:-248
B111:21
B112:-32
B113:21
A212:355
A213:-248
B211:27
B212:-29
B213:27
A312:224
A313:-248
B311:31
B312:-15
B313:31
A412:72
A413:-248
B411:34
B412:4
B413:34
2nd
2nd
-order
coeff.
A122:458
A123:-248
B121:2225
B122:-4285
B123:2225
A222:366
A223:-248
B221:1090
B222:-1826
B223:1090
A322:239
A323:-248
B321:762
B322:-965
B323:762
A422:88
A423:-248
B421:633
B422:-464
B423:633
Gain
G1=80 G2=120 G3=140 G4=160
Table 3.3: MATLAB filter coefficients for Chebyshev II
(40 dB stop band) Filters 1-4
# Filter 5 Filter 6 Filter 7 Filter 8
f,KHz
1 – 1.2 1.2 – 1.4 1.4 – 1.6 1.6 – 1.8
1st
2nd
-order
coeff.
A512:-72
A513:-248
B511:34
B512:-4
B513:34
A622:-239
A623:-248
B621:762
B622:965
B623:762
A712:-355
A713:-248
B711:27
B712:29
B713:27
A812:-451
A813:-248
B811:21
B812:32
B813:21
2nd
2nd
-order
coeff.
A522:-88
A523:-248
B521:633
B522:464
B523:633
A622:458
A723:-248
B721:2225
B722:-4285
B723:2225
A722:-366
A723:-248
B721:1090
B722:1826
B723:1090
A822:-458
A823:-248
B821:2225
B822:4285
B823:2225
Gain
G5=160 G6=140 G7=120 G8=80
Table 3.4: MATLAB filter coefficients for Chebyshev II
(40 dB stop band) Filters 5-8
3.2.6 Wireless Packet Format
The preamble byte composed of alternating zeros and
ones is sent first, followed by five bytes address field.
Data payload of user settable length (1-32 bytes) is
sent next. Two versions of payload was implemented
i.e. 2 bytes payload was primarily used having only
the encrypted byte and a count byte, however for data
acquisition from temperature and light sensors from a
remote location, an 18 byte payload version was
designed. The final part is the two byte long CRC.
3.2.7.2 Wireless Data Payload format
The data payload for control module is of two types:
transmitter mode and receiver mode payload, both
having 18 bytes payload width. Control module has
to transmit data packets to individual robots and also
receive sensor data from replying robots. So it has to
hold the entire payload of the each robot (two in our
case) for both transmission and reception. Two 18
bytes char arrays data_tx1 and data_tx2 stores the
transmission mode payload while the other two
arrays data_rx1 and data_rx2 are for the receiver.
Both the payload sizes are of PAYLOAD_SIZE (18
bytes) defined in the wireless routine of ATmega16.
6. Figure 3.6: Transmitter Mode Payload
Out of three blocks, the first 16 bytes block holds the
data text to be sent from the control to the robot
modules. For inputting the text data, we use
RealTerm to send the text from the computer to the
MCU via UART for sending text messages to the
individual robots at different locations. The control
block is formed by the 1 byte data_control which
stores the ASCII characters: ‘F’, ‘B’, ‘L’, ‘R’ and ‘S’,
representing the control information for front, back,
left, right and stop. When the targeted robot receives
the control information in transmitter payload, it will
interpret the ASCII control byte as the corresponding
robot movement commands.
The ARC4 cipher is used to encrypt the control byte
and data text block. Being a stream cipher, the byte
count must be kept up to date (missing a packet will
result in an incorrect decryption from that point on),
so a packet count byte is added with each packet that
keeps a packet count. This allows the local unit to
catch up to the correct byte in the PRGA (assuming
targeted robot misses less than 256 packets in a row).
Figure 3.7: Receiver Mode Payload
Receiver mode payload is needed to receive the
encrypted data payload sent by the individual robots,
decrypt the encrypted block by syncing with the help
of packet count, segregate the sensor readings of
temperature (2 bytes), light (2 bytes) and speed
setting (1 byte) and store it in their respective
variables for data logging. For data acquisition, the
payload is divided into temperature and light blocks.
The readings from the two sensors in each robot are
stored in their respective integer variables and sent to
the control module in packet format.
3.2.7.3 Source and destination data pipe addressing
Using switches connected to PD4 and PD5 of
ATMega16, the user can select whether the control
byte generated by roboControl function is directed to
control bytes data_control1 or data_control2 which
are concatenated to respective data packets for each
robot. The user would thus be able to select to which
robot the current command would be directed to. This
technique would enable the realization of multi-robot
control paradigm from a single control module.
For implementing a minimalistic Star network
topology, the receiving pipes of control module,
Robot1 and Robot2 are 0, 1 and 2 respectively and
the corresponding pipe addresses are E7:E7:E7:E7:E7,
C2:C2:C2:C2:C2, C2:C2:C2:C2:C3. The rest of the five
data pipes in each of the three linking modules are
disabled to effectively block reception of packets
destination was elsewhere. Prior to transmitting a
data packet, the destination address should be set.
Figure 3.8: Minimalistic Star Network Topology for
establishing communication link between Control and
Robot Agent modules and their respective destination
multi-pipe addressing
3.2.7 ARC4 Cryptography
ARC4 generates a pseudorandom stream of bits
(keystream) which, for encryption, is combined with
the plaintext using bit-wise xor; decryption is
performed in the same way (since xor is a symmetric
operation). To generate the keystream, the cipher
Data text (data_text1, data_text2)
(16 bytes)
17 16 15----------------------------------------------- 0
Packet
count
(1 byte)
Control
(1 byte)
data_control
Encrypted Block
T T T T T T T T T T T T T T T
T
PAYLOAD_SIZE (18 Bytes)
data_tx1
data_tx2
Padding bits
(12 bytes)
Light
(2 bytes)
P P P P P P P P P P
P P
L L T T
17 16 15 ------------------------ 4 3 2 1 0
Speed
(1 byte)
Packet
count
(1 byte)
Temp
(2 bytes)
PAYLOAD_SIZE (18 Bytes)
Encrypted Block
E7:E7:E7:E7:E7
Pipe 0
Robotic
Agent I
Pipe 2Pipe 0
C2:C2:C2:C2:C2
Pipe 1
C2:C2:C2:C2:C3
Pipe 2
Pipe 1 Pipe 0
P5 P4 P3 P2 P1
P0
P5 P4 P3 P2 P1
P0
P5 P4 P3 P2 P1
P0 TX
TX
Robotic
Agent II
TX
Control Module
Communication
Link (Pipe
Destination)
7. makes use of a secret internal state which consists of
two parts:
A permutation of all 256 possible bytes (denoted
"S" below).
Two 8-bit index-pointers (denoted "i" and "j").
The permutation is initialized with a variable length
key, typically between 40 and 256 bits, using the key-
scheduling algorithm (KSA). After this, the stream of
bits is generated using the pseudo-random generation
algorithm (PRGA). The ARC4 cipher is implemented
in conjugation with the wireless routine of
ATMega16 of both control and robot modules.
3.2.8 MMA7260Q Tilt Sensing
Figure 3.9: Overall accelerometer tilt sensing algorithm
MMA7260Q has three sensor output pins viz. X, Y
and Z connected to three of the ADC inputs viz. PA3,
PA4 and PA5 of ATMega32. The robot functions
(front, back, left and right) are controlled in either
Speech or Accelerometer mode. In the latter, the tilt-
sensing algorithm samples the X, Y, Z values for
origin first into xyzOrigin, and rapidly stores the
remaining into xyzADCArray. These arrays are used
by the three decision blocks to determine the speeds
in the individual directions. In the speed and decision
block, once the speed either in positive or negative
direction (depending on accelerometer orientation) is
determined, decide whether the function to be
interpreted is a front, back, left, right or stop. For this,
the calculated speed in either X or Y has to exceed a
predefined threshold, to consider the movement data
valid. The decision of the command interpreted by
the algorithm is sent to the roboControl function
which conveys it ultimately to one of the robots.
Figure 3.10: Flowchart showing xSpeed determination and
decision making of robot functions (FRONT and BACK)
Yes
Samples X, Y, Z values for
Origin into xyzOrigin array
No
STAR
T
Initialize:
*Origin & Speed variables for x, y, z
XOrizin = yOrigin = zOrigin = 0
XSpeed = ySpeed = zSpeed = 0
*Configure ADC pin = 3 to 5
*Initialize LCD
Determine xSpeed, ySpeed and
zSpeed (REFERENCE AXIS)
Decision of robot function
Send appropriate control signal
ADC
conversi
on
Store the remaining values
into xyzADCArray
No
Yes
Yes
No
Yes
Yes
No
Yes
Decision
= FRONT
Decisio
n =
STOP
Decision
= LT/RT
Is
xADCArr
ay>
xSpeed = xADCArray -
xOrigin
(+ve speed value)
From
xOrigin
From
xADCArray
xSpeed = xOrigin -
xADCArray
(-ve speed value)
Is xSpeed
>
threshold
Decision
= BACK
AXIS=
1?
Decisio
n =
Is xSpeed
>
threshold
AXIS=
1?
Send decision to roboControl function
8. 4. RESULTS
4.1 Time domain waveform
The figure depicts different time domain waveforms
of the spoken word generated by Matlab. The time
duration of the spoken words front, left and right are
approximately of 4s duration. The word back is of
lowest duration of 2s due to which it is recognized
with least accuracy relative to other five words while
stop is of highest duration of 5s accuracy is highest.
Figure 4.1: Time domain representation of Back
Figure 4.2: Time domain representation of Stop
4.2 Frequency domain waveform
These figures depict the spectral analysis (discreate
fourier transform) of the sampled time domain data
generated using Matlab.
Figure 4.3: FFT of the word Back
Figure 4.4: FFT of the word Stop
4.3 Dictionary data points for voice fingerprints
Table 4.1: Dictionary data points for the word FRONT
stored in the flash memory
128 data points for each of the five words are logged
via RealTerm in similar manner during the training
stage and stored as dictionary in the flash memory.
4.4 Speech Recognition
Figure 4.5: Recognition Probability Comparison
85%
90%
95%
100%
Front Back Left Right Stop
95%
90%
95% 95%
100%
Recognition Probability
Number of Testing=20
Filter
1
Filter
2
Filter
3
Filter
4
Filter
5
Filter
6
Filter
7
Filter
8
731
831
723
2343
4838
2514
7815
1085
681
1025
707
1057
625
309
172
672
177
346
307
364
95
59
10
0
0
0
0
35
4
0
0
0
3120
3704
4341
1001
1957
5105
288
51
156
31
0
732
175
4
0
44
474
1188
1966
539
167
184
78
0
30
52
30
193
0
0
0
0
7662
4377
3991
2200
1639
347
561
134
0
23
20
1309
874
0
0
0
1564
789
4137
1752
1311
1629
52
5
34
68
123
728
343
120
77
76
385
183
306
171
553
163
3
56
72
123
68
219
196
42
41
37
704
764
796
950
2347
1998
489
665
266
379
137
138
729
944
1400
516
9. The accuracy of the speech recognition was within an
acceptable range of above 90% by our initial
expectations of the system design. However,
considering the basic speech algorithm, recognition is
valid only for the same person who underwent the
preliminary voice training to initialize the dictionary
fingerprints. For convenience, the recorded voice of
Oxford dictionary software stored as a .wav file was
played in a relatively quiet surroundings.
4.5 Euclidean Distance Comparison
Figure 4.6: Euclidean Distance Comparison
UART logging from RealTerm was done and the
Euclidean distance comparison was logged with all
five different fingerprints already stored in the
EEPROM. As expected, the word was recognized as
the one with the least distance when comparing with
the five fingerprints.
4.6 Wireless Transmit and Receive
4.6.1 Correct ARC4 Key Encryption/Decryption
The logged data data from the RealTerm is presented
below. It depicts correct ARC4 key encryption and
decryption. If the private key is matched in both the
control and robot modules as shown below, then the
encrypted data is decrypted back to the original data
as the PRGA of robot agent updates 12 times to catch
up with the PRGA of Control module.
CONTROL Initialized!
== Control Module ==
Private Key = SaGuN
- TX to Robot I -
Destination:
C2:C2:C2:C2:C2(Pipe1)
Original:
data_tx1[0]= S
data_tx1[1]=0
ROBOT Initialized!
== Robot Module I==
Private Key = SaGuN
-RX from Control-
Packet received!
Encrypted
data[0]= ‘
data[1]=0
No. of PRGA updates =
Encrypted:
data_tx1[0]= ‘
data_tx1[1]=0
Packet sent!
Current Sequence = 1
- TX to Robot I -
Destination:
C2:C2:C2:C2:C2(Pipe1)
Original:
data_tx1[0]= S
data_tx1[1]=1
Encrypted:
data_tx1[0]= ,
data_tx1[1]=1
Packet sent!
Current Sequence = 2
12 times
Decrypted
data[0]= S
data[1]=0
Current Sequence = 1
-RX from Control-
Packet received!
Encrypted
data[0]= ,
data[1]=1
Decrypted
data[0]= S
data[1]=1
Current Sequence = 2
4.6.2 Incorrect ARC4 Key Encryption/Decryption
If the private key is not matched between the two
modules then the encrypted data cannot be decrypted
back to its original data as shown below.
CONTROL Initialized!
= Control Module =
Private Key= VoCoRoBo
- TX to Robot II -
Destination:
C2:C2:C2:C2:C3(Pipe2)
Original
data_tx1[0]= S
data_tx1[1]=0
Encrypted
data_tx1[0]= j
data_tx1[1]=0
Packet sent!
Current Sequence = 1
- TX to Robot II -
Destination:
C2:C2:C2:C2:C3(Pipe2)
Original
data_tx1[0]= S
data_tx1[1]=1
Encrypted
data_tx1[0]= D
data_tx1[1]=1
Packet sent!
Current Sequence = 2
ROBOT Initialized!
=Robot Module II=
Private Key = SaGuN
- RX from Control-
Packet received!
Encrypted
data[0]= j
data[1]=0
No. of PRGA updates =
7 times
Decrypted
data[0]= ƒ
data[1]=0
Current Sequence = 1
- RX from Control-
Packet received!
Encrypted
data[0]= D
data[1]=1
Decrypted
data[0]= ~
data[1]=1
Current Sequence = 2
5. CONCLUSION
This project is based on the implementation of real-
time speech recognition using DSP algorithms such
as Chebyshev IIR filters, accelerometer for tilt-
sensing and establishment of short-range wireless
10. secure link with ARC4 cipher, all using ubiquitous
low-cost 8-bit microcontrollers. With an accuracy of
the speech recognition above 90%, it shows the
feasibility of the system to be applied in any low cost
applications in real time. It was observed that the
words with greater pronunciation stress were
recognized better. Although for now, the recognition
is accurate only for the same person who trained the
system, it can be expanded to make the system
speaker independent by further research on the
storing and retrieval of the voice fingerprint from a
different media. Multi-channel wireless link with
ARC4 was also successfully implemented to
exchange control and sensor data. As nRF24L01 is
capable of higher speed data transmission, the system
can also be expanded to incorporate other sensors
like audio or video sensors for richer data acquisition
.
6. REFERENCES
[1] T. Aamodt. (2003, April) “Speech Recognition
Algorithm”, University of British Columbia.
http://www.eecg.toronto.edu/%7Eaamodt/ece34
1/speech-recognition
[2] X. Lu, S. Lee, 2006. “Voice Recognition
Security System”, Cornell University
[3] A. Harison, C. Shah, 2006 "Voice Recognition
Car", Cornell University.
[4] B. R. Land; Cornell University; Fixed Point
mathematical function in GCC and assembler;
Optimized 2nd order IIR code.
[5] B. R. Land (2008, September). Fast Digital
Filtering. Circuit Cellar Issue # 218, p. 40.
[6] Application Note AVR201: “Using the AVR®
Hardware Multiplier”, Atmel Corporation.
[7] IIR Design: nauticom.net/www/jdtaft/iir.htm
[8] Brennen Ball; 2007; “Specializing in the NXP
LPC2148 and Microchip PIC18F452
microcontrollers and the Nordic Semiconductor
nRF24L01 2.4 GHz RF link”; diyembedded.com
[9] “Interfacing nRF2401 with SPI” (White Paper),
Nordic Semiconductor.
[10] T. Igoe, “MMA7260Q 3-Axis Accelerometer
Report for PIC 18F252 using PicBasic Pro”,
Sensor Workshop at ITP (January 16, 2006).
[11] Application Note AN3447: “Implementing Auto-
zero calibration technique for accelerometers”,
Freescale Semiconductors.
7. PICTURES
Figure 7.1: Overall System
Figure 7.2: Schematic Diagram of Control Module
Figure 7.3: Schematic Diagram of a single Robot Module