The document discusses JFETs (junction field-effect transistors). It describes that JFETs are voltage-controlled devices unlike BJTs which are current-controlled. It explains the construction and working of an n-channel JFET, including its four terminals (drain, source, gate, and substrate) and how applying a voltage between the gate and source controls the flow of current from drain to source. The key characteristics of a JFET like its drain/I-V characteristics and transfer characteristics are also summarized. Different biasing configurations for JFETs like fixed bias, self-bias, and voltage divider bias are outlined.

1. JFET

2. Current Controlled vs Voltage Controlled Devices

3. Current Controlled vs Voltage
Controlled Devices
• BJT is current controlled device.
• FET is voltage controlled device.
Ic = f(Ib)
Id = f(vgs)

4. FET - Introduction
• BJT is Bipolar device, FET is unipolar device.
• FET conduction depends either on electrons or holes.
• Types:
n-channel JFET
P-channel JFET
In n-channel JFET conductivity depends on electrons.
In p-channel JFET conductivity depends on holes.

5. • Application of FET is approximately the same as BJT.
• FET can be used as amplifiers and switches.
• Electric field controls the conduction path of output hence it is called
as field effect transistor
• FETs have high input impedance than BJT
• FETs are more temperature stable
• FETs are smaller than BJT

7. Construction and Working of JFET

8. Construction and Working of JFET
• The above figure represents the n-channel JFET.
• The major part of the material is made up of n-type materials.
• It is forming channels between two embedded p-type materials,
hence it is called n-channel JFET.
• There are totally 4- Ohmic contact.
• The Ohmic contact is a low resistance junction (non-rectifying)
provides current conduction from metal to semiconductor and vice
versa

9. Construction and Working of JFET
• The first ohmic contact is the drain (D) terminal.
• The second ohmic contact is the source(S) terminal.
• The third and fourth ohmic contact are connected together and one
common terminal is taken out and that terminal is called as Gate(G).
• There are 2 p-n junctions and hence 2 depletion regions are formed.
• Depletion region will not have any free charge carriers.
• On varying the width of the depletion regions the flow of electrons
from source(S) to drain(D) can be controlled.

11. Construction and Working of JFET
• The voltage across gate to the source controls the flow of current
from the drain to the source and hence it is called as voltage-
controlled device.

12. Construction and Working of JFET
• Vgs = 0V, Vds >0

13. Construction and Working of JFET
• The width of the depletion region will be increased at the top and
remains almost the same at the bottom because the n channel is
reverse-biased at the top and forward-biased at the bottom.
• Increasing the reverse bias voltage will increase the width of the
depletion region.

14. Symbol of JFET

15. Pinch-off Voltage

16. Characteristics of FET

17. CHARACTERISTICS OF N-CHANNEL
JFET :-
• There are two important characteristics of a JFET.
1.Drain or VI Characteristics
2.Transfer characteristics

18. Drain Characteristics:-
• Drain characteristics shows the relation between the drain to
source voltage Vds and drain current Id. In order to explain
typical drain characteristics let us consider the curve with Vgs=
0.V.
1.When Vds is applied and it is increasing the drain current ID
also increases linearly up to knee point.
2.This shows that FET behaves like an ordinary resistor.This
region is called as ohmic region.
3.ID increases with increase in drain to source voltage. Here the
drain current is increased slowly as compared to ohmic region.

19. • 4) It is because of the fact that there is an increase in VDS .This
in turn increases the reverse bias voltage across the gate
source junction .As a result of this depletion region grows in
size thereby reducing the effective width of the channel.
• 5) All the drain to source voltage corresponding to point the
channel width is reduced to a minimum value and is known as
pinch off.
• 6) The drain to source voltage at which channel pinch off occurs
is called pinch off voltage(Vp).

21. PINCH OFF Region:-
1.This is the region shown by the curve as saturation region.
2.It is also called as saturation region or constant current region.
Because of the channel is occupied with depletion region , the
depletion region is more towards the drain and less towards the
source, so the channel is limited, with this only limited number of
carriers are only allowed to cross this channel from source drain
causing a current that is constant in this region. To use FET as an
amplifier it is operated in this saturation region.
3.In this drain current remains constant at its maximum value IDSS.
4.The drain current in the pinch off region depends upon the gate to
source voltage and is given by the relation
• Id =Idss [1-Vgs/Vp]2
This is known as shokley’s relation.

22. BREAKDOWN REGION:-
1.The region is shown by the curve .In this region, the drain current
increases rapidly as the drain to source voltage is increased.
2.It is because of the gate to source junction due to avalanche effect.
3.The avalanche break down occurs at progressively lower value of
VDS because the reverse bias gate voltage adds to the drain voltage
thereby increasing effective voltage across the gate junction
• This causes
1. The maximum saturation drain current is smaller
2. The ohmic region portion decreased.
1.It is important to note that the maximum voltage VDS which can be
applied to FET is the lowest voltage which causes available break
down.

23. Transfer Characteristics
• Output Current Vs Input Voltage, keeping Output voltage constant.
• ID vs VGS, Keeping VDS constant.

24. Transfer Characteristics
• There are 2 ways of obtaining the transfer characteristics.
1. Using the equation
2. Using the output or drain characteristics.

25. VGS = -5V

26. Pinch off voltage (JFET)
• in junction field-effect transistors (JFETs), "pinch-off" refers to the
threshold voltage below which the transistor turns off.
• the pinch-off voltage is the value of Vds when the drain current
reaches a constant saturation value.

27. The threshold voltage
• The threshold voltage, commonly abbreviated as Vth or VGS(th), of a
field-effect transistor (FET) is the minimum gate-to-source voltage
(VGS) that is needed to create a conducting path between the source
and drain terminals. It is an important scaling factor to maintain
power efficiency.

28. MOSFET
• MOSFET stands for Metal Oxide Semiconductor Field
Effect Transistor.
• It is a type of Field Effect Transistor and it is voltage
controlled device.
• It is also called an Insulated Gate Field Effect Transistor
(IGFET).
• It is used for switching or amplifying electronic signals in
electronic devices.
• It is the most commonly used transistor and it can be
used in both analog and digital circuits.

30. Symbol of MOSFET:

31. Symbol of MOSFET:
• In the Enhancement MOSFET the source and the drain
are not connected physically, so in the symbol lines are
broken
• In the Depletion mode line is continuous.
• In the N-type the arrow points inside and in the P type
arrow points outside.

32. Construction of Enhancement
MOSFET:

33. Construction of N channel
Enhancement MOSFET:
• The metallic gate terminal in the MOSFET is insulated
from the semiconductor layer by a SiO2 layer or
dielectric layer.
• The MOSFET consists of three terminals, they are
source(S), Gate (G), Drain (D) and the body which is
called as substrate.
• The substrate is connected to the source internally.

34. Construction of N channel
Enhancement MOSFET:
• In N channel Enhancement MOSFET the source and
drain are of N type semiconductor which is heavily
doped and the Substrate is of P type semiconductor.
• Majority charge carriers are electrons.
• The source and drain terminals are physically separated
in Enhancement mode.

35. • In P channel Enhancement MOSFET the source and
drain are of P type semiconductor which is heavily
doped
• the Substrate is of N type semiconductor.
• Majority charge carriers are holes.

36. Construction of Depletion MOSFET:

37. Construction of N Channel
Depletion MOSFET:
• In the N Channel depletion MOSFET a small strip of
semiconductor of N type connects the source and drain.
The source and drain are of N type semiconductor and
the Substrate is of P type semiconductor.
• Majority charge carriers are electrons.
• The source and drain are heavily doped.

38. Construction of P Channel
Depletion MOSFET:
• In the P Channel depletion MOSFET a small strip of
semiconductor of P type connects the source and drain.
• The source and drain are of P type semiconductor and
the Substrate is of N type semiconductor.
• Majority charge carriers are holes.

39. Working of N channel Enhancement MOSFET
• In the enhancement mode the applied Gate voltage is always positive.
• It crosses the threshold voltage it turns ON.
• The current is generated due to the movement of majority carriers.
• In the N channel majority of carriers are electrons and in the P channel majority of
carriers are holes.
• The source is connected to the negative terminal.
• When the electrons move from source to drain the positive charges form below the
dielectric because the repulsive force from the gate combines with each other.
• When the applied gate voltage is increased the number of majority carriers becomes
more than the minority carriers below the dielectric medium.
• So the majority of carriers overcome the recombination of holes and electrons and the
majority of carriers move from source to drain in the channel, which forms the current.
• Thus the gate voltage controls the concentration of the majority of carriers which is
responsible for the formation of the channel.

41. Working of Depletion MOSFET:
• The depletion MOSFET is ON by default.
• The source and drain terminals are physically connected.
• When the gate terminal is connected to the negative terminal and source to
the positive terminal, the electrons gets repelled below the dielectric layer.
• The positive charged carrier from the source gets combined with the majority
carrier the electrons in the N type and thus depletion layer is formed
• the channel resistance increases and the current flow decreases.
• Thus the increase in gate voltage decreases the drain current.
• They are inversely proportional.
• When the negative voltage is further increased it reaches the pinch off mode.
• When the gate is connected to the positive terminal and the source terminal it
operates in the enhancement mode.

42. V-I Characteristics of MOSFET:

43. • Cut off region:
• No current flows through it and the MOSFET is off.
• Ohmic region:
• Drain current increases when the drain source voltage increases. Used as amplifier in
this region.
• Saturation region:
• Drain current is constant for drain source voltage. Used as switch in this region. This
occurs when the drain source voltage reaches pinch off voltage.
• Depletion mode:
• The MOSFET is ON by default. When negative voltage is applied to the gate terminal it
operates in the depletion mode and when positive voltage is applied, it operates in the
enhancement mode.
• Enhancement mode:
• When positive voltage is applied to the gate terminal, it starts conducting and the
current starts to flow.

44. Depletion MOSFET Enhancement MOSFET
The type of MOSFET where the channel depletes with
the gate voltage is know as depletion or simply D-
MOSFET.
The type of the MOSFET where the channel is
enhanced or induced using the gate voltage is known
as E-MOSFET.
The channel is fabricated during manufacturing. There is no channel during its manufacturing.
It conducts current between its source and drains
when there is no Gate voltage VGS.
It does not conduct current when there is no Gate
voltage VGS.
Applying reverse voltage to the gate reduces the
channel width.
Applying reverse voltage does not affect E-MOSFET
since there is no channel.
Applying forward voltage to the gate increases the
channel width.
Applying the forward voltage generates and increases
the width of the channel.
It can work in both depletion and enhancement mode. It can only work in enhancement mode.
It is a normally ON transistor. It is a normally OFF transistor.
It switches OFF with reverse biasing of gate. It switches ON with the forward biasing of the gate.
There is no threshold voltage for switching ON the
MOSFET.
There a threshold voltage at which the MOSFET
switches ON.
Diffusion or subthreshold current does not exist.
E-MOSFET has sub-threshold current leakage
between its source and drain.

45. Load line analysis of JFET

48. Types of Biasing in FET
• Fixed Bias Configuration
• Self-bias Configuration
• Voltage divider Bias
• Source bias

49. Fixed Bias Configuration

50. Fixed Bias Configuration
• N- Channel FET is used in the above diagram for forming Fixed bias
configuration.
• In the N-Channel FET the gate will be of P-type and it is reverse
biased.
• Two biasing voltages VDD and VGG are used.
• C1 and C2 are the coupling capacitors.
• V1 is the input voltage and V2 is the output voltage for the amplifier
circuit.
• In case of FET VGS is the input voltage and VDS is the output voltage

51. Fixed Bias Configuration
• In this biasing we are using DC sources (VDD and VGG) so we will
discuss DC analysis.
• As we are discussing DC analysis, the reactance of the capacitors C1
and C2 will be
• For DC signal frequency will be not be there and hence the frequency
is zero.
X c = ∞

52. Fixed Bias Configuration
• So the coupling circuit C1 and C2 will act as open circuit.

53. Fixed Bias Configuration

54. Fixed Bias Configuration
• Since gate is reverse biased, input impedance will be high and hence
the gate current is zero.

55. • Hence RG can be removed and act like a short circuit.

65. Self-bias Configuration

66. Self-bias Configuration
• In Self-bias, we will be having a single voltage biasing circuit(VDD).
• Source Resistance is present in self biasing circuit, where us it is not
there in the fixed biasing circuit.

70. Voltage divider Bias

71. Voltage divider Bias
• C1, C2 – Coupling capacitor.( blocks DC signal allows AC signal)
• Cs – Bypass capacitor. ( shorts AC signal to ground, allows DC signal)

80. Source Biasing

81. Source Biasing

82. Source Biasing

86. Source Biasing

87. JFET Small Signal Model
• Small Signal Model is used for the analysis of a given amplifier circ
by drawing its equivalent circuit.

90. There is no current or resistance in the input side as the gate is always reverse biased.