Chap13--Digital Modulation Techniques.ppt

Prof. J.F. Huang, Fiber-Optic Communication Lab.
National Cheng Kung University, Taiwan
Amplitude Shift Keying (ASK)
 ASK is implemented by changing the amplitude of a
carrier signal to reflect amplitude levels in the digital
signal.
 For example: a digital “1” could not affect the signal,
whereas a digital “0” would, by making it zero.
 The line encoding will determine the values of the
analog waveform to reflect the digital data being
carried.
1

Amplitude Shift Keying (ASK)
 Mathematically, ASK is
vask(t) = [1 vm(t)][A/2 cos(c t)]
 For logic 1 , vm(t)=+1V
vask(t) = [1  1][A/2 cos(c t)] = Acos(c t)
 For logic 0 , vm(t)=-1V
vask(t) = [1 - 1][A/2 cos(c t)] = 0
2

Binary Amplitude Shift Keying (BASK)
3

Bandwidth of ASK
 The bandwidth B of ASK is equal to the signal rate fb .
B = fb
 Baud = fb
4

Implementation of binary ASK
5

6
 The general expression for a binary FSK signal is
v(t) = Vccos{2π[fc vm(t)Df)]t} (13-3)
 where
v(t)= binary FSK waveform
Vc = peak unmodulated carrier amplitude
fc = carrier frequency
vm(t) = binary input modulating signal (volts)
Df = difference in output frequency
Frequency Shift Keying

7
Frequency Shift Keying
 From Equ. (13-3) it is seen that with binary FSK the
carrier amplitude Vc remains constant with modulation.
However, the output carrier frequency (fc) shifts by an
amount equal to +Df.
 The frequency shift Df is proportional to the amplitude
and polarity of the binary input signal. For example, a
binary ‘1’ could be +1 volt and a binary ‘0’ could be –1
volt producing frequency shifts of + Df and - Df,
respectively.

8
FSK Transmitter
 With binary FSK, the center carrier frequency is shifted
(deviated) by the binary input data. As the binary input
signal changes from a logic ‘0’ to a logic ‘1’, and vice versa,
the FSK output shifts between mark (or logic ‘1’)
frequency and space (or logic ‘0’) frequency.
 The rate of change at the modulator input is called the bit
rate and has the units of bits per second (bps). The rate of
change at the modulator output is called the baud rate
and is equal to the reciprocal of the time of one output
signaling element.
 In binary FSK, the input and output rates of change are
equal; therefore, the bit rate and baud rate are equal. A
simple binary FSK transmitter is shown in Figure 13-3.

9
Fig. 13-3. Binary FSK transmitter.
FSK Transmitter

10
Bandwidth Considerations of FSK
 Figure 13-4 shows a binary FSK modulator. The fastest
input rate of change occurs when the binary input is a
series of alternating 1’s and 0’s.
 Consequently, if only the fundamental frequency of the
input is considered, the highest modulating frequency is
equal to one-half of the input bit rate.
 A logic ‘1’ input shifts the VCO from its rest frequency
to the mark frequency, and a logic ‘0’ input shifts the
VCO from its rest frequency to the space frequency.

11
Fig. 13-4. FSK modulator.

12
 Consequently, as the input binary signal changes from
a logic ‘1’ to a logic ‘0’, and vice versa, the VCO output
frequency shifts or deviates back and forth between
the mark and space frequencies.
 For binary FSK, modulation index is given as
mf = Df / fa
= |(fm-fs)/2|/(fb/2)
= |fm - fs|/fb (13-4)
where mf = modulation index
Df = frequency deviation (Hz)
fa = modulating frequency (Hz)

13
 Example 13-1:
For a binary FSK modulator with space, rest, and mark
frequencies of 60, 70, and 80 MHz, respectively and an
input bit rate of 20 Mbps, determine the output baud
and the minimum required bandwidth.
Solution:
Substituting into Equ. (13-4), we have
mf = |(fm – fs)/fb|
= |80MHz–60MHz|/20Mbps
= 20MHz/20Mbps
= 1.0

14
 From the Bessel chart (Table 13-1), a modulation index
of 1.0 yields three sets of significant side frequencies.
Each side frequency is separated from the center
frequency or adjacent side frequency by the modulating
frequency, which is 10 MHz (fb/2) in this example.
 The output spectrum for this modulator is shown in
Figure 13-5. It can be seen that the minimum double-
sided Nyquist bandwidth is 60 MHz and the baud rate
is 20 megabaud, the same as the bit rate.

15

16
FSK Receiver
 The most common circuit used for demodulating binary
FSK signals is the phase-locked loop (PLL), which is
shown in block diagram form in Figure 13-6.
 As the input to the PLL shifts between the mark and
space frequencies, the dc error voltage at the output of
the phase comparator follows the frequency shift.
 The natural frequency of the PLL is generally made
equal to the center frequency of the FSK modulator.
The changes in the dc error voltage will then follow
the changes in the analog input frequency and are
symmetrical around 0 Vdc.

17
FSK Receiver

18
 Binary FSK has a poorer error performance than PSK
or QAM and, consequently, is seldom used for high-
performance digital radio systems.
 Its use is restricted to low-performance, low-cost,
asynchronous data modems that are used for data
communications over analog, voice band telephone lines.
FSK Receiver

19
Minimum Shift-Keying
 Minimum shift-keying (MSK) is a form of continuous-
phase FSK (CPFSK). Essentially, MSK is a binary
FSK except that the mark and space frequencies are
synchronized with the input binary bit rate.
 With MSK, the mark and space frequencies are selected
such that they are separated from the center frequency
by an exact odd multiple of one-half of the bit rate.
 This ensures that there is a smooth phase transition in
the analog output signal when it changes from a mark
to a space frequency, or vice versa.

20

21
 Figure 13-7 shows a noncontinuous FSK waveform. When
the input changes from a logic ‘1’ to a logic ‘0’, and vice
versa, there is an abrupt phase discontinuity in the analog
output signal.
 When this occurs, the demodulator has trouble following
the frequency shift; consequently, an error may occur.
Figure 13-8 shows a continuous phase MSK waveform.
 MSK has a better bit-error performance than conventional
binary FSK for a given SNR. The disadvantage of MSK is
that it requires synchronizing circuits and it therefore
more expensive to implement.

22

23
Binary Phase Shift Keying
 With binary phase shift keying (BPSK), two output phases are
possible for a single carrier frequency.
One output phase represents a logic ‘1’ and the other
a logic ‘0’.
 As the input digital signal changes state, the phase of the
output carrier shifts between two angles that are 180° out of
phase. BPSK is a form of suppressed carrier, square-wave
modulation of a continuous wave (CW) signal.

24
 BPSK Transmitter
Fig. 13-9. BPSK modulator.
Figure 13-9 shows a simplified block diagram of a BPSK
modulator. The balanced modulator acts like a phase
reversing switch.

25
 In BPSK, depending on the logic condition of the digital
input, the carrier is transferred to the output either in
phase or 180° out of phase with the reference carrier
oscillator.
 Figure 13-10a shows the schematic diagram of a
balanced ring modulator.
 If the binary input is a logic ‘1’ (positive voltage), diodes
D1 and D2 are forward biased and “on”, while diodes
D3 and D4 are reverse biased and “off” (Figure 13-10b).
 The carrier voltage developed across transformer T2
is in phase with the carrier voltage across T1.
Consequently, the output signal is in phase with the
reference oscillator.

26
Fig. 13-10. (a) Balanced ring modulator; (b) Logic ‘1’ input; (c) Logic ‘0’ input.

27
 If the binary input is a logic ‘0’ (negative voltage), diodes
D1 and D2 are reverse biased and “off,” while diodes D3
and D4 are forward biased and “on” (Figure 13-10c).
 The carrier voltage developed across transformer T2
is 180°out of phase with the carrier voltage across T1.
Consequently, the output signal is 180° out of phase with
the reference oscillator.
 Figure 13-11 shows the truth table, phasor diagram, and
constellation diagram for a BPSK modulator.
 A constellation diagram, or signal state-space diagram, is
similar to a phasor diagram except that the entire phasor
is not drawn. In a constellation diagram, only the relative
positions of the peaks of the phasors are shown.

28
Fig. 13-11. BPSK modulator: (a) truth table;
(b) phasor diagram; (c) constellation diagram.

29
 For BPSK, the output rate of change (baud) is equal to
the input rate of change (bps), and the widest output
bandwidth occurs when the input binary data are an
alternating 1/0 sequence.
 The fundamental frequency (fa) of an alternating 1/0 bit
sequence is equal to one-half of the bit rate (fb/2).
 Mathematically, the output phase a BPSK modulator is
output = (sinat) x (sinct)
= (1/2)cos(c-a)t – (1/2)cos(c+a)t (13-6)
 Consequently, the minimum double-sided Nyquist
bandwidth (fN) is fN = 2 x (fb/2) = fb .
Bandwidth Considerations of BPSK

30
 Figure 13-12 shows the output phase versus time
relationship for a BPSK waveform.
 The output spectrum from a BPSK modulator is simply
a double-sideband suppressed carrier signal where the
upper and lower side frequencies are separated from the
carrier frequency by one-half of the bit rate.
 Consequently, the minimum bandwidth (fN) required to
pass the worst-case BPSK output signal is equal to input
bit rate.

31
Fig. 13-12. Output phase vs. time for a BPSK modulator.

32
 Example 13-2: For a BPSK modulator with a carrier
frequency of 70 MHz and an input bit rate on 10 Mbps,
determine the maximum and minimum upper and lower
side frequencies, draw the output spectrum, determine the
minimum Nyquist bandwidth, and calculated the baud.
 Solution:
Substituting into Equ. (13-6) yields
Output = (sinat)(sinct)
  
5MHz)t
MHz
70
(
2
cos
2
1
-
5MHz)t
-
MHz
70
(
2
cos
2
1
MHz)t
70
(
2
sin
MHz)t
5
(
2
sin








33
 Minimum lower side frequency (LSF):
LSF = 70 MHz-5 MHz = 65 MHz
Maximum upper side frequency (USF):
USF = 70 MHz+5 MHz = 75 MHz
 The minimum Nyquist bandwidth (fN) for
the worst-case binary input conditions is
fN = 75 MHz – 65 MHz = 10 MHz
and the baud rate is fb = 10 megabaud.

34
BPSK Receiver
Fig. 13-13. BPSK receiver.

35
For BPSK input signal of +sinct (logic ‘1’), the output
of the balanced modulator is (sinct)(sinct) = sin2ct ,
or sin2ct = ½(1-cos2ct) = ½ - ½ cos2ct.
After LPF, the term of cos2ct will be filtered out, leaving
Output = +1/2 Vdc = logic ‘1’
For BPSK input signal of -sinct (logic ‘0’), the output
of the balanced modulator is -(sinct)(sinct) = -sin2ct ,
or -sin2ct = -½(1-cos2ct) = -½ + ½ cos2ct.
After LPF, the term of cos2ct will be filtered out, leaving
Output = -1/2 Vdc = logic ‘0’
BPSK Receiver

36
 Essentially, a QPSK modulator is two BPSK
modulators combined in parallel.
 For a logic ‘1’ = +1V and a logic ‘0’ = -1V, two phases
are possible at the output of the I balanced modulator
(+sinct and -sinct), and two phases are possible at
the output of the Q balanced modulator (+cosct and
-cosct).
 When the linear summer combines the two quadrature
(90° out of phase) signals, there are four possible
resultant phases: +sinct + cosct, +sinct - cosct,
-sinct + cosct, and -sinct - cosct.
Quaternary Phase Shift Keying

37
Fig. 13-14. QPSK modulator.

38
 Example 13-3:
For the QPSK modulator shown in Figure 13-14, construct the truth
table, phasor diagram, and constellation diagram.
Solution:
For a binary data input of Q=0 and I=0, the two inputs to the
I balanced modulator are –1 and sinct, and the two inputs to
the Q balanced modulator are –1 and cosct.
Consequently, the outputs are
I balanced modulator = (-1)(sinct) = -1.sinct
Q balanced modulator = (-1)(cosct) = -1.cosct
And the output of the linear summer is
-1.cosct – 1.sinct = 1.414sin(ct - 135o)
For the remaining digit codes (‘01’, ‘10’, and ‘11’), the
procedure is the same.

39
Fig. 13-15. QPSK modulator. (a) truth table;
(b) phasor diagram; (c) constellation.

40
 In Figure 13-15b it can be seen that with QPSK each of the four
possible output phasors has exactly the same amplitude.
Therefore, the binary information must be encoded entirely in
the phase of the output signal.
 From Figure 13-15b it can be seen that the angular separation
between any two adjacent phasors in QPSK is 90°. Therefore, a
QPSK signal can undergo almost a +45° or -45° shift in phase
during transmission and still retain the correct encoded
information when demodulated at the receiver.
 Figure 13-16 shows the output phase versus time relationship for
a QPSK modulator.

41
Fig. 13-16. Output phase vs. time for a QPSK modulator.

42
 The output of the balanced modulators can be
expressed mathematically as q = (sinat)(sinct)
where at = 2fbt/4 and at = 2fct .
Thus
q = (sin2fbt/4)(sin2fct)
= ½ cos2(fc - fb/4)t – ½ cos2(fc + fb/4)t
 The output frequency spectrum extends from fc - fb/4
to fc + fb/4 and the minimum bandwidth (fN) is
fN = ( fc - fb/4) – (fc + fb/4)
= 2fb/4 = fb/2.
Bandwidth Considerations of QPSK

43
Fig. 13-17. Bandwidth considerations of a QPSK modulator.

44
Example 13-4:
For a QPSK modulator with an input data rate (fb)
equal to 10 Mbps and a carrier frequency of 70 MHz,
determine the minimum Nyquist bandwidth (fN) and
the baud. Compare the results with those achieved
with the BPSK modulator in Example 13-2.
Solution:
 The bit rate in both the I and Q channels is equal to
one-half of the transmission bit rate or
fbQ = fbI = fb/2 = 10Mbps/2 = 5Mbps
 The highest fundamental frequency presented to either
balanced modulator is
fa = fbQ/2 = fbI/2 = 5Mbps/2 = 2.5Mbps.

45
 The output wave from each balanced modulator is
(sin2fat).(sin2fct)
= ½ cos2(67.5MHz)t - ½ cos2(72.5MHz)t
 The minimum Nyquist bandwidth is
fN = (72.5MHz - 67.5MHz) = 5MHz.
 The baud equals the bandwidth; thus baud rate is
5 megabaud.

46
 The output spectrum is as follows:
 For the same input bit rate the minimum bandwidth require to
pass the output of the QPSK modulator is equal to one-half of
that required for the BPSK modulator.
 Also, the baud rate for the QPSK modulator is one-half that of
the BPSK modulator.

47
 Figure 13-18 shows the schematic of a QPSK receiver.
 The received QPSK signal (-sinct + cosct) is one of
the inputs to the I product detector. The other input is
the recovered carrier (i.e., sinct).
 The output of the I product detector is
qI = (-sinct + cosct).(sinct)
= -½ + ½ cos2ct + ½ cos2ct + ½ sin0 .
 After LPF, the terms of cos2ct will be filtered out,
leaving Output = -1/2 Vdc = logic ‘0’.
QPSK Receiver

48
QPSK Receiver
Fig. 13-18. QPSK receiver.

49
 Again, the received QPSK signal (-sinct + cosct) is one
of inputs to the Q product detector. The other input is
the recovered carrier shifted 90° in phase (i.e., cosct).
 The output of the Q product detector is
qQ = (-sinct + cosct).(cosct)
= ½ + ½ cos2ct - ½ cos2ct - ½ sin0 .
 After LPF, the terms of cos2ct will be filtered out,
leaving Output = 1/2 Vdc = logic ‘1’.
 The demodulated I and Q bits (‘1’ and ‘0’, respectively)
correspond to the constellation diagram and truth table
for the QPSK modulator shown in Figure 13-15.
QPSK Receiver

50
Offset QPSK (OQPSK)
 OQPSK is a modified form of QPSK where the bit
waveforms or the I and Q channels are offset or shifted
in phase from each other by one-half of a bit time.
 Figure 13-19 shows a simplified block diagram, the bit
sequence alignment and the constellation diagram for
an OQPSK modulator.
 Because changes in the I channel occur at the
midpoints of the Q-channel bits, and vice versa, there
is never more than a single bit change in the dibit code,
and therefore there is never more than a 90° shift in the
output phase.

51
Fig. 13-19. Offset QPSK block diagram.
Offset QPSK (OQPSK)

52
 In conventional QPSK, change in the input dibit
from ’00’ to ’11’ or ’01’ to ’10’ causes a corresponding
180° shift in the output phase.
 An advantage of OQPSK is the limited phase shift that
must be imparted during modulation. A disadvantage
of OQPSK is that changes in the output phase occur at
twice the data rate in either the I or Q channels.
 Consequently, with OQPSK the baud and minimum
bandwidth are twice that of conventional QPSK for a
given transmission bit rate.
Offset QPSK (OQPSK)

53
8-PSK Transmitter
Fig. 13-20. 8-PSK modulator.

54
Fig. 13-21. I- and Q-channel 2-to-4-level converters:
(a) I-channel truth table; (b) Q-channel truth table; (c) PAM levels.
8-PSK Transmitter

55
Fig. 13-22. 8-PSK modulator: (a) truth table;
8-PSK Transmitter

56
Example 13-5:
For a tribit input of Q = 0, I = 0, and C = 0 (000), determine
the output phase for the 8-PSK modulator shown in Figure
13-20.
Solution:
The inputs to the I-channel 2-to-4-level converter are I = 0
and C = 0. From Figure 13-21 the output is –0.541V. The
inputs to the Q-channel 2-to-4-level converter are Q = 0 and
C = 1. Again from Figure 13-21, the output is –1.307V.
Thus the two inputs to the I-channel product modulators
are –0.541V and sinct. The output is
qI = (-0.541) (sinct) = -0.541 sinct.
8-PSK Transmitter

57
 The two inputs to the Q-channel product modulator are
–1.307V and cosct. The output is
qQ = (-1.307)(cosct) = -1.307 cosct.
 The outputs of the I- and Q-channel product modulators
are combined in the linear summer and produce a
modulated output of
qI + qQ = -0.541 sinct - 1.307 cosct
= 1.41 sin(ct – 112.5o)
 For the remaining tribit codes (‘001’, ‘010’, ‘011’, ‘100’,
‘101’, ‘110’, and ‘111’), the procedure is the same.
8-PSK Transmitter

58
Fig. 13-23. Output phase versus time for an 8-PSK modulator.
8-PSK Transmitter

59
Fig. 13-24. Bandwidth considerations of an 8-PSK modulator.
Bandwidth Considerations of 8-PSK

60
 With 8-PSK, since the data are divided into three channels,
the bit rate in the I, Q, or C channel is equal to 1/3 of the
binary input data rate (fb/3). (The bit splitter stretches the I,
Q, and C bits to three times their input bit length.)
 Figure 13-24 shows the bit timing relationship between the
binary input data; the I-, Q-, and C-channel data; and the I
and Q PAM signals.
 The highest fundamental frequency in the I, Q or C channel
is equal to 1/6 of the bit rate of the binary input (one cycle in
the I, Q, or C channel takes the same amount of time as six
input bits).
 Also, the highest fundamental frequency in either PAM
signal is equal to one-sixth of the binary input bit rate.

61
Fig. 13-24. Bandwidth considerations of an 8-PSK modulator.

62
 With an 8-PSK modulator, there is one change in phase
at the output for every 3 data input bits. Consequently,
the baud for 8-PSK equals fb/3, the same as the
minimum bandwidth.
 The output of the balanced modulators is
q = (X sinat)(sinct) (13-11)
where at = 2 fbt/6 and ct = 2 fct
and X = +1.307 or +0.541
 Thus q = (X sin2fbt/6)(sin2fct)
t
f
f
X
t
f
f
X b
c
b
c 















6
2
cos
2
6
2
cos
2



63
 The output frequency spectrum extends from fc-fb/6 to
fc+fb/6 and the minimum bandwidth (fN) is
fN = (fc+(fb/6)) – (fc-(fb/6)) = 2fb/6 = fb/3.
Example 13-6:
For an 8-PSK modulator with an input data rate (fb)
determine the minimum double-sided Nyquist BW (fN)
and the baud. Also, compare the results with those
achieved with the BPSK and QPSK modulators in
Examples 13-2 and 13-4.

64
Solution:
The bit rate in the I, Q, and C channels is equal to
one-third of the input bit rate, or
fbC=fbQ=fbI = 10Mbps/3 =3.33Mbps.
The faster rate of change and highest fundamental
frequency presented to either balanced modulator is
fa = fbC/2 = fbQ/2 = fbI/2
= 3.33Mbps/2 = 1.667Mbps
The output wave from the balance modulator is
(sin2fat)(sin2fct)
= ½[cos2(68.333MHz)t – cos2(71.667MHz)t]

65
fN = (71.667 – 68.333)MHz = 3.333MHz.
Again, the baud equals the bandwidth; thus
Baud = 3.333 megabaud
The output spectrum is as follows:

66
 For the same input bit rate the minimum bandwidth
required to pass the output of an 8-PSK modulator
is equal to one-third that of the BPSK modulator in
Example 13-2 and 50% less than that required for
the QPSK modulator in Example 13-4.
 Also, in each case the baud has been reduced by the
same proportions.

67
8-PSK Receiver
Fig. 13-25. 8-PSK receiver.

68
 Figure 13-25 shows a block diagram of an 8-PSK
receiver. The power splitter directs the input 8-PSK
signal to the I and Q product detectors and the carrier
recovery circuit.
 The carrier recovery circuit reproduces the original
reference oscillator signal.
 The incoming 8-PSK signal is mixed with the
recovered carrier in the I product detector and with a
quadrature carrier in the Q product detector.
 The outputs of the product detectors are 4-level PAM
signals that are fed to the 4-to-2- level analog-to-digital
converters (ADCs).
8-PSK Receiver

69
 The outputs from the I-channel 4-to-2- level converter
are the I and C bits, while the outputs from the Q-
channel 4-to-2-level converter are the Q and C bits.
 The parallel-to-serial logic circuit converts the I/C and
Q/C bit pairs to serial I, Q, and C output data streams.
C
8-PSK Receiver

70
8-QAM Transmitter
 The difference between the 8-QAM (Figure 13-27) and
the 8-PSK (Figure 13-19) is the omission of the inverter
between the C channel and the Q product modulator.
 As with 8-PSK, the incoming data are divided into
groups of three (tribits): the I, Q, and C channels, each
with a bit rate equal to one-third of the incoming data
rate.
 Again, the I and Q bits determine the polarity of the
PAM signal at the output of the 2-to-4-level converters,
and the C channel determines the magnitude.

71
Figure 13-27. 8-QAM transmitter block diagram.
8-QAM Transmitter

72
 Because the C bit is fed uninverted to both the I- and
Q-channel 2-to-4-level converters, the magnitudes of I
and Q PAM signals are always equal.
 Their polarities depend on the logic condition of the I
and Q bits and therefore may be different.
 Figure 13-28 shows the truth table for the I and Q-
channel 2-to-4-level converters; they are the same.
8-QAM Transmitter

73
Fig. 13-28. Truth table for the I- and Q-channel 2-to-4-level converters.
8-QAM Transmitter

74
Fig. 13-28. 8-QAM modulator: (a) truth table;
8-QAM Transmitter

75
Example 13-7:
For a tribit input of Q = 0, I = 0, and C = 0 (input
sequence ‘000’), determine output amplitude and phase
for the 8-QAM modulator of Figure 13-27.
Solution:
 The inputs to the I-channel 2-to-4-level converter are I=0
and C=0. From Figure 13-28 the output is -0.541V.
 The inputs to the Q-channel 2-to-4-level converter are
Q=0 and C=0. From Figure 13-28 the output is -0.541V.
 Thus the two inputs to the I-channel product modulator
are -0.541 and sinct. The I-channel output is
qI = (-0.541)(sinct) = -0.541 sinct
8-QAM Transmitter

76
 The two inputs to the Q-channel product modulator
are -0.541 and cosct. The Q-channel output is
qQ = (-0.541)(cosct) = -0.541 cosct
 The outputs from the I- and Q-channel product
modulators are combined in the linear summer and
produce a modulated output of
qI + qQ = -0.541 sinct - 0.541 cosct
= 0.765 sin(ct – 135o)
 For the remaining tribit codes (‘001’, ‘010’, ‘011’, ‘100’,
‘101’, ‘110’, and ‘111’), the procedure is the same.
8-QAM Transmitter

77
Figure 13-29. Output phase and amplitude versus time
relationship for 8-QAM.
8-QAM Transmitter

78
Bandwidth Considerations of 8-QAM
 In 8-QAM, the bit rate in the I and Q channels is 1/3
of the input binary rate, the same as in 8-PSK.
 As a result, the highest fundamental modulating
frequency and fastest output rate of change in 8-QAM
are the same as with 8-PSK.
 Therefore, the minimum bandwidth required for 8-
QAM is fb/3, the same as in 8-PSK.

79
Fig. 13-30. 8-QAM receiver.
8-QAM Receiver

80
8-QAM Receiver
 An 8-QAM receiver (Figure 13-30) is almost identical to the
8-PSK receiver (Figure 13-25). The differences are the PAM
levels at the output of the product detectors and the binary
signals at the output of the A/D converters.
 Because there are two transmit amplitudes possible with 8-
QAM that are different from those achievable with 8-PSK,
the four demodulated PAM levels in 8-QAM are different
from those in 8-PSK.
 The conversions factor for the A/D converters must also be
different. Also, with, 8-QAM the binary output signals from
the I-channel A/D converter are the I and C bits, and the
binary output signals from the Q-channel A/D converter are
the Q and C bits.

81
16-QAM Transmitter
 The block diagram for 16-QAM transmitter is shown
in Figure 13-31. The input binary data are divided into
four channels: The I, I’, Q, and Q’.
 The bit rate in each channel is equal to 1/4 of the input
bit rate (fb/4). Four bits are serially clocked into the bit
splitter; then they are outputted simultaneously and in
parallel with the I, I’, Q, and Q’ bits determine the
magnitude (a logic ‘1’ = 0.821V and a logic ‘0’ = 0.22V).
 The 2-to-4-level converters generate a 4-level PAM
signal. Two polarities and two magnitudes are possible
at the output of each 2-to-4-level converter. They are
+0.22V and +0.821V.

82
Fig. 13-31. 16-QAM transmitter block diagram.
16-QAM Transmitter

83
 The PAM signals modulate the in-phase and
quadrature carriers in the product modulators.
Four outputs are possible for each product modulator.
 For the I product modulator they are +0.821sinct,
-0.821sinct, +0.22sinct, and -0.22sinct.
For the Q product modulator they are -0.821cosct,
+0.22cosct, -0.821cosct, and -0.22cosct.
 The linear summer combines the outputs from the I-
and Q-channel product modulators and produces the
16 output conditions necessary for 16-QAM.
 Figure 13-32 shows the truth table for the I- and Q-
channel 2-to-4-level converters.
16-QAM Transmitter

84
Fig. 13-32. Truth tables for the I- and Q-channel 2-to-4 level
converters: (a) I channel; (b) Q channel.
16-QAM Transmitter

85
Example 13-8:
For a quadbit input of I = 0, I' = 0, Q = 0, and Q' = 0 (input
sequence of ‘0000’), determine the output amplitude and
phase for the 16-QAM modulator shown in Figure 13-31.
Solution:
 The inputs to the I-channel 2-to-4-level converter are
I=0 and I'=0. From Figure 13-32, the output is -0.22 V.
 The inputs to the Q-channel 2-to-4-level converter are
Q=0 and Q'=0. From Figure 13-32, the output is -0.22V.
 Thus the two inputs to the I-channel product modulator
are -0.22V and sinct. The I-channel output is
qI = (-0.22)(sinct) = -0.22sinct
16-QAM Transmitter

86
 The two inputs to the Q-channel product modulator
are -0.22V and cosct. The Q-channel output is
qQ = (-0.22)(cosct) = -0.22cosct
 The outputs from the I- and Q-channel product
modulators are combined in the linear summer and
produce a modulated output of
qI + qQ = - 0.22sinct - 0.22 cosct
= 0.311 sin(ct - 135o).
 For the remaining quadbit codes the procedure is the
same. The results are shown in Figure 13-33.
16-QAM Transmitter

87
Fig. 13-33. 16-QAM modulator: (a) truth table
16-QAM Transmitter

88
Fig. 13-33. 16-QAM modulator: (b) phasor diagram;
(c) constellation diagram.
16-QAM Transmitter

89
 With 16-QAM, since input data are divided four channel,
the bit rate in the I, I’, Q, and Q’ channel is equal to 1/4 of the
binary input data rate (fb/4).
 Because the I, I’, Q, and Q’ bits are outputted simultaneously
and in parallel, the 2-to4-level converters see a change in their
inputs and outputs at a rate equal to 1/4 of the input data rate.
 Figure 13-34 shows the bit timing relationship between the
binary input data; the I, I’, Q, and Q’ channel data; and the I-
channel PAM signal.
 The highest fundamental frequency in the I, I’, Q, and Q’
channel is equal to 1/8 of the bit rate of the binary input data
(one cycle in the I, I’, Q, and Q’ channel takes the same amount
of time as 8 input bits). The highest fundamental frequency of
either PAM signal is equal to 1/8 of the binary input bit rate.

90
 With a 16-QAM modulator, there is one change in the
output signal (either its phase, amplitude, or both) for
every 4 input data bits. Consequently, the baud equals
fb/4, the same as the minimum bandwidth.
 The balanced modulators are product modulators and
their outputs can be represented mathematically as
q = (X sinat)(sinct) (13-11)
where at = 2fbt/8 and ct = 2fct
and X = +0.22 or +0.821
 Thus q = (X sin2fbt/8)(sin 2fct)
= (X/2)cos2(fc-(fb/8))t - (X/2)cos2(fc+(fb/8))t

91
 The output frequency spectrum extends from fc – (fb/8)
to fc +(fb/8) and the minimum bandwidth (fN) is
fN = (fc + (fb/8)) – (fc – (fb/8)) = 2fb/8 = fb/4.
Fig. 13-34. Bandwidth considerations of a 16-QAM modulator.

92
Fig. 13-34. Bandwidth considerations of a 16-QAM modulator.

93
 Example 13-9:
For a 16-QAM modulator with an input data rate (fb)
determine the minimum double-sided Nyquist
frequency (fN) and the baud.
 Also, compare the results with those achieved with the
BPSK, QPSK, and 8-PSK modulators in Examples 13-
2, 13-4, and 13-6. Use the 16-QAM block diagram
shown in Figure 13-27 as the modulator model.

94
 Solution:
The bit rate in the I, I’, Q, and Q’ channels is equal to
1/4 of the input bit rate or
fbI = fbI’ = fbQ = fbQ’ = fb/4 = 10Mbps/4 = 2.5 Mbps
 Therefore, the faster rate of change and highest
fundamental frequency presented to either balanced
modulator is
fa = fbI/2 = fbI’/2 = fbQ/2 = fbQ’/2
= 2.5 Mbps/2 = 1.25 Mbps
 The output wave from the balanced modulator is
(sin2fat)(sin2fct)
= ½ cos[2(68.75MHz)t] - ½ cos[2(71.25MHz)t]

95
fN = (71.25 – 68.75)MHz = 2.5MHz.
Again, the baud equals the bandwidth; thus
Baud = 2.5 megabaud
The output spectrum is as follows:

96
 For the same input bit rate, the minimum bandwidth
required to pass the output of a 16-QAM modulator
is equal to one-fourth that of the BPSK modulator,
one-half that of QPSK, and 25% less than with 8-PSK.
 For each modulation technique, the baud is also
reduced by the same proportions.

97
Bandwidth Efficiency
 Bandwidth efficiency is the ratio of the transmission
bit rate to the minimum bandwidth required for a
particular modulation scheme.
 Bandwidth efficiency generally indicates the number
of bits that can be propagated through a medium for
each hertz of bandwidth:
cycle
bits
hertz
d
bits/secon
(Hz)
bandwidth
minimum
(bps)
rate
on
transmissi
effeciency
BW


 (13-12)

98
 Example 13-10: Determine the bandwidth efficiencies
for the following modulation schemes: BPSK, QPSK,
8-PSK, and 16-QAM.
Solution: Recall from Examples 13-2, 13-4, 13-6, and
13-9 the minimum bandwidths required to propagate
a 10-Mbps transmission rate with the modulation
schemes:

99
 Substituting into Equ. 13-12, the bandwidth
efficiencies are determined:
 The results indicate that BPSK is the least
efficient and 16-QAM is the most efficient.16-
QAM requires one-fourth as much bandwidth
as BPSK for the same bit rate.
BPSK: BW efficiency =
QPSK: BW efficiency =
8-PSK: BW efficiency =
16-QAM: BW efficiency =
cycle
bit
Hz
bps
MHz
Mbps 1
1
10
10


cycle
bit
Hz
bps
MHz
Mbps 2
2
5
10


cycle
bit
Hz
bps
MHz
Mbps 3
3
33
.
3
10


cycle
bit
Hz
bps
MHz
Mbps 4
4
5
.
2
10



100
Probability of Error and Bit Error Rate
 Probability of error P(e) and bit error rate (BER) are often
used interchangeably, although in practice they do have
slightly different meanings.
 P(e) is a theoretical (mathematical) expectation of the bit
error rate for a given system. BER is an empirical
(historical) record of a system’s actual bit error
performance.
 Probability of error is a function of the carrier-to-noise
power ratio (or more specifically, the average energy-per-bit
to noise-power-density ratio) and the number of possible
encoding conditions used (M-ary).
 Carrier-to-noise power ratio is the ratio of the average
carrier power (the combined power of the career and its
associated sidebands) to the thermal noise power.

101
 Carrier power can be stated in watts or dBm, where
C(dBm) = 10log[C(watts)/0.001] (13-13)
 Thermal noise power is expressed mathematically as
N = kTB (watts) (13-14a)
or N(dBm) = 10log(kTB/0.001) (13-14b)
 Mathematically, the carrier-to-noise power ratio is
C/N = C/kTB (13-15a)
where
C = Carrier power (W)
N = thermal noise power (W)
k = Boltzmann's constant (1.38×10-23 J/oK)
T = temperature (0oK = -273 oC, Room temp. = 290oK)
B = bandwidth (Hz).

102
 Energy-per-bit to noise-power-density ratio is simply the
ratio of the energy of a single bit to the noise power
present in 1 Hz of bandwidth.
Eb/No = (C/fb) / (N/B) (13-18a)
= (C/N) x (B/fb) (13-18b)
or Eb/No (dB) = 10log(C/N) + 10log(B/fb) (13-18c)
 Where
Eb/No = energy per bit-to-noise power density ratio
C/N = carrier-to-noise power ratio
B/fb = noise bandwidth-to-bit rate ratio

103
 From Equ. (13-18b) it can be seen that the Eb/No ratio
is simply the product of the carrier-to-noise power
ratio and the noise-bandwidth-to-bit-rate ratio.
 From Equ. (13-18b), it can be seen that when the
bandwidth equals the bit rate, Eb/No = C/N.
 In general, the minimum carrier-to-noise power ratio
required for QAM system is less than that required
for comparable PSK system.
 Also, the higher the level of encoding used (the higher
the value of M), the higher the minimum carrier-to-
noise power-ratio.

104
PSK Error Performance
 The general expression for the bit-error probability
of an M-phase PSK system is
)
(
log
1
)
(
2
z
erf
M
e
P  (13-22)
where erf = error function
z =   
0
2 /
log
sin N
E
M
M
b


105
Fig. 13-41. PSK error region: (a) BPSK; (b) QPSK.

106
 It can be shown that QPSK provides the same error
performance as BPSK. This is because the 3-dB
reduction in error distance for QPSK is offset by the
3-dB decrease in its bandwidth (in addition to the
error distance, the relative widths of the noise
bandwidths must also be considered).
 Thus both systems provide optimum performance.
Figure 13-42 shows the error performance for 2-, 4-,
8-, 16-, and 32-PSK systems as a function of Eb/No.

107
Fig. 13-42. Error rates of PSK modulation systems.

108
 The general expression for the bit error probability of
an L-level QAM system is
)
(
1
log
1
)
(
2
z
erfc
L
L
L
e
P 




 
 (13-24)
where erfc(z) = complementary error function
0
2
1
log
N
E
L
L
z b


Figure 13-43 shows the error performance for 4-, 16-,
32-, and 64-QAM systems as a function of Eb/No.
QAM Error Performance

109
Fig. 13-43. Error rates of QAM modulation systems.
QAM Error Performance

Chap13--Digital Modulation Techniques.ppt

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