The document discusses different types of inverters, including half bridge and full bridge single phase inverters, series inverters, parallel inverters, and pulse width modulation (PWM) control methods. Series inverters have commutating components connected in series with the load and operate at high frequencies. Parallel inverters use a commutating capacitor connected in parallel with the load. PWM control varies the pulse width to regulate the output voltage without additional components. Single pulse width modulation controls one device per half cycle, while multiple pulse width modulation uses multiple pulses per half cycle to reduce harmonics.

1. Inverter –unit-3
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2. INTRODUCTION
A CIRCUIT THAT CONVERTS DC POWER INTO AC
POWER AT DESIRED OUTPUT VOLTAGE AND
FREQUENCY IS CALLED AN INVERTER.
APPLICATIONS
❑ADJUSTABLE SPEED DRIVES
❑INDUCTION HEATING
❑STAND-BY AIRCRAFT POWER SUPPLIES
❑UPS FOR COMPUTERS,
❑ HVDC TRANSMISSION LINES
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3. CLASSIFICATION
VOLTAGE SOURCE
INVERTER
• IT HAS STIFF DC
VOLTAGE SOURCE AT
ITS INPUT TERMINALS.
• IT HAS SMALL AND
NEGLIGIBLE
IMPEDANCE.
• IN VSI USING
THYRISTOR FORCED
COMMUTATION
REQUIRED
CURRENT SOURCE
INVERTER
• CSI IS FED WITH
ADJUSTABLE DC
CURRENT SOURCE.
• IT HAS HIGH INTERNAL
IMPEDANCE.
• IT HAS STIFF CURRENT
SOURCE OUTPUT
CURRENT NOT
AFFECTED BY LOAD.
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4. From the view point of connections of
semiconductor devices, inverters are
classified under,
• Bridge inverter
• Series inverter
• Parallel inverter
❖ VSI using transistor
turned off by
controlling its basic
current,
❖ GTO- self
commutated inverter
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5. Single phase Half bridge inverters
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6. ✓ Consists two SCRs, two diodes and three wire supply.
✓ 0<t<T/2 Thyristor 1 conducts and load is subjected to Vs / 2 due to
upper voltage source Vs /2
✓ At t=T/2 T1 is commutated and T2 is gated ON .
✓ During the period T/2<t<T , thyristor T2 conducts and the load is
subjected to --Vs /2 due to lower voltage source Vs /2
✓ The alternating voltage waveform amplitude is Vs /2 and frequency 1/T
Hz.
✓ Frequency of the inverter output voltage can be changed by controlling
T`
✓ The main draw back of Half bridge inverter is that it requires 3 wire dc
supply
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7. Single phase Full bridge inverters
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8. ✓ The draw back of half bridge overcome by use of full bridge inverter
✓ It consists of four diodes and four SCRs, output voltage doubled.
✓ When T1, T2 conduct, load voltage is Vs and when T3,T4 conduct
load voltage is –Vs
✓ Frequency of output voltage can be controlled by varying the time T
✓ During inverter operation it should be ensured that two SCRs in same
branch do not conduct simultaneously.
✓ For Resistive load, Load current and load voltage would always be in
phase with each other.
✓ For other load io will not in phase with V0 , diodes will allow to current
flow when thyristors turned off.
✓ As the energy is fed back to the dc source when these diodes conduct,
theses are called feed back diodes. 8

9. SUMMARY
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10. Series Inverter
-Commutating components permanently connected
in series with the load
-Self commutated inverters
-Operates at high frequency(200 Hz to 100 kHz)
- Size of commutating components are small
- Used Extensively in induction heating, fluorescent
lighting
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11. Basic Series inverter
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❖ It consists of load resistance R in
series with commutating
components L and C.
❖ L and C Values chosen to form a
under damped circuit
❖ Two thyristors T1 and T2 are turned on appropriately
so that output voltage of desired frequency can be
obtained
❖ When thyristor T1 is turned on, with T2 off, current I
starts building up in the RLC circuit.

12. Basic Series inverter - operation
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-load current decays to Zero at a
after reaching peak value
-T1 is commutated then capacitor
upper plate attain +ve polarity.
-when T2 turned on at b capacitor
begin to discharge and load current
builds up in reverse direction.
-Then decays to zero at c, at d T1 is
again turned on and process repeats.
-The capacitor stores charge during
one half cycle and releases the same
amount of charge during next cycle
Toff =ab, cd- turn off time or dead zone time
tq.min – minimum time to regain forward blocking capability of T1
Load current wave form of series inverter

13. Basic Series inverter – Drawbacks
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-for load power, load current is taken from the supply during positive half cycle only
This has the effect of increasing the peak current rating of DC current.
- Since source current flows during the positive half cycle only, its harmonic content is
much pronounced.
-the maximum operating frequency of the inverter is limited because this frequency
ω has to be less than the circuit ringing frequency.
-for output frequency much lower than the circuit ringing frequency, the load voltage
waveform gets distorted considerably due to the increased duration of the dead
zone.
-Amplitude and duration of load current flow in each half cycle depends on the
load circuit parameters. Therefore these inverter suffer from poor output regulation

14. Modified Series inverter
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-draw back of limited frequency is overcome
- Consist of T1,T2, dc source voltage, Load R, capacitor, mid
tapped inductor. .
-means it has center tapping and both halves of inductance are
equal.( L1= L2)
-T1 switched on and load current builds up through R and then
decreases.
-When i=0, vc is less than vs + vco, now SCR T2 turned on.
-Since L1 and L2 are mutually coupled, KVL for loop 1 via T1,Vs, R,C,L1 …vT1 = - 0.5 Vco –iR
drop.
- Since vT1 is negative , T1 reverse biased. And T2 turned on, gets forward biased by voltage
VT2 = emf in L2+(vs + vco) +iR drop
-no danger of any short circuit. Modified one permits operate at frequency higher than ωr

15. Parallel inverter
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➢ consists of two SCRs T1 and T2,
an inductor L, an output
transformer and a commutating
capacitor C.
➢ The output voltage and current
are Vo and Io respectively.
➢ The function of L is to make the source current constant.
➢ During the working of this inverter, capacitor C comes
in parallel with the load via the transformer.
➢ So it is called a Parallel inverter

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Mode I
➢ In this mode, SCR T1 is conducting
and a current flow in the upper half
of primary winding. SCR T2 is OFF.
➢ As a result an emf Vs is induced
across upper as well as lower half
of the primary winding.
➢ In other words total voltage across
primary winding is 2 Vs.
➢ Now the capacitor C charges to a
voltage of 2Vs with upper plate as
positive.
-Steady state current flows through Vs,
L, T1, and upper half f primary
winding.

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➢ Mode II
➢ At time to, T2 is turned ON by
applying a trigger pulse to its gate.
➢ At this time t=0, capacitor voltage
2Vs appears as a reverse bias
across T1, it is therefore turned OFF.
➢ A current Io begins to flow through
T2 and lower half of primary
winding.
➢ Now the capacitor has charged
(upper plate as negative) from
+2Vs to -2Vs at time t=t1.
➢ Load voltage also changes from Vs
at t=0 to –Vs at t=t1.

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Mode III
➢ When capacitor has charged to
–Vs, T1 may be tuned ON at any
time .
➢ When T1 is triggered, capacitor
voltage 2Vs applies a reverse
bias across T2, it is therefore
turned OFF.
➢ After T2 is OFF, capacitor starts
discharging, and charged to the
opposite direction, the upper
plate as positive.

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Wave form of current and voltage in single phase parallel inverter

20. This is most efficient method of inverter output voltage control.
The constant DC input voltage is applied at the input of the
inverter and output voltage is controlled by switching
semiconductor device of the inverter in this method.
Advantages: There are no necessary of any extra components to
control output voltage of inverter.
As the low order harmonics ( 3rd, 5th ) reduces whereas higher
order harmonics ( 7th , 9th and 11th ) are filter out, less
requirement of filter.
Disadvantages:
As the switching semiconductor device requires low turn on and
turn off time, cost of semiconductor device increases.
Pulse width modulation ( PWM )

21. Methods of PWM control
Single pulse width modulation ( SPWM )
•As the semiconductor device receives only one pulse during one half
cycle, one semiconductor device is switched on.
•The output voltage of the inverter can be controlled by controlling
width of pulse.
•The gate signal is generated by comparing VR amplitude reference
signal and VC amplitude control signal.
•The width of gate pulse can be varies from 0o to 180o by controlling
the reference signal from 0 to VR.
•This will control the output voltage of the inverter.
•The frequency of the output voltage depends upon frequency of
reference signal.

23. The amplitude modulation M is ratio of reference signal
( VR ) and carrier signal ( VC).
M = VR / VC
The analysis of waveform shown in the figure A is done
by fourier series. The output voltage becomes maximum
when the width of pulse becomes π radian.
VL = 4VDC / π ...........................................(1)
RMS output voltage
VRMS = VDC √ d / π....................................(2)
And maximum value of nth harmonic
VLn = 4VDC / nπ ( Sin nd / 2 ) .....................(3)
From equation (1) and (3)
VLn / VL = Sin ( nd / 2) / n ..........................(4)

24. The graphical representation of pulse width in degree ( x – axis ) and n = 1, 3, 5 and 7 ( y – axis ) is shown
in the figure I

25. • When a value of the fundamental component becomes equal to 0.143, the third, fifth and seventh
harmonics becomes equal.
•This will conclude the higher harmonics remains present when the output voltage is low.
Waveform Y - axis X – axis
Fundamental n = 1 Sin ( d / 2 ) Pulse width in degree
3rd harmonic n = 3 Sin ( 3d / 2 ) / 3
5th harmonic n = 5 Sin ( 5d / 2 ) / 5
7th harmonic n = 7 Sin ( 7d / 2 ) / 7

26. Multiple pulse width modulation ( MPWM )
•There are more than one pulse per half cycle in the MPWM.
•These gate pulses are used to control output voltage of inverter as well
as reduce harmonics.
•The magnitude and width of the pulses are equal in this method.
•The reference signal and higher frequencies carrier signals are compared
in this method in order to generate more than one gating pulses.
•The number of gate pulses depends upon carrier frequencies whereas
the output voltage depends frequencies of reference signal.

27. Carrier frequency = fC in Hz
Reference frequency = fR in Hz

28. 1 / fC = π / 3..................................................(5)
OR
TC = π / 3
Similarly
1 / 2fR = 1 / π ...............................................(6)
OR
TR = π / 2
There the Number of pulses per half cycle
( NP ) = Length of half cycle reference signal /
Length of one cycle triangular waveform
= ( fR / 2 ) / ( 1 / fC )
NP = fC / 2 fR
Number of generated pulses NP = ( 3 / π ) × π [ from equation (5) and (6) ]
= 3
The RMS voltage when pulse width is equal to d
VRMS = VDC √ ( NP × d / π

29. •As the number of pulses increases in the each half cycle, lower order
harmonics reduces but higher order harmonics increases.
•The higher order harmonics are reduced by using filter.
•It is to be noted that the switching losses of the semiconductor increases as
there are more number of pulses per half cycle.
•This modulation technique is also called as symmetrical modulation control

30. Sinusoidal Pulse width Modulation ( SINPWM )
The reference signal is taken as sinusoidal waveform whereas the carrier
signal is taken as triangular waveform in this method.
The width of pulse in the SINPWM is not equal due to reference signal is
taken as sinusoidal waveform.
The amplitude of sinusoidal waveform is also not constant.
The width of gate pulse is determined by intersect point of the sinusoidal
waveform and triangular waveform.
The frequency of inverter output voltage depends upon frequency of
reference signal fR and amplitude of reference signal VR controls the
modulation index ( M ).

31. The number of pulses per half cycle when the amplitude of triangular waveform
becomes maximum and sinusoidal waveform becomes zero.
NP = fC / 2 fR
Where
fC = Carrier wave frequency = 3 / π
fR = Reference wave frequency = 1 / 2π
Therefore
NP = ( 3 / π ) × ( 2π / 2 )
= 3
The number of pulses per half cycle when the amplitude of triangular waveform
and sinusoidal becomes zero at same time.
NP = ( fC / 2 fR – 1 )
= 2

34. The modulation index = VR / VC
The analysis of harmonics is done in the sinusoidal PWM control is below.
When the value of modulation index is less than one, the maximum harmonic number in the
output voltage is
fC / fR ± 1 OR 2NP ± 1
Where NP = Number of pulses per half cycle
As the number of pulses per half cycle increases, the higher order harmonics also
increases.
Let NP = 4, it will generates 7th harmonic and 9th harmonic but higher order harmonics are
easily filtered out.
As the number of pulses increases per half cycle, the switching losses also increase and it
will affect the efficiency of inverter.
When the modulation index is greater than one, lower order harmonics induces in the
output of the inverter.

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