This document describes the design of an 8-bit current steering digital to analog converter (DAC) using full swing GDI logic. The DAC was implemented in a 0.13 μm CMOS process with a supply voltage of 3.3V. Simulation results showed the DAC operated at 200MHz with low power consumption of 16.823mW. Differential and integral nonlinearities were both below 0.121 least significant bits, and active area was reduced to 0.00447mm2 compared to previous designs. The DAC is suitable for low-power and high-speed applications.

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International Journal of Electronics and Communication Engineering & Technology
(IJECET)
Volume 6, Issue 9, Sep 2015, pp. 97-106, Article ID: IJECET_06_09_011
Available online at
http://www.iaeme.com/IJECETissues.asp?JType=IJECET&VType=6&IType=9
ISSN Print: 0976-6464 and ISSN Online: 0976-6472
© IAEME Publication
DESIGN OF 8-BIT CURRENT STEERING
DIGITAL TO ANALOG CONVERTER USING
FULL SWING GDI LOGIC
Kolli Ramesh
Department of Electronics and Communication Engineering,
MVGR College of Engineering,
Vizianagaram, India
Mr. A. Ashok Kumar
Department of Electronics and Communication Engineering,
MVGR College of Engineering,
Vizianagaram, India
ABSTRACT
A low-voltage low-power small-area digital to analog converter (DAC) for
high speed applications is introduced in this paper. A current steering digital
to analog converter is well suitable for high speed application, because all the
currents taken from the supply is used for the output signal. In this paper it
deals with the design and analysis of an 8-bit current steering digital to
analog converter which was implemented using full Swing (FS) GDI Logic in
CMOS process. The active area of this proposed DAC was reduced to four
times in a standard 1P3M 0.13 µm 3.3V CMOS process, both the INL and
DNL were reduced to half of 8-bit DAC implemented using conventional logic
gates.
Index Terms: BT Decoder, Current Source, Full swing GDI, Differential
Nonlinearity, Integral Nonlinearity and Power consumption.
Cite this Article: Kolli Ramesh and Mr. A. Ashok Kumar. Design of 8-Bit
Current Steering Digital To Analog Converter Using Full Swing GDI Logic,
International Journal of Electronics and Communication Engineering &
Technology, 6(9), 2015, pp. 97-106.
http://www.iaeme.com/IJECET/issues.asp?JType=IJECET&VType=6&IType=
9

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1. INTRODUCTION
In recent years, the current steering converter is the dominant construction for very
high speed Digital to Analog Converters (DAC). The current steering DAC has the
advantages of being quite small for resolution below 10 bits, being very fast, and
being more cost effective. The current-steering architecture of a DAC (digital to
analog converter) [1] can directly connect a resistance load to the voltage at the output
stage, without a current amplifier. There is no capacitance in the circuit, and there is
no need to charge or discharge current while in action [2]. The major drawbacks are
its sensitivity to device mismatch, glitches and current source output impedance for
higher number of bits. A self-calibrated circuit can be designed to solve these
problems but the circuit will consume more power and require a large chip area.
Current steering digital to analog converters are suitable for high speed and high-
resolution design. In this commonly used current-steering architectures are
Thermometer, Binary weighted and segmented architectures.
Thermometer architecture [3] is also called unary weighted architecture, as it
only has a one-size current source. An N-bit thermometer DAC requires 2N−1
identical
current sources to generate 0–2N−1
voltage levels. When a switch turns on, the output
value increases by one LSB. The thermometer architecture of a current steering DAC
is monotonic, shows good linearity and reduces the magnitude of glitches as only one
transistor switches at a time. The unary-weighted DACs suffer from design
complexity, a large area and large power consumption. So, they are not appropriate
for high resolution DAC circuit design.
Binary weighted architecture [4], [5] is simple and requires less area and less
power consumption, as it can directly use the binary input code to control switching
the current sources, without the requirement of decoding logic [6]. The major
drawback of binary-weighted architecture is degraded performance due to glitches,
mainly at middle-code transitions and tough current source matching requirements.
For example, a 4-bit binary input code transfers 0111 into 1000, which uses too many
current sources at the same time and generates large amplitude glitches, which
generate more power consumption.
Segmented architecture [7] is a mixture of thermometer and binary-weighted
architecture. MSB blocks use thermometric fashion for better accuracy, and LSB
blocks use the binary-weighted scheme. Segmented architecture reduces the
complexity, area and power consumption of the converter. The LSB introduces small
amplitude glitches as white noise in the frequency domain [6]. Too many segmented
stages can increase the digital noise and worsen the performance [8].
The static performance of DACs such as DNL and INL must be considered, as
well as the dynamic performance of DACs such as SFDR.A DNL should be smaller
than 1 LSB, and the DAC converter should be kept monotonic. Every increase of the
digital input code increases the analog output value. The DNL is always smaller than
1 LSB if the INL is smaller than 0.5 LSB. An INL should be less than 0.5 LSB, which
ensures that the maximum linearity error is smaller than the maximum quantization
error [9]. Section-2 describes an overview of the DAC architecture. The simulation
results are presented in Section-3. Finally, conclusion presented in the section-4.

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2. DIGITAL TO ANALOG CONVERTER ARCHITECTURE
This circuit includes both BT (binary to Thermometric) modules called BT decoder
[10] and current source modules (which includes both current mirror and switch
circuit).The 8-bit DAC module contains two BT decoders, as shown in Fig.1.The first
BT decoder transfers A7–A4 to thermometric code, which controls the on/off of 64I0
and 16I0 current source. The second BT decoders transfer A3–A0 to thermometric
codes, which controls the on/off of 4I0 and I0 current source, respectively.
Figure 1 8-bit current-steering DAC Architecture.
Each bit of thermometric code controls a current source in the current source
module. All the current source cells are divided into four different unit groups, i.e. 1I0,
4I0, 16I0 and 64I0. Each group contains three cells. Therefore, the above two modules
constitute an 8-bit DAC. The analog signal is converted by current flowing directly
through the output resister. It can generate a voltage varying from 0 to 255 units,
which of equally spaced level output voltage. Fig. 1 shows the construction of an 8-bit
current-steering DAC.
2.1. BINARY TO THERMOMETRIC DECODER
Fig.2. shows the 8-bit binary to thermometer decoder. It consisted of four AND gate
and four OR gate.S0-S11 are the control signals for current source. The 8-bit DAC
decoder of differential mode required four AND gates and four OR gates only. The
Binary to Thermometric(BT) module uses to transform binary code (I7I6I5I4I3I2I1I0)2 to
4 thermometric codes(S11S10S9)thermometric,(S8S7S65)thermometric,(S5S4S3)thermometric and
(S2S1S0)thermometric as shown in Fig.2.

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The output current of the current sources controlled by (S11S10S9) thermometric is 4,
16, 64 times of the current sources controlled by (S8S7S65) thermometric, (S5S4S3)
thermometric, (S2S1S0) thermometric respectively. This DAC uses a BT decoder instead of
conversional decoding construction, which provides some advantages. The BT
decoder contains one AND gate and one OR gate. The advantages of the BT decoder
are a reduction of DAC circuit complexity, delay and power consumption
respectively. All these gates are implemented using CMOS logic. This requires six
transistors for each logic gate.
Figure 2 8-bit BT Decode.
The AND, OR gates are implemented using Gate Diffusion Input (GDI) logic
[11, 12] to reduce number of transistors and area. The basic GDI cell consists of two
transistors as shown in Fig.3. Which implements different Boolean functions as listed
in Table I.
Figure 3 GDI cell.

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Table I Boolean Function Synthesis through Input Configuration of a Simple GDI Cell
N P G OUTPUT FUNCTION
0 B A ĀB F1
B 1 A +B F2
1 B A A+B OR
B 0 A AB AND
C B A B+AC MUX
0 1 A NOT
The drawbacks of GDI logic gates are overcomes by introducing Full Swing
(FS) GDI Logic gate, which are shown in Fig.4 and Fig.5.
Figure 4 Full Swing GDI AND gate.
Figure 5 Full Swing GDI OR gate

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2.2. CURRENT SOURCE MODULE
The current source in the proposed DAC is shown in Fig.6. MOS p1 operates in a
saturation region and controls the value of the current in each current source. The
current of each current source can be adjusted by changing the width of MOS p1. The
bias voltages Vin and Vin1 are also adjusted such that MOSFETs p1, p2 and p3 are
operate in the saturation region. MOSFET p3 is used to increase the output
impedance. The high output impedance can improve the performance of INL and
SFDR.
Figure 6 Current source module.
The goal of MOSFETs sw0 and sw1 are switches. The gate signal of sw0 is
connected from the BA decoder output, i.e. thermometric code (S2S1S0). As Si = 1,
where 0≤ i≤2, MOS sw0 turns on the switch and MOS sw1 turns it off. The current
sources that are turned on generate current flows through the output resistor Rout0 to
generate an analog output from the DAC. As MOS sw1 turns on, MOS sw0 turns off,
and the current flows through the output resistor Rout1 to generate an inverse signal,
this is for a single current source module. The 8-bit DAC (in Fig.7) requires 12
current sources and all the currents from each current sources are added at the output
stage. The output voltage and currents are given by
Vout = Iout * Rout
Iout = [(B1∨B0)+(B1)+(B1∧B0)](1unit)
+[(B3∨B2)+(B3)+(B3∧B2)](4Iunit)
+[(B5∨B4)+(B5)+(B5∧B4)](16Iunit)
+[(B7∨B6)+(B7)+(B7∧B6)](64Iunit).
Here, Vout is analog output voltage, Iout is total current drawn by all current
sources and Rout is output resistance. This DAC output can generate a differential
analog output signal.

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3. SIMULATION RESULTS
Fig.7. shows the 8-bit DAC, which consists of current source modules of different
weights. The digital input bits B0 and B1 are drives the first three current source of
having same weight and gives a current I0.The current sources driven by inputs
B2B3, B4B5, B6B7 are having weights 4, 16, 64 times of the current sources driven
by B0B1 respectively.
Figure 7 Schematic of 8-bit DAC using FS-GDI logic.

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The layout and output waveforms of the above 8-bit DAC shown in Fig.8 and
Fig.9 respectively. The full scale voltage of the DAC divided into equal parts and
output is a staircase wave which rises one step in output to corresponding to one bit
increment in input.
The output analog values corresponding to digital inputs 00000000, 01000000,
10000000, 11111111 are shown in fig.9. The proposed 8-bit DAC was implemented
using Mentor Graphics CMOS 0.13nm 1P2M technology with supply voltage 3.3V at
sample rate 200MHz. The maximum power consumption of the 8-bit DAC is
16.823mW. Differential nonlinearity (DNL) is the deviation of the actual step size at
each input code from the ideal 1LSB step. DNL errors can result in additive noise and
spurs beyond quantization effects. Integral nonlinearity (INL) is the deviation of the
actual output voltage from the ideal output voltage on a straight line drawn between
the end points of the transfer function. INL is calculated after offset and gain errors
are removed. The DNL and INL of the proposed DAC were ±0.01 LSB and
0.001LSB, respectively.
Figure 8 Layout of 8-bit DAC using FS-GDI logic
Figure 9 Output waveforms of 8-bit DAC using FS-GDI logic.

9. Design of 8-Bit Current Steering Digital To Analog Converter Using Full Swing GDI Logic
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Table II Comparison of Different DACs
PARAMETERS
EXISTING
MODEL
DAC WITH
GDI LOGIC
DAC WITH FS-
GDI LOGIC
Resolution 8-bit 8-bit 8-bit
Supply voltage 3.3V 3.3V 3.3V
Sample Rate 100MHz 200MHz 200MHz
DNL +0.32/-0.2LSB +0.21/-0.13LSB +0.1/-0.121LSB
INL +0.30/-0.01LSB +0.27/-0.01LSB +0.13/0.01LSB
Power Dissipation 53.71mW 16.850mW 16.823mW
Full Scale Voltage 255mV 255mV 255mV
Resistor Value 50ohm 50ohm 50ohm
Area 0.016mm2
0.00420mm2
0.00447mm2
Transistor count 152 100 124
Technology 130nm 130nm 130nm
4. CONCLUSION
In this paper, the 8-bit current-steering DAC was implemented using Full Swing GDI
logic in CMOS process to reduce the area and power dissipation. This designed digital
to analog converter successfully operates at 200MHz with 3.3V supply voltage. A
power consumption of 16.823mV, DNL and INL below 0.121LSB and 0.13LSB
respectively are achieved. The active area of the 8-bit DAC is 0.00447mm2
. This
DAC presented better performance when compared with existing designs regarding
the parameters DNL, INL and power consumption. This design is suitable for low-
power and high speed applications.
REFERENCES
[1] Yi S-C. An 8-bit current-steering digital to analog converter, AEU–Int J
Electron Commun 2012; 66: 433–7.
[2] Razavi B. Principle of data conversion system design. IEEE Press; 1994.
[3] Van der Plas GAM, Vandenbussche J, Sansen W, Steyaert MSJ, Gielen
GGE. “ 14-bit intrinsic accuracy Q2 random walk CMOS DAC". IEEE
Journal of Solid-State Circuits 2000; 34 (December (12)):1708–18.
[4] Deveugle J, Steyaert MSJ, A 10-bit 250-MS/s binary- weighted current
steering DAC, IEEE Journal of Solid-State Circuits 2006;41 February
(2)):320–9.
[5] Jurgen Deveugele, Steyaert MSJ. A 10-bit 250M-MS/s binary-weighted
current steering DAC.IEEE J Solid-State Circuits 2006; 41(February
(2)):320–9.
[6] John Wilson and S. Sakthivel. Big Bang-Big Crunch Algorithm For
Minimizing Power Consumption by Embedded Systems, International

10. Kolli Ramesh and Mr. A. Ashok Kumar
http://www.iaeme.com/IJECET/index.asp 106 editor@iaeme.com
Journal of Electronics and Communication Engineering & Technology,
5(7), 2014, pp. 9-14.
[7] Van den Bosch A, Borremans MAF, Steyaert MSJ, S Sansen W. A 10-bit
1G Sample/s Nyquist current-steering CMOS D/A converter. IEEE
Journal of Solid-StateCircuits 2001;36 (March (3)):315–24
[8] Chen W, Bauwelinck J, Ossieur P, Qiu X-Z, Vandewege J. A current-
steering DAC architecture with novel switching scheme for GPON burst-
mode laser drivers. IEICE Transactions on Electronics 2007; E90-C
(4):877–84.
[9] Eisa SM, Shehata KA, Ragai HF. Design and implementation of an 11-bit
nonlinear interpolation DAC. In: DTIS 2006, international conference on
design and test of integrated systems in nano-scale technology. September
2006. p. 136–9.
[10] V. Suresh Babu and M.R. Biju, Novel Circuit Realizations of Neuron
Activation Function and Its Derivative with Continuously Programmable
Characteristics and Low Power Consumption, International Journal of
Advanced Research in Engineering & Technology, 5(10), 2014, pp. 185-
200.
[11] Chena C-Y. Current-mode digital-to-analog converter designed in hybrid
architecture. International Journal of Electronics 2008; 95:361–9.
[12] Lee D H, Kuo T H, Wen K L. Low-cost 14-bit current-steering DAC with
a randomized thermometer-coding method. IEEE Trans Circuits Syst II:
Express Briefs, 2009, 56(2): 137.
[13] Vishwanath Muddi and Prof. Sanjay Eligar. A High-Speed, Low Power
Consumption D Flip-Flop For High Speed Phase Frequency Detector and
Frequency Divider, International Journal of Electronics and
Communication Engineering & Technology, 5(8), 2014, pp. 185 – 193.3.
[14] A. Morgenshtein, A. Fish, I.A. Wagner, Gate-diffusion input (GDI)-a
power efficient method for digital combinatorial circuits, IEEE
Transactions on VLSI Systems 10 (5) (2002).
[15] A. Morgenshtein, I. Shwartz, A. Fish, Gate diffusion input (GDI) logic in
standard CMOS nano-scale process, in: Proceedings of IEEE Convention
of Electrical and Electronics Engineers in Israel, 2010.