IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is an open access international journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Design of a 45nm TIQ Comparator for High Speed and Low Power 4-Bit Flash ADCIDES Editor
The continued speed improvement of serial links
and appearance of new communication technologies, such as
ultra-wideband (UWB), have introduced increasing demands
on the speed and power specifications of high-speed low-tomedium
resolution analog-to-digital converters (ADCs).This
paper presents the design of high speed and ultra low power
comparator of a 4-bit ADC. The comparator used is Threshold
Inverter Quantization (TIQ) consuming less than 145μW power
with the input frequency of 1GHz and is designed using
standard CMOS (Complementary Metal Oxide
Semiconductor) technology. The power supply voltage is 0.7V
minimum which makes this design adaptable to wide variety
of System-on-Chip (SoC) applications. The complete design of
ADC is clockless which reduces the electromagnetic
interference and gives better modularity. The ADC is targeted
for 45nm as it was the mainstream CMOS technology, at the
beginning of this research. However, the circuit should be
portable to smaller feature size CMOS technologies with lower
supply voltages.
Design of Low Power High Speed 4-Bit TIQ Based CMOS Flash ADCAman JanGra
The analog-to-digital converter (ADC) is an essential part of systemon-
chip (SoC) products because it bridges the gap between the analog physical
world and the digital logical world. In the digital domain, low power and low
voltage requirements are becoming more important issues as the channel length
of MOSFET shrinks below 0.25 sub-micron values. SoC trends force ADCs to
be integrated on the chip with other digital circuits. These trends present new
challenges in ADC circuit design. This paper investigates high speed, low
power, and low voltage CMOS flash ADCs for SoC applications.
Analog-to-Digital Converter (ADC) is an integral part of high-speed signal processing applications. This paper discusses about 10-bit SAR based ADC that enables very low power consumption and sampling rate as high as 165 MSPS.
VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicro...VLSICS Design
Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for costeffective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs). Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Since the ADC has a continuous, infinite –valued signal as its input, the important analog points on the transfer curve x-axis for an ADC are the ones that corresponding to changes in the digital output word. These input transitions determine the amount of INL and DNL associated with the converter. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing process and improved the resolution and design specially power consumption . The paper presents a design of 4 bit Pipeline ADC with low power dissipation mplemented in <0.18µm.
Nexgen Technology Address:
Nexgen Technology
No :66,4th cross,Venkata nagar,
Near SBI ATM,
Puducherry.
Email Id: praveen@nexgenproject.com.
www.nexgenproject.com
Mobile: 9751442511,9791938249
Telephone: 0413-2211159.
NEXGEN TECHNOLOGY as an efficient Software Training Center located at Pondicherry with IT Training on IEEE Projects in Android,IEEE IT B.Tech Student Projects, Android Projects Training with Placements Pondicherry, IEEE projects in pondicherry, final IEEE Projects in Pondicherry , MCA, BTech, BCA Projects in Pondicherry, Bulk IEEE PROJECTS IN Pondicherry.So far we have reached almost all engineering colleges located in Pondicherry and around 90km
Design of a 45nm TIQ Comparator for High Speed and Low Power 4-Bit Flash ADCIDES Editor
The continued speed improvement of serial links
and appearance of new communication technologies, such as
ultra-wideband (UWB), have introduced increasing demands
on the speed and power specifications of high-speed low-tomedium
resolution analog-to-digital converters (ADCs).This
paper presents the design of high speed and ultra low power
comparator of a 4-bit ADC. The comparator used is Threshold
Inverter Quantization (TIQ) consuming less than 145μW power
with the input frequency of 1GHz and is designed using
standard CMOS (Complementary Metal Oxide
Semiconductor) technology. The power supply voltage is 0.7V
minimum which makes this design adaptable to wide variety
of System-on-Chip (SoC) applications. The complete design of
ADC is clockless which reduces the electromagnetic
interference and gives better modularity. The ADC is targeted
for 45nm as it was the mainstream CMOS technology, at the
beginning of this research. However, the circuit should be
portable to smaller feature size CMOS technologies with lower
supply voltages.
Design of Low Power High Speed 4-Bit TIQ Based CMOS Flash ADCAman JanGra
The analog-to-digital converter (ADC) is an essential part of systemon-
chip (SoC) products because it bridges the gap between the analog physical
world and the digital logical world. In the digital domain, low power and low
voltage requirements are becoming more important issues as the channel length
of MOSFET shrinks below 0.25 sub-micron values. SoC trends force ADCs to
be integrated on the chip with other digital circuits. These trends present new
challenges in ADC circuit design. This paper investigates high speed, low
power, and low voltage CMOS flash ADCs for SoC applications.
Analog-to-Digital Converter (ADC) is an integral part of high-speed signal processing applications. This paper discusses about 10-bit SAR based ADC that enables very low power consumption and sampling rate as high as 165 MSPS.
VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicro...VLSICS Design
Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for costeffective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs). Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Since the ADC has a continuous, infinite –valued signal as its input, the important analog points on the transfer curve x-axis for an ADC are the ones that corresponding to changes in the digital output word. These input transitions determine the amount of INL and DNL associated with the converter. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing process and improved the resolution and design specially power consumption . The paper presents a design of 4 bit Pipeline ADC with low power dissipation mplemented in <0.18µm.
Nexgen Technology Address:
Nexgen Technology
No :66,4th cross,Venkata nagar,
Near SBI ATM,
Puducherry.
Email Id: praveen@nexgenproject.com.
www.nexgenproject.com
Mobile: 9751442511,9791938249
Telephone: 0413-2211159.
NEXGEN TECHNOLOGY as an efficient Software Training Center located at Pondicherry with IT Training on IEEE Projects in Android,IEEE IT B.Tech Student Projects, Android Projects Training with Placements Pondicherry, IEEE projects in pondicherry, final IEEE Projects in Pondicherry , MCA, BTech, BCA Projects in Pondicherry, Bulk IEEE PROJECTS IN Pondicherry.So far we have reached almost all engineering colleges located in Pondicherry and around 90km
Nexgen Technology Address:
Nexgen Technology
No :66,4th cross,Venkata nagar,
Near SBI ATM,
Puducherry.
Email Id: praveen@nexgenproject.com.
www.nexgenproject.com
Mobile: 9751442511,9791938249
Telephone: 0413-2211159.
NEXGEN TECHNOLOGY as an efficient Software Training Center located at Pondicherry with IT Training on IEEE Projects in Android,IEEE IT B.Tech Student Projects, Android Projects Training with Placements Pondicherry, IEEE projects in pondicherry, final IEEE Projects in Pondicherry , MCA, BTech, BCA Projects in Pondicherry, Bulk IEEE PROJECTS IN Pondicherry.So far we have reached almost all engineering colleges located in Pondicherry and around 90km
Nexgen Technology Address:
Nexgen Technology
No :66,4th cross,Venkata nagar,
Near SBI ATM,
Puducherry.
Email Id: praveen@nexgenproject.com.
www.nexgenproject.com
Mobile: 9751442511,9791938249
Telephone: 0413-2211159.
NEXGEN TECHNOLOGY as an efficient Software Training Center located at Pondicherry with IT Training on IEEE Projects in Android,IEEE IT B.Tech Student Projects, Android Projects Training with Placements Pondicherry, IEEE projects in pondicherry, final IEEE Projects in Pondicherry , MCA, BTech, BCA Projects in Pondicherry, Bulk IEEE PROJECTS IN Pondicherry.So far we have reached almost all engineering colleges located in Pondicherry and around 90km
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Vlsi IEEE 2014 titles 2014_2015_CSE/IT/ECE/EEE/ STUDENTS IN CHENNAI (S3 INFO...S3 Infotech IEEE Projects
DOTNET/JAVA/MATLAB/VLSI/NS2/EMBEDDED IEEE 2014 PROJECTS FOR ME/BE/B.TECH STUDENTS. FINAL YEAR 2014 PROJECTS FOR CSE/IT/ECE/EEE/ STUDENTS IN CHENNAI (S3 INFOTECH : 09884848198).
Final year IEEE 2014 projects for BE, BTech, ME, MTech &PHD Students (09884848198 : S3 Infotech)
Dear Students,
Greetings from S3 INFOTECH (0988 48 48 198). We are doing Final year (IEEE & APPLICATION) projects in DOTNET, JAVA, MATLAB, ANDROID, VLSI, NS2, EMBEDDED SYSTEMS and POWER ELECTRONICS.
For B.E, M.E, B.Tech, M.Tech, MCA, M.Sc, & PHD Students.
We implement your own IEEE concepts also in ALL Technologies. We are giving support for Journal Arrangement & Publication also.
Send your IEEE base paper to yes3info@gmail.com (or) info@s3computers.com.
To Register your project: www.s3computers.com
We are providing Projects in
• DOT NET
• JAVA / J2EE / J2ME
• EMBEDDED & POWER ELECTRONICS
• MATLAB
• NS2
• VLSI
• NETWORKING
• HADOOP / Bigdata
• Android
• PHP
DESIGN OF LOW POWER SAR ADC FOR ECG USING 45nm CMOS TECHNOLOGYVLSICS Design
Design of a low power Successive Approximation Register Analog to Digital Converter (SAR ADC) in
45nm CMOS Technology for biopotential acquisition systems is presented. It is designed by using a high
threshold voltage (Vt) cell to reduce power dissipation. A 10-bit SAR ADC is designed and compared with
the low resolution SAR ADC and normal threshold voltage (Vt) ADC with respect to power and delay. The
results show that high Vt SAR ADC saves power upto 67% as compared to low Vt SAR ADC without any
penalty of delay. Other performance metrics studied are the Effective Number of Bits (ENOB) and Signal to
Noise Ratio (SNR), Signal to Noise and Distortion Ratio and Spurious Free Dynamic ratio.
JESD204B Survival Guide: Practical JESD204B Technical Information, Tips, and ...Analog Devices, Inc.
Free downloadable PDF book for analog and FPGA designers. The guide provides an introduction to JESD204B – the new data converter interface standard – and explains why JESD204B is important, how it is used with high-speed A/D and D/A converters as well as providing trouble shooting tips and how-to articles. By Analog Devices, Inc.
by Analog Devices, Inc. - the World’s Data Converter Market Share Leader
CPU Subsystem Total Power Consumption: Understanding the Factors and Selectin...CAST, Inc.
Power consumption figures for a processor core only tell part of the energy usage story for a CPU subsystem.
Smart IP choices regarding performance, instruction set architecture, required memory operations and size, and other factors can also significantly reduce the real-world total power required for such subsystems. Learn how to better assess these factors through practical comparisons with processor cores supporting the BA2 ISA, which offer both extreme code density and excellent performance (see http://www.cast-inc.com/ba22).
Register for this free webinar:
Dec 13 at 10am Pacific Standard Time (PST) — 1pm USA Eastern, 10am USA Pacific
https://attendee.gotowebinar.com/rt/6662961646095173120
International Journal of Computational Engineering Research (IJCER) ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology
Gate Diffusion Input Technology (Very Large Scale Integration)Ashwin Shroff
The aim of project is by using GDI technique the power consumption, delay, chip area and connection and parasitic capacitors is decreased. In this project, we are implementing the new T-flip flop using GDI technique for low power and high speed in order to achieve power delay product (PDP)
-Study of the functionality of 2MB mother board, providing E1 data interfaces
-CMS LAB,TEST EQUIPMENT, QUALITY CONTROL. - ABOUT BEL,ROTATIONAL PROGRAM.-FPGA,ADSP,DSO,VHDL.
-E1 EUROPEAN DATA FORMAT , LINK, SPECIFICATION
ENCODING TECHNIQUES- HDB3, AMI
Comparative Performance of Crude Pongamia Oil in A Low Heat Rejection Diesel ...IOSR Journals
Experiments were carried out to evaluate the performance of a low heat rejection (LHR) diesel engine with ceramic coated cylinder head [ceramic coating of thickness 500 microns was done on inside portion of cylinder head] with different operating conditions [normal temperature and pre-heated temperature] of crude Pongamia oil with varied injection pressure and injection timing.
Study Design: Performance parameters of brake thermal efficiency, exhaust gas temperature and volumetric efficiency were determined at various values of brake mean effective pressure (BMEP). Methodology: Exhaust emissions of smoke and oxides of nitrogen (NOx) were noted at the various values of BMEP. Combustion characteristics at peak load operation of the engine were measured with TDC (top dead centre) encoder, pressure transducer, console and special pressure-crank angle software package. Brief Results: Conventional engine (CE) showed deteriorated performance, while LHR engine showed improved performance with biodiesel operation at manufacturer’s recommended injection timing of 27obTDC and pressure of 190 bar. The performance of both version of the engine was improved with advanced injection timing and at higher injection pressure when compared with CE with pure diesel operation. The optimum injection timing was 32obTDC for CE, while it was 29obTDC for LHR engine with CPO operation. Peak brake thermal efficiency increased by 7%, smoke levels timing, when compared with pure diesel operation on CE at manufacturer’s recommended injection timing.
A Hypocoloring Model for Batch Scheduling ProblemIOSR Journals
In this paper we define Scheduling, Batch Scheduling, Coloring, Subcoloring, Hypocoloring, Chromatic number, Subchromatic number, and Hypochromatic number for a given graph. A batch Scheduling problem has been obtained by using the above discussed concepts.An exponential algorithm has been developed for triangle free graphs. The solution is obtained by introducing COCA - ‘Contract or Connect” Principle. The Subchromatic and Hypochromatic number for shell graphs has been illustrated. A Hypocoloring model for personnel assignment problem has been briefly discussed.
FPGA Based Implementation of Electronic Safe LockIOSR Journals
Thispaper is based on design of an “Automatic Security System Using VHDL” providing
understandable and adequate operating procedure to the user. The operation is conducted by six different
modules. If any of the modules fails, the failed module can be replaced without affecting the activity of others.
The safety is ensured to the user by setting a secret code number which is the combination of three numbers, by
doing so, only the authorized users can unlock the safe. The paper finds its appositeness in big organizations,
military and banking sectors. Simulation through VHDL is quite generous and fiscal due to the reduction in
number of components. Important operation consideration is to not give any indication to the user that the
combination entered is incorrect until after the user has entered the all three numbers and pressed the OPEN
key. Otherwise, it is possible for a user to determine the combination in no more than 96 attempts, as opposed to
no more than 32,768 attempts
Characterizing Erythrophleum Suaveolens Charcoal as a Viable Alternative Fuel...IOSR Journals
An experimental study was conducted to characterize erythrophleum suaveolens (Gwaska) charcoal. The test was conducted for proximate analysis (involving the determination of moisture content, ash, volatile matter and fixed carbon) and ultimate analysis (involving the determination of carbon, hydrogen, oxygen, nitrogen sulphur and calorific value) of erythrophleum suaveolens charcoal. The determined values of moisture, ash, volatile matter and fixed carbon were 0.94%, 6.13%, 6.77% and 86.16% respectively. Also the determined values of carbon, hydrogen, oxygen, nitrogen, sulphur and calorific value were 77.5%, 9%, 5.48%, 1.89%, 0.003% and 7158.6995 Kcal/Kg respectively. Therefore, the gwaska charcoal satisfies the blast furnace requirements for moisture, ash and sulphur in Nigeria. However, its volatile matter exceeds the specified limit except for Indian standard practice. The erythrophleum suaveolens charcoal’s thermal properties showed that it could compete favourably with coke and therefore can be an excellent reducing fuel for the production of iron.
Nexgen Technology Address:
Nexgen Technology
No :66,4th cross,Venkata nagar,
Near SBI ATM,
Puducherry.
Email Id: praveen@nexgenproject.com.
www.nexgenproject.com
Mobile: 9751442511,9791938249
Telephone: 0413-2211159.
NEXGEN TECHNOLOGY as an efficient Software Training Center located at Pondicherry with IT Training on IEEE Projects in Android,IEEE IT B.Tech Student Projects, Android Projects Training with Placements Pondicherry, IEEE projects in pondicherry, final IEEE Projects in Pondicherry , MCA, BTech, BCA Projects in Pondicherry, Bulk IEEE PROJECTS IN Pondicherry.So far we have reached almost all engineering colleges located in Pondicherry and around 90km
Nexgen Technology Address:
Nexgen Technology
No :66,4th cross,Venkata nagar,
Near SBI ATM,
Puducherry.
Email Id: praveen@nexgenproject.com.
www.nexgenproject.com
Mobile: 9751442511,9791938249
Telephone: 0413-2211159.
NEXGEN TECHNOLOGY as an efficient Software Training Center located at Pondicherry with IT Training on IEEE Projects in Android,IEEE IT B.Tech Student Projects, Android Projects Training with Placements Pondicherry, IEEE projects in pondicherry, final IEEE Projects in Pondicherry , MCA, BTech, BCA Projects in Pondicherry, Bulk IEEE PROJECTS IN Pondicherry.So far we have reached almost all engineering colleges located in Pondicherry and around 90km
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Vlsi IEEE 2014 titles 2014_2015_CSE/IT/ECE/EEE/ STUDENTS IN CHENNAI (S3 INFO...S3 Infotech IEEE Projects
DOTNET/JAVA/MATLAB/VLSI/NS2/EMBEDDED IEEE 2014 PROJECTS FOR ME/BE/B.TECH STUDENTS. FINAL YEAR 2014 PROJECTS FOR CSE/IT/ECE/EEE/ STUDENTS IN CHENNAI (S3 INFOTECH : 09884848198).
Final year IEEE 2014 projects for BE, BTech, ME, MTech &PHD Students (09884848198 : S3 Infotech)
Dear Students,
Greetings from S3 INFOTECH (0988 48 48 198). We are doing Final year (IEEE & APPLICATION) projects in DOTNET, JAVA, MATLAB, ANDROID, VLSI, NS2, EMBEDDED SYSTEMS and POWER ELECTRONICS.
For B.E, M.E, B.Tech, M.Tech, MCA, M.Sc, & PHD Students.
We implement your own IEEE concepts also in ALL Technologies. We are giving support for Journal Arrangement & Publication also.
Send your IEEE base paper to yes3info@gmail.com (or) info@s3computers.com.
To Register your project: www.s3computers.com
We are providing Projects in
• DOT NET
• JAVA / J2EE / J2ME
• EMBEDDED & POWER ELECTRONICS
• MATLAB
• NS2
• VLSI
• NETWORKING
• HADOOP / Bigdata
• Android
• PHP
DESIGN OF LOW POWER SAR ADC FOR ECG USING 45nm CMOS TECHNOLOGYVLSICS Design
Design of a low power Successive Approximation Register Analog to Digital Converter (SAR ADC) in
45nm CMOS Technology for biopotential acquisition systems is presented. It is designed by using a high
threshold voltage (Vt) cell to reduce power dissipation. A 10-bit SAR ADC is designed and compared with
the low resolution SAR ADC and normal threshold voltage (Vt) ADC with respect to power and delay. The
results show that high Vt SAR ADC saves power upto 67% as compared to low Vt SAR ADC without any
penalty of delay. Other performance metrics studied are the Effective Number of Bits (ENOB) and Signal to
Noise Ratio (SNR), Signal to Noise and Distortion Ratio and Spurious Free Dynamic ratio.
JESD204B Survival Guide: Practical JESD204B Technical Information, Tips, and ...Analog Devices, Inc.
Free downloadable PDF book for analog and FPGA designers. The guide provides an introduction to JESD204B – the new data converter interface standard – and explains why JESD204B is important, how it is used with high-speed A/D and D/A converters as well as providing trouble shooting tips and how-to articles. By Analog Devices, Inc.
by Analog Devices, Inc. - the World’s Data Converter Market Share Leader
CPU Subsystem Total Power Consumption: Understanding the Factors and Selectin...CAST, Inc.
Power consumption figures for a processor core only tell part of the energy usage story for a CPU subsystem.
Smart IP choices regarding performance, instruction set architecture, required memory operations and size, and other factors can also significantly reduce the real-world total power required for such subsystems. Learn how to better assess these factors through practical comparisons with processor cores supporting the BA2 ISA, which offer both extreme code density and excellent performance (see http://www.cast-inc.com/ba22).
Register for this free webinar:
Dec 13 at 10am Pacific Standard Time (PST) — 1pm USA Eastern, 10am USA Pacific
https://attendee.gotowebinar.com/rt/6662961646095173120
International Journal of Computational Engineering Research (IJCER) ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology
Gate Diffusion Input Technology (Very Large Scale Integration)Ashwin Shroff
The aim of project is by using GDI technique the power consumption, delay, chip area and connection and parasitic capacitors is decreased. In this project, we are implementing the new T-flip flop using GDI technique for low power and high speed in order to achieve power delay product (PDP)
-Study of the functionality of 2MB mother board, providing E1 data interfaces
-CMS LAB,TEST EQUIPMENT, QUALITY CONTROL. - ABOUT BEL,ROTATIONAL PROGRAM.-FPGA,ADSP,DSO,VHDL.
-E1 EUROPEAN DATA FORMAT , LINK, SPECIFICATION
ENCODING TECHNIQUES- HDB3, AMI
Comparative Performance of Crude Pongamia Oil in A Low Heat Rejection Diesel ...IOSR Journals
Experiments were carried out to evaluate the performance of a low heat rejection (LHR) diesel engine with ceramic coated cylinder head [ceramic coating of thickness 500 microns was done on inside portion of cylinder head] with different operating conditions [normal temperature and pre-heated temperature] of crude Pongamia oil with varied injection pressure and injection timing.
Study Design: Performance parameters of brake thermal efficiency, exhaust gas temperature and volumetric efficiency were determined at various values of brake mean effective pressure (BMEP). Methodology: Exhaust emissions of smoke and oxides of nitrogen (NOx) were noted at the various values of BMEP. Combustion characteristics at peak load operation of the engine were measured with TDC (top dead centre) encoder, pressure transducer, console and special pressure-crank angle software package. Brief Results: Conventional engine (CE) showed deteriorated performance, while LHR engine showed improved performance with biodiesel operation at manufacturer’s recommended injection timing of 27obTDC and pressure of 190 bar. The performance of both version of the engine was improved with advanced injection timing and at higher injection pressure when compared with CE with pure diesel operation. The optimum injection timing was 32obTDC for CE, while it was 29obTDC for LHR engine with CPO operation. Peak brake thermal efficiency increased by 7%, smoke levels timing, when compared with pure diesel operation on CE at manufacturer’s recommended injection timing.
A Hypocoloring Model for Batch Scheduling ProblemIOSR Journals
In this paper we define Scheduling, Batch Scheduling, Coloring, Subcoloring, Hypocoloring, Chromatic number, Subchromatic number, and Hypochromatic number for a given graph. A batch Scheduling problem has been obtained by using the above discussed concepts.An exponential algorithm has been developed for triangle free graphs. The solution is obtained by introducing COCA - ‘Contract or Connect” Principle. The Subchromatic and Hypochromatic number for shell graphs has been illustrated. A Hypocoloring model for personnel assignment problem has been briefly discussed.
FPGA Based Implementation of Electronic Safe LockIOSR Journals
Thispaper is based on design of an “Automatic Security System Using VHDL” providing
understandable and adequate operating procedure to the user. The operation is conducted by six different
modules. If any of the modules fails, the failed module can be replaced without affecting the activity of others.
The safety is ensured to the user by setting a secret code number which is the combination of three numbers, by
doing so, only the authorized users can unlock the safe. The paper finds its appositeness in big organizations,
military and banking sectors. Simulation through VHDL is quite generous and fiscal due to the reduction in
number of components. Important operation consideration is to not give any indication to the user that the
combination entered is incorrect until after the user has entered the all three numbers and pressed the OPEN
key. Otherwise, it is possible for a user to determine the combination in no more than 96 attempts, as opposed to
no more than 32,768 attempts
Characterizing Erythrophleum Suaveolens Charcoal as a Viable Alternative Fuel...IOSR Journals
An experimental study was conducted to characterize erythrophleum suaveolens (Gwaska) charcoal. The test was conducted for proximate analysis (involving the determination of moisture content, ash, volatile matter and fixed carbon) and ultimate analysis (involving the determination of carbon, hydrogen, oxygen, nitrogen sulphur and calorific value) of erythrophleum suaveolens charcoal. The determined values of moisture, ash, volatile matter and fixed carbon were 0.94%, 6.13%, 6.77% and 86.16% respectively. Also the determined values of carbon, hydrogen, oxygen, nitrogen, sulphur and calorific value were 77.5%, 9%, 5.48%, 1.89%, 0.003% and 7158.6995 Kcal/Kg respectively. Therefore, the gwaska charcoal satisfies the blast furnace requirements for moisture, ash and sulphur in Nigeria. However, its volatile matter exceeds the specified limit except for Indian standard practice. The erythrophleum suaveolens charcoal’s thermal properties showed that it could compete favourably with coke and therefore can be an excellent reducing fuel for the production of iron.
Enhance the Throughput of Wireless Network Using Multicast RoutingIOSR Journals
Wireless Mesh Network is designed static or limited mobility environment .In multicast routing for
wireless mesh networks has focused on metrics that estimate link quality to maximize throughput
andtoprovide secure communication. Nodes must collaborate in order to compute the path metric and
forward data.Node identify the novel attacks against high- throughput multicast protocols in wireless
mesh network.. The attacks exploit the local estimation and global aggregation of the metric to allow
attackers to attract a large amount of traffic These attacks are very effective b a s e d on high
throughput metrics. The aggressive path selection is a double-edged sword: It is maximizes throughput,
it also increases attack effectiveness. so Rate guard mechanism will be used.Rate guard mechanism
means combines Measurement-based detection and accusation-based reaction techniques.The attacks
and the defense using ODMRP, a representative multicast protocol for wireless mesh networks, and
SPP, an adaptation of the well-known ETX unicast metric to the multicast setting
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is an open access international journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Ultimate Behavior of Lightweight High Strength Concrete Filled Steel Tube (LW...IOSR Journals
Strength and ductility of concrete members can be significantly improved with lateral confinement, usually achieved by using a steel tube casing. The concrete confinement can be utilized to make bridge lighter and have longer spans. In addition, a significant portion of the load carried concrete bridge girders is the self-weight of the girders and deck. If all or part of the girder and deck can be made using high strength lightweight concretes, there is a potential for appreciable economic savings since the self-weight could be reduced by as much as 15-20%. The study described herein investigates the static nonlinear behavior of lightweight high strength concrete filled steel tube (LWHCFST) bridges up to failure. The current study had two specific goals. The first was to experimentally determine the static modulus of elasticity of confined high strength lightweight concrete mixture. The second was to develop a nonlinear finite element computer program to study the ultimate behavior of a filled tube (LWHCFST) example bridge. The nonlinear stress-strain behavior of confined high strength lightweight concrete is evaluated experimentally by the authors and is used to help establish a comparison between the ultimate behavior of the bridge using confined normal weight concrete and confined high strength lightweight concrete. The ultimate strength of the bridge is related to the occurrence of an equivalent failure mechanism. The study indicated that the use of (LWHCFST) is beneficial for extending bridge girder lengths
IOSR Journal of Applied Physics (IOSR-JAP) is an open access international journal that provides rapid publication (within a month) of articles in all areas of physics and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in applied physics. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
CFD Simulation and Analysis of Fluid Flow Parameters within a Y-Shaped Branch...IOSR Journals
Plumbing system use pipe fittings to connect straight pipe or tubing section for regulating or measuring fluid flow. Y (wye)-shape fitting is one of the important component in the plumbing system. A wye branch allows splitting a branch line equally in two directions. The opening sizes can vary for different situations for instance in situation where a large main line needs to be split into two smaller branches. The wye shape fitting will convert into T shape fitting when the included angle between two pipe branches is 180°. In the present work, effect of angle of turn/bend for a Y-shape pipe will be studied computationally using ANSYS CFX software. For the analysis, all the three pipe branches of 1 inch internal diameter are selected along with equal length so that only the effect of bend angle at 450, 600, 900 and 1800 can be studied. Water as a fluid is selected which flows through the plumbing system. The effect of bend angle, pipe diameter, pipe length, Reynolds number on the resistance coefficient is studied. It was observed that resistance coefficient vary with the change in flow
Levels of Physical Activity Participation of the Staff of Universiti SelangorIOSR Journals
Abstract: This study is carried out to identify the levels of the Universiti Selangor (Unisel) staff’s participation
in physical activities. It aims to investigate the stages of their physical activities to determine whether these
activities are beneficial to them or otherwise. This study is a descriptive survey research of which the data has
been collected via questionnaire from 231 employees of Unisel in Bestari Jaya Campus. Respondents are asked
questions about their physical activities based on the International Physical Activity Questionnaire (IPIQ). The
findings reveal that many members of the staff of the Universiti Selangor practice physical activities as their
way of life. However, the level of their participation in physical activities has not reached a satisfactory level.
The respondents often carry out physical activities, but mostly their participation is still considered within the
range of average to low level. The respondents’ participation in physical activities is influenced by their attitude
which seeks acknowledgment rather than practicing it as a healthy lifestyle. The findings shows that the
employees’ physical activity participation is very high. However, they do not carry out the activities according
to the principles of physical activity domain. This study concludes that there are still many Unisel staff members
that seldom treat physical activities as their everyday routines. The findings show that 106 of the respondents
carry out physical activities at a low level, 49 of the respondents at the medium level and 76 of the respondents
at a high level. The findings are insufficient to establish that the respondents have carried out the best physical
activity practice. The results conclude that these Unisel staff members still need to be guided and educated in
order to ensure that their participation in physical activities becomes a healthy lifestyle that is led by the whole
community.
Keywords: Employee, Low, Medium and High Level, Physical Activities
Investigation of Tribological Behavior of Stainless Steel 304 and Grey Cast I...IOSR Journals
The tribological behavior of stainless steel 304 and grey cast iron was investigated using the pinon-disc
standard test with varying sliding speeds and normal loads. A pin-on-disc device with round tool
inserts was used to conduct friction wear tests in which the linear wear of the tribo-pairs were continuously
recorded versus sliding distance. For the quantitative comparison of the wear resistance of the material was
tested by calculating the weight loss. Scanning electron microscopy (SEM) was applied for observations of
wear scars and wear products, and the identification of the predominant wear mechanisms which occurred.
Some specific frictional behaviors and relevant wear mechanisms observed for both steel 304 and cast iron
sliding were highlighted and quantified. It was concluded that with the increase in sliding speed and normal
load wear behavior shown by stainless steel 304 was more as it become soften with the increase in the load.
But the wear behavior shown by grey cast was low due to the presence of graphite
Effects of Learning by Video Modeling on Gymnastic Performances among Tunisia...IOSR Journals
Abstract: The purpose of this work was to analyze the effects of learning through video modeling combined of
sessions of physical education on gymnastic performance among Tunisian students in the second year of
secondary level. Our study was conducted on a sample of 103 subjects (16,95 0,9 years) divided into two
independent groups (experimental and control). The experimental group was subjected to a cycle of video
modeling with explanations and verbal representations of gymnastic skills combined with sessions of physical
education gymnastics, while the second group was practiced gymnastics with the usual conditions in the
physical education sessions. Measures of performances were taken before and after the experiment. These
results demonstrate the effectiveness of learning by video modeling procedures for the acquisition and
improvement of gymnastic skills for students. In addition, the progression of gymnastic performance of girls is
more important than boys after receiving the learning by video modeling.
Keywords: Learning; Video modeling; Performance; Gymnastics
Common Sports Injuries amongst the Elite Women Basketball Players of IndiaIOSR Journals
Abstract: An injury is a common phenomenon in the field of sports. Ranging from amateurs to the most
seasoned sports personalities, almost every one faces the brunt of an injury at some point in their sporting
careers. To gauge the effect and extent of these injuries, the members of the Indian women basketball team were
examined for common sports injuries. While they represent the country at various international tournaments
round the year, the results of the survey painted a very dismal picture.
The longevity of a sports person’s career depends critically on the severity of an injury. In some cases, severe
injuries have an intense impact immediately. While on the other hand, there are also instances when an injury is
ignored and remains untreated; this becomes worse and hinders the crucial functioning of a sports person on
the field. Irrespective of the case, it is essential that all such injuries be avoided at all levels of the sport for its
growth and development.
It is an endeavor by the research scholars to isolate the most common and frequently occurring injuries so that
the players, coaches, doctors and physiotherapists can concentrate and work on the preventive measures for
them. Key Words: Basketball, Prevention, Sports Injuries, Women
A 12-Bit High Speed Analog To Digital Convertor Using μp 8085IJERA Editor
The need constantly exists for converters with higher resolution, faster conversion speeds and lower power dissipation. High-speed analog to digital converters (ADC’s) have been based on flash architecture, because all comparators sample the analog input voltage simultaneously, this ADC is thus inherently fast. Unfortunately, flash ADC requires 2N - 1 comparators to convert N bit digital code from an analog sample. This makes flash ADC’s unsuitable for high-resolution applications. This paper demonstrates a simple technique to enhance resolution of flash ADC’s that require as few as 256 comparators for 12-bit conversion. In this approach, the analog input range is partitioned into 256 quantization cells, separated by 255 boundary points. An 8-bit binary code 00000000 to 11111111 is assigned to each cell. A 12-bit flash converter requires 4096 comparators, while proposed technique reduces number of comparator requirements to only 256 for 12- bit conversion. Therefore, this technique is best suitable when high speed combined with high resolution is required. Result of 12-bit prototype is presented.
Design and Implementation of Low Power 3-Bit Flash ADC Using 180nm CMOS Techn...IJERA Editor
Analog-to-digital converter has become a very important device in today’s digitized world as they have a very
wide variety of applications. Among all the ADC’s available, the Flash ADC is the fastest one but a main
disadvantage of Flash ADC is its power consumption. So, this paper aims at implementing a low power high
speed Flash ADC. A 3-bit Flash ADC has been designed using CMOS technology. A two stage open loop
comparator and a priority encoder have been implemented using which the ADC has been designed. All the
circuits are simulated using 180nm technology in Tanner EDA environment. The supply voltage Vdd is
1.8v.Analog output of each comparator depending upon the comparison between the input and the reference
voltage is fed to the encoder and finally the compressed digital output is obtained. The power dissipation of
each circuit implemented is calculated individually including other parameters like are, resolution gain and
speed.
DESIGN OF IMPROVED RESISTOR LESS 45NM SWITCHED INVERTER SCHEME (SIS) ANALOG T...VLSICS Design
This work presents three different approaches which eliminates the resistor ladder completely and hence
reduce the power demand drastically of a Analog to Digital Converter. The first approach is Switched
Inverter Scheme (SIS) ADC; The test result obtained for it on 45nm technology indicates an offset error of
0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of
0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 μwatts;
Power delay product (PDP) is 415.9 fWs, and the area is 1.89μm2. The second and third approaches are
clocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in power
dissipation as 57.5% & 71% respectively. Whereas PDP is 229.7 fWs and area is 0.05 μm2 for Clocked SIS
ADC and 107.3 fWs & 1.94 μm2 for Sleep transistor SIS ADC.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
DESIGN OF LOW POWER SAR ADC FOR ECG USING 45nm CMOS TECHNOLOGYVLSICS Design
Design of a low power Successive Approximation Register Analog to Digital Converter (SAR ADC) in 45nm CMOS Technology for biopotential acquisition systems is presented. It is designed by using a high threshold voltage (Vt) cell to reduce power dissipation. A 10-bit SAR ADC is designed and compared with the low resolution SAR ADC and normal threshold voltage (Vt) ADC with respect to power and delay. The results show that high Vt SAR ADC saves power upto 67% as compared to low Vt SAR ADC without any penalty of delay. Other performance metrics studied are the Effective Number of Bits (ENOB) and Signal to Noise Ratio (SNR), Signal to Noise and Distortion Ratio and Spurious Free Dynamic ratio.
Simulation of 3 bit Flash ADC in 0.18μmTechnology using NG SPICE Tool for Hig...ijsrd.com
This paper provides the basic simulation result for the 3 bit flash type ADC in 0.18μm technology using the NG Spice device simulator tool. It includes two stages, first stage includes 7 comparators and second stage has a thermometer encoder. The simulation is done in NG spice tool developed by university of California at Berkeley (USA).The response time of the comparator and ADC are 3.7ns and 4.9ns respectively with 50.01μw power dissipation which makes the ADC more suitable for high speed application with lower power devices.
A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTERVLSICS Design
In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented. CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, the switching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation results show that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sample/s with 3.3V supply voltage in TSMC 0.35 µm process. Compared with the traditional flash ADC, this proposed method can reduce about 78% in power consumption.
VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicro...VLSICS Design
Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for costeffective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs). Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Since the ADC has a continuous, infinite –valued signal as its input, the important analog points on the transfer curve x-axis for an ADC are the ones that corresponding to changes in the digital output word. These input transitions determine the amount of INL and DNL associated with the converter. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing process and improved the resolution and design specially power consumption . The paper presents a design of 4 bit Pipeline ADC with low power dissipation implemented in <0.18µm.
Cmos Full Adder and Multiplexer Based Encoder for Low Resolution Flash AdcIOSRJECE
The present investigation proposed a low power encoding scheme of thermometer code to binary code converter for flash analog to digital conversion by the design of different circuits. In this paper, we have proposed three encoding techniques for the conversion of analog to digital signal using Multiplexer based encoder, heterogeneous encoder and encoding technique using dynamic logic circuits providing low power of operation and we compare the results obtained from each technique based on power consumption. The multiplexer based encoder was designed with the help of multiplexers which consumes less amount of power comparing with other designs.
An approach to design Flash Analog to Digital Converter for High Speed and Lo...VLSICS Design
This paper proposes the Flash ADC design using Quantized Differential Comparator and fat tree encoder. This approach explores the use of a systematically incorporated input offset voltage in a differential amplifier for quantizing the reference voltages necessary for Flash ADC architectures, therefore eliminating the need for a passive resistor array for the purpose. This approach allows very small voltage comparison and complete elimination of resistor ladder circuit. The thermometer code-to-binary code encoder has become the bottleneck of the ultra-high speed flash ADCs. In this paper, the fat tree thermometer code to-binary code encoder is used for the ultra high speed flash ADCs. The simulation and the implementation results shows that the fat tree encoder performs the commonly used ROM encoder in terms of speed and power for the 6 bit CMOS flash ADC case. The speed is improved by almost a factor of 2 when using the fat tree encoder, which in fact demonstrates the fat tree encoder and it is an effective solution for the bottleneck problem in ultra-high speed ADCs.The design has been carried out for the 0.18um technology using CADENCE tool.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
An Optimal Design of UP-DOWN Counter as SAR Logic Based ADC using CMOS 45nm T...IJERA Editor
In this paper an analog to digital converter architecture is introduced. The proposed design is based on Up-Down counter approach SAR type ADC. This design offers less design complexity which leads to low power consumption. Based on the proposed idea, a 4-bit ADC is simulated in Microwind 3.5 environment using 45nm CMOS technology with supply voltage of 1 V. The ADC is designed with control signal like Start of conversion (SOC) and End of conversion (EOC). The ADC design consumes 3.2mW of power. The proposed ADC design is optimized to area of 829.6µm2.
A 8-bit high speed ADC using Intel μP 8085IJERD Editor
An 8-bit ADC Architecture of is proposed, it uses 16 comparators and produces 8-bit digital code in half the time as that of successive approximation technique. In this approach, the analog input range is partitioned into 16 quantization cells, separated by 15 boundary points. A 4-bit binary code 0000 to 1111 is assigned to each cell. The results show that the ADC exhibits a maximum DNL of 0.49LSB and a maximum INL of 0.51LSB.
1. IOSR Journal of Electronics and Communication Engineering (IOSR-JECE)
e-ISSN: 2278-2834,p- ISSN: 2278-8735. Volume 5, Issue 3 (Mar. - Apr. 2013), PP 42-48
www.iosrjournals.org
Low Power CMOS Data Converter with SNDR analysis for High
Speed System On Chip Applications
Ritam Dutta1, Krishanu Mitra2, Moumita Majumdar3
1
(Asst. Prof., ECE, Surendra Institute of Engg. & Management, WBUT, Siliguri, India)
2,3
(Asst. Engg., ECE, Surendra Institute of Engg. & Management, WBUT, Siliguri, India)
Abstract: In modern era of advanced VLSI design the transistor sizing and scaling has an considerable
impact. There are very essential two constrains, which needs serious attention to the VLSI chip designer are
high speed and low power consumption. Therefore in this paper an 8-bit 3 Gs/sec flash analog-to-digital data
converter (ADC) in 45nm CMOS technology is presented for low power and high speed system-on-chip (SoC)
applications. This low power 8-bit flash Analog to Digital data converter comprises 255 comparators and one
thermometer to binary encoder. This flash ADC design is an extended research work of the earlier work related
to ADC design using CMOS process technology. The schematic simulation of ADC is done in Tanner-Spice Pro
(S-Edit) and layout simulation is done in Tanner-Spice Pro (L-Edit) V.15.14. The Simulated result shows the
power consumption in Flash ADC is 41.78μw. The Threshold Inverter Quantization (TIQ) technique is proposed
to get WPMOS/WNMOS < 1 for transistors to keep the power consumption as low as possible. It is also
observed that the ADC consumes 41.78μW of peak power and 6.45μW of average power at full speed while it
operates on a power supply voltage of 0.6V. Compared with the earlier work, this project consumes less power
and high speed with proposed TIQ technique gives an edge in SoC based VLSI design. Finally the Signal to
Noise Distortion analysis is done to obtain more precise data conversion results. The SNDR was found 31.9dB
for ultimate precise data conversion using 45nm CMOS process technology.
Keywords: System-on-chip based design, flash ADC, Threshold Inverter Quantization technique, Modern VLSI
design, SNDR, CMOS process technology.
I. INTRODUCTION
At present scenario, analog to digital converters find applications in communications, high-definition
television set top boxes, video projectors, etc. ADCs are interfaced with digital circuits in mixed signal
integrated chips, where digital signal processing is performed. The supply voltage for digital devices is
decreasing rapidly as the technology scales. Analog to digital converters are required to be operating with these
devices, preferably at the same voltages. If the analog and digital components on a chip are not operating at the
same supply voltage, then level converters need to be incorporated. There are major two constrains of
VLSI/ASIC design. Firstly the circuit should be able to operate at as low voltage as possible, to minimize the
power consumption. Secondly the circuit design should be functional at nanometer feature sizes. At such low
feature sizes, large device integration is possible. The proposed design meets both criteria.
In this paper, we have successfully implemented a 8-bit low power flash ADC at 45nm CMOS
technology. The comparators in the flash ADC have been designed using the threshold inverter quantization
(TIQ) technique. While designing these comparators, many transistors have been sized such that
WPMOS/WNMOS < 1 in order to keep the power consumption as low as possible. The advantage of using
these TIQ based comparators over a conventional differential comparator is that a resistor ladder network is not
required for providing the reference voltages for the comparators and the comparison speed is faster. In addition,
process matching issues are eliminated. This makes the proposed ADC ideal for use in low power and high
speed SoCs.
II. RELATED EARLIER WORK
Some related earlier research works of designing flash ADC using CMOS technology are listed as
follows. The TIQ technique has been used to design a flash ADC [1]. The focus is on low voltage and high
speed design, with supply of 1.8V and a conversion rate of 1.3 Gs/sec [2]. A capacitive interpolation technique
is employed for a low power design which eliminates the need for a resistor ladder [3]. The next work presents
use of digital techniques instead of analog techniques to overcome comparator offset [4]. In 2002 an average
termination circuit is proposed [5] to reduce the number of over-range amplifiers, hence reducing the power
consumption. An ADC [6] is designed for disk-drive read-channel applications. The authors use a current
interpolating technique to design an ADC operating at 1V power supply [7]. In another edition [8] the authors
have addressed the problem of meta-stability which becomes important when operating at high sampling speeds.
They propose a gray encoded ROM as the solution. In the year 2006, it has been shown that the static
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2. Low Power CMOS Data Converter with SNDR analysis for High Speed System On Chip Applications
nonlinearity presents in the track and hold circuit [9] can be reduced. In 2004, a complementary average value
technique has been proposed in which the input signal is pre-processed before comparing it with a fixed voltage
reference level in order to simplify the comparator design [10].
III. DESIGN OF 8-BIT FLASH DATA CONVERTER
In this section the proposed 45nm CMOS technology based 8-bit flash analog to digital converter is
described. The 8-bit flash (ADC) Analog to Digital Data Converter consists of following blocks: i) comparator
bank, ii) 1-out of n-code generators and iii) 255 x 8 NOR ROM.
A. System Specifications: The block schematic diagram is shown in the figure 1 below.
Figure 1. Block diagram of a 8-bit flash ADC
The set of comparator circuit accepts an analog input such as current or voltage and provides an n-bit
binary number at the output. Among various analog to digital converters, the flash type ADC is always preferred
for the low power and high speed applications. The proposed ADC is designed which meets the specifications
shown in table 1 where VLSB denotes the quantization step value of the ADC.
Parameter Specifications
Resolution 8 Bit
CMOS Technology 45 nm
Architecture Flash
Power Supply (VDD) 0.6 V
VLSB 500 μV
Speed (Samples /sec.) 3G
Power Consumption 41.78 μW
Signal to Noise Distortion Ratio 31. 9 dB
Table 1. Design Specifications of 45nm Flash ADC
B. Proposed Design Approach: The design of an n-bit flash ADC requires the design of 2n – 1comparators, 1-
out of n code generators and a (2n – 1 x n) NOR ROM. As shown in figure 2, a 4-bit ADC is designed which
need 15 comparators, 1-out of 15 code generators and a 15 x 4 NOR ROM. Similarly, for a 8 bit ADC, we
designed 255 TIQ based comparators, 1-out of 255 code generators and 255 x 8 NOR ROM. As discussed
earlier, the TIQ based technique does not require a resistive ladder circuit like a conventional flash ADC circuit
because the switching voltages for the TIQ comparators are determined by the sizes of the PMOS and NMOS
transistors in the comparator. Hence the design is much simpler, faster and suitable for low power, low voltage
and high speed System-on-chip applications.
Figure 2 shows the circuit diagram for a 4-bit flash ADC based on the TIQ technique. Each of the
comparators is designed to switch at a specific reference voltage. We need 24-1 i.e.; 15 comparators. As the
input analog voltage increases the comparators start turning on in succession from comparator 0 (COMP_0) to
comparator 15 (COMP_15). Thus, we get a thermometer code at the output of the comparators. The point where
the code changes from one to zero is the point where the input signal becomes smaller than the respective
comparator reference voltage levels. This is known as thermometer code encoding, so named because it is
similar to a mercury thermometer, where the mercury column rises to the appropriate temperature and no
mercury is present above that temperature. The thermometer code is converted to a binary code in two steps.
First, the thermometer code is converted into a 1-out of n code using the 1-out of n code generators. This code is
subsequently converted to binary code using a NOR ROM. Therefore the input analog voltage is represented by
a binary code at the output.
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3. Low Power CMOS Data Converter with SNDR analysis for High Speed System On Chip Applications
Figure 2. Schematic diagram of a 4-bit flash ADC
A 8-bit flash ADC design is carried out, which consists of such (fig. 2) two sub-circuit blocks of 4-bit
flash ADC. Using the SUBCKT Netlist coding the two 4-bit flash ADCs can be merged in Tanner S-Edit full
custom schematic design.
IV. DESIGN OF TIQ COMPARATOR
To ensure a high-quality product, the comparator circuit is modified with Threshold Inverter
Quantization technique for low power applications.
A. Working Principle: In this paper the Threshold Inverter Quantization (TIQ) technique is used especially
for low power applications. The TIQ comparator circuit consists of four cascaded inverters as shown in figure 3.
In order to provide sharp switching along with full voltage swing such comparators are very essential.
Figure 3. Schematic diagram of a TIQ comparator
The sizes of the PMOS and NMOS transistors in a comparator are the same, but they are different for
different comparators. They depend upon the switching voltage they are designed for. The mathematical
expression [11] used for deciding these switching voltages is given as:
Where, Wp = PMOS width, Wn = NMOS width, VDD = supply voltage, Vtn = NMOS threshold voltage,
Vtp = PMOS threshold voltage, μn = the electron mobility, μp = the hole mobility, and also assuming that the
PMOS length = NMOS length. The sizes of the NMOS and PMOS transistors used in the proposed 8-bit flash
ADC corresponding to the minimum and maximum switching voltages are shown in Table 2 below.
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4. Low Power CMOS Data Converter with SNDR analysis for High Speed System On Chip Applications
TIQ comparator W/L ratio(s)
switching voltage(s) of CMOS used
248.572 mV PMOS = NMOS =
45nm/90nm 90nm/90nm
335.936 mV PMOS = NMOS =
120nm/90nm 90nm/90nm
Table 2. Transistor Sizing for Different Switching Voltages
For determining these sizes of the PMOS and NMOS transistors in the comparator a DC parametric
sweep is used. The DC voltage was varied from 0 to 0.6V in steps of 500μV with NMOS transistors having
W/L=90nm/90nm. The length of PMOS transistor was also kept at 90nm, and the width was given a parametric
sweep. Therefore 255 switching voltage levels were obtained as shown in figure 4.
Figure 4. DC sweep analysis of a TIQ comparator
B. Encoder Design: The output of the comparators in a flash ADC is a thermometer code. This thermometer
code is converted to a binary code using an encoder in two steps. The thermometer code is first converted into a
1-out-of-n code [12] using 1-out of n code generators, which generates a „01‟ code. This „01‟ code is converted
into a binary code using a NOR ROM. A NOR ROM consists of PMOS pull-up and NMOS pull-down devices.
The PMOS and NMOS sizes for the NOR ROM are 45nm/90nm (W/L) and 90nm/90nm, respectively. We have
taken WPMOS < WNMOS to achieve a good voltage swing [13] because a NOR ROM consists of pseudo
NMOS NOR gates put together. The logic is that the pull-up network (PMOS) should be narrow enough so that
the pull-down devices (NMOS) can still pull down the output safely.
V. SIMULATION RESULTS
In this section the experimental results are analyzed and the functional simulation results are discussed.
The following result analysis concludes its performance for low power applications and suitability for high speed.
The design simulation and characterization is done using Tanner EDA Tools Pro V.15.14 software [14].
A. Transient Analysis of 8-bit Flash ADC:
A transient analysis of 8-bit flash ADC is performed. A sinusoidal AC signal was generated, going from 248.572
mV to 335.936 mV (which is the full scale range of the 8-bit ADC). The digital codes were obtained correctly,
going from 0 to 255 at the output, indicating that the flash ADC was functionally correct. The waveform of 8-bit
flash ADC is shown in figure 5 below. The PMOS are of W/L=45nm/90nm and NMOS are of W/L=90nm/90nm.
The waveforms of 4 bits are shown below. The total 8-bits are of different voltage levels (binary form). The
transient analysis of the 8-bit flash ADC is designed and simulated to prove the functional correctness of the
circuit.
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5. Low Power CMOS Data Converter with SNDR analysis for High Speed System On Chip Applications
Figure 5. Transient Analysis of 8-bit Flash ADC
B. SPICE Netlist Results: The Tanner SPICE also provides simultaneously the backend Netlist coding along
with SPICE Netlist results in 45nm CMOS technology. Figure 6 shows the simulation Netlist result of the flash
ADC.
Figure 6. Simulation Netlist Result of 8-bit Flash ADC
C. Power Analysis of Flash ADC: The Threshold Inverter Quantization (TIQ) technique is used with
WPMOS/WNMOS < 1 for transistors to keep the power consumption as low as possible. It is also observed that
the ADC consumes 41.78μW of peak power and 6.45μW of average power at full speed while it operates on a
power supply voltage of 0.6V. Figure 7 illustrates the detailed power analysis of 8-bit flash ADC.
Figure 7. Power Analysis of 8-bit Flash ADC in 45nm CMOS technology
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6. Low Power CMOS Data Converter with SNDR analysis for High Speed System On Chip Applications
D. Full Custom Layout of 8-bit Flash ADC: Finally the 8-bit flash ADC is analyzed by designing the full
custom layout [15] of the target object (ADC). It includes total 255 TIQ based comparators, 1-out of 255 code
generators and 255 x 8 NOR ROM. The detailed layout is designed (figure 8) by Tanner Pro L-Edit V15.14
software. Each of all mask layers are clearly classified and verified for the exact output results.
Figure 8. Full Custom Layout of 45nm 8-bit Flash ADC
E. Noise Analysis of proposed Flash ADC: The proposed flash ADC has been also characterized for the
differential non-linearity (DNL), integral non-linearity (INL) and the Signal to Noise Distortion Ratio (SNDR).
i) Differential Non-Linearity (DNL): A Verilog-A block has been used to test the DNL. The Verilog-A block
generates a slowly varying full scale range ramp to be given as input to the flash ADC, which completes the full
scale range in 4096 steps. The flash ADC has 256 codes, so ideally there should be 256 hits per code. But for the
transistor level implementation, this is typically not the case. The number of hits per code is recorded, and the
DNL is calculated from that. The results show that the ADC exhibits a maximum DNL of 0.70 LSB, which is
within the acceptable limits. A DNL error specification of less than or equal to 1LSB guarantees a monotonic
transfer function with no missing codes. An ADC's monotonicity is guaranteed when its digital output increases
(or remains constant) [Maxim 2000] with an increasing input signal, thereby avoiding sign changes in the slope
of the transfer curve. The DNL is calculated from the formula:
DNL = |(VD+1 – VD )/(VLSB – IDEAL) – 1| LSB
Where VD is the analog value corresponding to the digital output code D and V LSB – IDEAL is the ideal spacing for
two adjacent digital codes. For an ideal ADC, DNL = 0LSB.
ii) Integral Non-Linearity (INL): Similar to DNL, a Verilog-A block has been used to test the INL that
generates a slowly varying full scale range ramp to be given as input to the flash ADC in 4096 steps. The INL is
calculated from the number of hits per code, of course ideally there should be 256 hits per code. The results
show that the ADC exhibits a maximum INL of 0.46LSB. The INL is calculated from formula [Maxim 2000]:
INL = |(VD – V0 )/(VLSB – IDEAL) – D| LSB
Where VD is the analog value represented by the digital output code D, V 0 is the minimum analog input
corresponding to an all-zero output code and VLSB – IDEAL is the ideal spacing for two adjacent output codes.
iii) Signal to Noise Distortion Ratio (SNDR): The ideal formula for SNDR calculation for an ADC is [Maxim
2001]: SNDR = 20 log10 (ARMS, Signal / ARMS, Noise + Harmonics) dB
Where ARMS,signal and ARMS,noise+harmonics are the root mean square (RMS) amplitude for the signal and the
noise, respectively. Here, signal means the fundamental amplitude signal, and the noise includes the significant
harmonics, which are usually from the second to the fifth highest amplitudes. The signal to noise and distortion
ratio (SNDR) of the designed ADC has been measured at an input frequency of 500 KHz. The Flash ADC is fed
a sinusoidal input (frequency: 500 KHz) which covers the entire full scale range and the output of the ADC if
fed to an ideal digital to analog converter (DAC, modeled as a Verilog-A block). Thus, the output of the DAC is
a reconstructed, digitized sine wave at 500 KHz. The FFT of this sine wave is plotted from which the SNDR is
calculated. The SNDR was found to be 31.9 dB. The FFT plot is shown in figure 9.
Figure 9. FFT Plot of flash ADC at input frequency of 500 KHz for SNDR Calculation
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7. Low Power CMOS Data Converter with SNDR analysis for High Speed System On Chip Applications
VI. Future Scope
The design and simulation results of a 8-bit flash ADC using the 45nm CMOS Technology Model has
been presented. The design is suitable for low voltages (0.6VDD) and high speed (3 Gs/sec) System-on-Chip
applications. The ADC consumes a peak power of 41.78μW and an average power of 6.45μW and SNDR of
31.9dB. Therefore this flash ADC is successfully designed which is functional at nano-scale CMOS
technologies. The layout of 32nm CMOS technology based design is under progress. This project is successfully
designed with a layout for a 45nm process. This project can be extended further with the new advent of
upcoming 32nm CMOS process technology.
REFERENCES
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Hose Lane, P.O.Box 1331, Piscataway,NJ08855-1331 USA.
Author Details:
Ritam Dutta: He earned his M.Tech in VLSI design (ECE) from SRM University, Chennai in 2009 and
B.Tech in Electrical & Electronics Engineering from Sikkim Manipal Institute of Technology, Sikkim Manipal
University, Sikkim in 2007. Currently he is working as an Asst. Professor at Surendra Institute of Engg. &
Management, WBUT, Siliguri. He has almost 4 years of teaching experience. He has published several research
papers in International & National Journals, Conferences and Symposiums across India. He is an Associative
member of several International Associations, such as: UACEE, IAENG, IEEE etc. His research areas are VLSI
design, ASIC design, Bio-metric Security, Email ID: ritam_siliguri@yahoo.com, Ph No: +91-94340-61896.
Krishanu Mitra: He earned his B.Tech in E.C.E from Asansol Engineering College under WBUT in 2010
and done diploma in Electronics and Telecommunication Engg. from Falakata Polytechnic College in 2007.
Recently he is working as an Asst. Engineer at Surendra Institute of Engineering & Management, Siliguri. He
has almost 3 years of experience in academic field. Email ID: kmitra007@gmail.com, Ph: +91-98512-79634.
Moumita Majumdar: She achieved her B.Tech in E.C.E from Siliguri Institute of Technology under
WBUT in 2012 and diploma in Electronics and Telecommunication Engg. from Falakata Polytechnic College in
2009. Recently she is working as Asst. Engineer at Surendra Institute of Engineering & Management, Siliguri.
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