This document discusses selective epitaxial growth (SEG) of SiGe and Ge using chemical vapor deposition (CVD) for advanced MOS devices. It provides an introduction to epitaxy and selective epitaxial growth. Key points covered include pre-epitaxial cleaning to remove native oxide, properties of SiGe alloys, achieving selectivity against oxide and nitride, and examples of selective SiGe growth for quantum well field effect transistors (QWFETs) and raised source/drain applications to improve device performance.

1. SiGe and Ge: selective epitaxial growth
and application in advanced MOS
devices
A. HIKAVYY, B.VINCENT, W.VANHERLE, J. DEKOSTER, L.WITTERS,
H. BENDER, A.THEAN, R. LOO

2. 2© IMEC 2012
CONTENT
 Introduction
 Epitaxy
 Pre-epi clean
 SiGe
 Selective SiGe/Ge epitaxial growth
 Examples
 Conclusions
ICMNE 2012

3. 3© IMEC 2012
IMEC
ICMNE 2012
Imec - headquartered in Leuven,
Belgium.
Additional R&D teams in The Netherlands
(Holst Center in Eindhoven), China,
Taiwan, and India, and offices in Japan
and the USA.
Staff of close to 2,000 people include
more than 600 industrial residents and
guest researchers.
Sensor systems for
industrial applications
Energy
Organic electronics
Imaging systems
Wireless communication
Electronics for healthcare and life sciences
Heterogeneous integration
sub-22nm CMOS

4. 4© IMEC 2012
INTRODUCTION / SCALING
ICMNE 2012
Litho: from 193 nm to 13.5 nm (Sn7+)
ArF immersion
ArF + RET
EUV
L=35nm
SiGe
L=35nmL=35nm
SiGe
NiSi
25 nm
NiSi
25 nm
FUSI
strain
HfO2
high -k
metal gate
FinFET
USJ
Active Area
Gate Field
Spacers
Active Area
Gate Field
Spacers
Active Area
Gate Field
Spacers
Ge/IIIV
silicide
nanowires
graphene
Introduction of high-
mobility channel materials
(e.g. Ge and III/V) on an Si
based platform in (sub)-
22nm CMOS technologies
22 – 14 nm
90 nm

5. 5© IMEC 2012 ICMNE 2012
SiGeSiGe
pMOS: embedded SiGe
NiGe
Hard
mask
TiN/
TaN
Ge subtrate
on Si
NiGeNiGe
Hard
mask
TiN/
TaN
Ge subtrate
on Si
NiGe
HfO2
SiO2
Ge Si (2-7ML)
FinFET: elevated S/D
Ge pMOS: - Si passivation layer
- sGe on SiGe
INTRODUCTION /NEW DEVICES /
IFQW
FDFET
oxide
Elevated Si

6. 6© IMEC 2012
CONTENT
 Introduction
 Epitaxy
 Pre-epi clean
 SiGe
 Selective SiGe/Ge epitaxial growth
 Examples
 Conclusions
ICMNE 2012

7. 7© IMEC 2012 ICMNE 2012
 Epitaxy is a special case of CVD
Si layer
Si substrate
SiH4 2H2
- homoepitaxy: when layer and substrate are from the same material
- heteroepitaxy: when layer and substrate are different materials
 CVD  Chemical Vapor Deposition
 CVD can be defined as the deposition of a solid on a heated surface from
a chemical reaction of a gaseous compound.
 The term “epitaxy” denotes the growth of a thin
crystalline film on a crystalline substrate.
 Epitaxy comes from Greek and means
“arrangement on”.
 To deposit a material on top of an other material, such
that the ordering of the underlying material is
continued in the new layersubstrate
EPI layer
EPITAXY

8. 8© IMEC 2012 ICMNE 2012
EPITAXY
• Build substrate/layer stacks with different
composition and thickness (group IV)
• Composition:
• homo-epitaxy: Si on Si
• hetero-epitaxy: Si1-xGex , Si:C, Si1-x-yGexCy , Ge on Si
• undoped, p or n type doped
• Thickness
• between 0.5 nm and 50 mm

9. 9© IMEC 2012 ICMNE 2012
ChemicalVapour Deposition (CVD)
▸ Preferred for production
▸ All wafer sizes (up to 300 mm)
▸ High and Low temperature epi
▸ Conventional and advanced uses
▸ Very flexible
▸ State-of-the-art: single wafer reactors
EPITAXY

10. 10© IMEC 2012
CONTENT
 Introduction
 Epitaxy
 Pre-epi clean
 SiGe
 Selective SiGe/Ge epitaxial growth
 Examples
 Conclusions
ICMNE 2012

11. 11© IMEC 2012 ICMNE 2012
Growth of high quality epitaxial layers requires :
• The growth conditions need to allow perfect 2D layer-
by-layer growth.
sufficiently high surface mobility of adatoms.
• The starting surface should be crystalline and free of
contaminants .
no contaminants (such as O2, H2O, C) present
during growth in the reactor or precursor gasses.
PRE-EPI CLEAN

12. 12© IMEC 2012 ICMNE 2012
Si wafer
What we have
What we need
Si wafer
~2 nm of native SiO2
No oxide
PRE-EPI CLEAN

13. 13© IMEC 2012 ICMNE 2012
Si wafer
What we have
What we need
Si wafer
~2 nm of native SiO2
Si/SiGe/SiC/Ge/GeSn
PRE-EPI CLEAN

14. 14© IMEC 2012 ICMNE 2012
O reacts with the Si substrate and the H2
carrier gas according to:
SiO2+Si (substrate) ↔ 2SiO↑ (1)
SiO2+2H2 ↔ Si+2H2O↑ (2)
Ideally clean surface
– after high temperature bake (10500C, 30 sec)
Diffusion of SiO through ~1nm native SiO2 layer
requires T > 1000°C.
PRE-EPI CLEAN

15. 15© IMEC 2012 ICMNE 2012
High temperature bake is not compatible with
modern device production!
Epi deposition is done when devices are practically formed
• dopands are present – diffusion.
• gate stack is formed – damage of high-k dielectric
• topography is present (Si recess, FinFETs) – Si/Ge reflow.
• SiGe, Ge channel relaxation
Ex situ wet etch removal of native oxide.
PRE-EPI CLEAN

16. 16© IMEC 2012 ICMNE 2012
Pre-epi cleaning procedure must be optimized for every
particular process.
Pre-epi cleaning procedure consists of:
• Ex situ wet HF dip (SiO2 removal + H passivation ).
• Low temperature in situ bake /removal of remaining SiO2/
(typically 8000C, 2 min.).
PRE-EPI CLEAN

17. 17© IMEC 2012 ICMNE 2012
FDFET IFQW
Epi thermal budget decrease is desired
• to avoid Si agglomeration and reflow;
• to avoid dopants diffusion;
• to avoid SiGe, Ge relaxation/reflow;
No bake?
Tunnel FETFinFET
PRE-EPI CLEAN
oxide
Elevated Si
Drain (Si) Source
(SiGe)
oxide

18. 18© IMEC 2012 ICMNE 2012
No bake?
No much problem for Si
Si is deposited @ 750C
SiGe growth is problematic
SiGe is more sensitive to contamination
SiGe growth temp ~650C and less.
SEG Si75Ge25SEG Si
PRE-EPI CLEAN

19. 19© IMEC 2012 ICMNE 2012
SiGe raised S/D growth without epi bake
No bake /more Ge ==> longer HF dip /
120 sec HF 0.7% dip
+ No bake, 25% SiGe
170 sec HF 0.7% dip
+ No bake, 25% SiGe
PRE-EPI CLEAN

20. 20© IMEC 2012
CONTENT
 Introduction
 Epitaxy
 Pre-epi clean
 SiGe
 Selective SiGe/Ge epitaxial growth
 Examples
 Conclusions
ICMNE 2012

21. 21© IMEC 2012
INTRODUCTION
ICMNE 2012
Litho: from 193 nm to 13.5 nm (Sn7+)
Scaling
ArF immersion
ArF + RET
EUV
L=35nm
SiGe
L=35nmL=35nm
SiGe
NiSi
25 nm
NiSi
25 nm
FUSI
strain
HfO2
high -k
metal gate
FinFET
USJ
Active Area
Gate Field
Spacers
Active Area
Gate Field
Spacers
Active Area
Gate Field
Spacers
Ge/IIIV
silicide
nanowires
graphene
Introduction of high-
mobility channel materials
(e.g. Ge and III/V) on an Si
based platform in (sub)-
22nm CMOS technologies
22 – 14 nm
90 nm

22. 22© IMEC 2012
SIGE
ICMNE 2012
• Si and Ge make alloys over full range (0-100 %)
• Lattice constants:
• Si: 5.4282 Å
• Ge: 5.658 Å
• Si1-xGex: ~5.4282 + (5.658-5.4282)x

23. 23© IMEC 2012 ICMNE 2012
SIGE

24. 24© IMEC 2012 ICMNE 2012
P. Packan, IEDM 2010,
p 1268
SIGE

25. 25© IMEC 2012 ICMNE 2012
K. J. Kuhn, A. Murthy, R. Kotlyar, and M. Kuhn ECS Transactions, 33 (6) 3-17 (2010)
“Strain” contribution increases with every node
Ge concentration increases (~ 50% for 22 nm node)
SIGE

26. 26© IMEC 2012
SIGE
ICMNE 2012
Si precursors : SiH4, SiH2Cl2,Si2H6, Si3H8,etc.
Ge precursor : GeH4,
Hartmann, Abbadie, and Favier
J. Appl. Phys. 110, 083529 (2011)

27. 27© IMEC 2012
CONTENT
 Introduction
 Epitaxy
 Pre-epi clean
 SiGe
 Selective SiGe/Ge epitaxial growth
 Examples
 Conclusions
ICMNE 2012

28. 28© IMEC 2012
An epi process is selective when material deposition happens
only on dedicated Si surfaces.
No poly deposition on oxides and nitrides.
In some cases only Si and SiO2 are present (early in the flow).
ICMNE 2012
SiGe epi
STI
Si3N4
SiGe epi
STI
SELECTIVE EPI GROWTH

29. 29© IMEC 2012 ICMNE 2012
Epi process Selective to SiO2 Selective to Si3N4
Si
SiH4, SiH2Cl2, Si2H6 etc
no no
SiGe
Si precursor+GeH4
Typically no Typically no
Ge
GeH4, Ge2H6
yes no
GeSn
Ge2H6+SnCl4
yes ?
Selectivity of Ge and GeSn depends on the process and
can be deteriorated when deposition rate is very high.
Most of the processes are not fully selective
SELECTIVE EPI GROWTH

30. 30© IMEC 2012
In order to achieve selectivity an etching reaction has to be
implemented.
Usually it is done by adding HCl to the gas mixture.
Co-flow scheme or cyclic scheme (Si:C:P)
ICMNE 2012
SELECTIVE EPI GROWTH
K. H. Chung, and J. C. Sturm
ECS Transactions, 6 (1) 401-407 (2007)

31. 31© IMEC 2012 ICMNE 2012
HCl etch ATM , blanket
0
2
4
6
8
10
12
500 550 600 650 700 750 800 850
Etch temperature, C
Etchrate,nm/min Etch rate, poly-Si
Etch rate, c-Si
40T etch 200 HCl
STI wafer
AL070088
Poly SI/c-Si =9.1
Poly SI/c-Si =5.56
Poly SI/c-Si =2.5
SELECTIVE EPI GROWTH
It is possible to find such precursors flows that
only crystalline Si (SiGe) deposition is observed

32. 32© IMEC 2012 ICMNE 2012
SELECTIVE SIGE EPI GROWTH
Si epi
Not selective
(oxide, nitride)
Ge epi
Selective (oxide)
Not selective
(nitride)
SiGe
?

33. 33© IMEC 2012 ICMNE 2012
Selectivity 0%
Selectivity 50%
Selectivity 100%
Both SiH4 and DCS based SiGe
processes become selective when
Ge content increases above 35%.
For disilane Ge concentrations was
limited around ~30%.
(Epi tool limitation)
SELECTIVE SIGE EPI GROWTH
Blanket
Wafers
With SiO2
surface

34. 34© IMEC 2012 ICMNE 2012
Neither of the processes showed full
selectivity.
Closed poly SiGe layer observed for
low Ge concentrations (below 40%)
Separate poly particles even for pure
Ge growth on nitride surface.
Selectivity 0%
Selectivity 50%
Selectivity 100%Blanket
wafers
With Si3Ni4
surface
SELECTIVE SIGE EPI GROWTH

35. 35© IMEC 2012 ICMNE 2012
Previous graphs lead to a conclusion that either full or
partial selectivity of SiGe towards oxide/nitride can be
achieve @ high Ge concentrations.
Less HCl (Cl) is needed for fully selective SiGe processes
Processes @ different temperatures
HCl effectiveness drops with
temperature decrease
HCl effectiveness increases with Ge%
increase
SELECTIVE SIGE EPI GROWTH

36. 36© IMEC 2012
CONTENT
 Introduction
 Epitaxy
 Pre-epi clean
 SiGe
 Selective SiGe/Ge epitaxial growth
 Examples
 Conclusions
ICMNE 2012

37. 37© IMEC 2012 ICMNE 2012
IFQW: Device Concept
G. Hellings, IEDM 2010
Main Features
▸ charges confined to a thin QW channel
▸ QW is close to the gate  short channel control
▸ pFET/QW for holes: Si/SiGe/Ge
▸ nFET/QW for electrons: InGaAs/InAlAs
QW channel: SiGe45%
Si (n-well)
gatesource drain
SiGe:B 25%
VB offset
SELECTIVE SIGE EPI EXAMPLES
CB
VB
EV = 0.84 x eV
EC ~ 0 eV
Strained
Si1-xGex
Unstrained Si
EV

38. 38© IMEC 2012 ICMNE 2012
Comparison : bulk Si pFET vs. SiGe IFQW pFET
Current
density
A/cm2
sub-surface s/d leakage s/d leakage avoided
S D
G
S D
G
OFF-state current density: VG-VT=0.4V; VD=-1V OFF-state current density: VG-VT=0.4V; VD=-1V
h+= 8×107cm-3
h+= 3×1015cm-3
TCAD simulation, OFF-state current density
▸ sub-surface leakage path exists, increasing halo doping may not be an
option anymore
▸ band offset reduces hole density in the substrate
with factor ~ 3x105 for Si0.55Ge0.45/Si interface
▸ Minimal required band offset is 200 meV
q
kT
EV
e

SELECTIVE SIGE EPI EXAMPLES

39. 39© IMEC 2012 ICMNE 2012
G. Hellings, IEDM 2010
S. Yamaguchi, IEDM 2011
< 1nm Si-cap / SiGe-channel
SELECTIVE SIGE EPI EXAMPLES

40. 40© IMEC 2012 ICMNE 2012
108
106
104
102
100
10-2
0.4 0.8 1.2 1.6 2
Lifetime[s]
|VG-Vth| [V]
0%
45%
55%
Si cap=1.3nm
QW=7nm
Ge fraction
10Y
Negative Bias Temperature Instability
SELECTIVE SIGE EPI EXAMPLES
ION/IOFF performance at VD = -1V of the
eSD:SiGe FQW pFET. Benchmarking with
other planar pFETs

41. 41© IMEC 2012 ICMNE 2012
Ge IFQW
Unstrained Ge
Raised SiGe
SiGe
Si
{113}{113} 76
361
{111}{111}
Ge
In-situdopedSiGe orGeSnS/D
sGe channel
SiGe-SRB
B-SiGe75% on unstrained Ge
SELECTIVE SIGE EPI EXAMPLES

42. 42© IMEC 2012 ICMNE 2012
GESN SOURCE/DRAIN STRESSORS
Initial motivation (B.Vincent EMRS2010, MicroElec Eng. 2011)
45nm compressive Si
pMOSFET from INTEL
SiGe SiGe
Comp.
Si GeSn GeSn
Comp.
Ge
New compressively strained Ge
MOSFET architecture
Replacing Si channel by Ge channel implies...
Replacing SiGe embedded Source/Drain by GeSn

43. 43© IMEC 2012 ICMNE 2012
GESN SOURCE/DRAIN STRESSORS
Current motivation
Relaxed SiGe
From our s-SiGe Implant Free QuantumWell pFET, we replace:
-Si substrate by SiGe relaxed buffer
-SiGe channel by a strained Ge channel
-Raised SiGe Source/Drain by GeSn
B.Vincent et al.
ECS Fall meeting 2012
L.Witters et al., IEDM11 (imec)

44. 44© IMEC 2012 ICMNE 2012
B. Vincent et al., Appl. Phys. Lett. 2011
GeSn grown on Ge at 320C and
ATM with Ge2H6 and SnCl4:
-fully strained GeSn8%, defect free
-(2x1) surface reconstruction along
the [110]Ge direction
3 to 10% obtained with different Ge2H6 and
SnCl4 flows, keeping 320C as growth
temperature
GESN SOURCE/DRAIN STRESSORS

45. 45© IMEC 2012 ICMNE 2012
Adding B2H6 in the gas phase reaction
 B being easily incorporated in
GeSn when adding B2H6
 B being fully activated during the
growth  no need of post growth
activation anneal
 Sn% decreased when using to high
B2H6 by products
 B vs. Sn benchmark does no achieve
the high Sn-high B concentrations area
 incorporation or gas phase reaction
related?
GESN SOURCE/DRAIN STRESSORS

46. 46© IMEC 2012 ICMNE 2012
CONCLUSIONS
Scaling is not stopping
Epitaxy is one of the techniques that helps to
boost transistors performance
SiGe and Ge are valuable materials for future
scaling concepts
SiGe with high Ge % is selective towards oxide
but not nitride.An etchant must be used.

47. 47© IMEC 2012 ICMNE 2012
ACKNOWLEDGEMENTS
Members from the epi group
Device integration teams
Analysis team
Pilot line
Industrial and non-industrial partners
...