MBE

1. Microelectronics:
Epitaxial Growth
SIRYSTALLINE
FILMS

2. • Introduction
• Types of Epitaxy
• Deposition Requirements
• Epitaxial Growth
• Lattice Strains - Misfit
• Application
• Summary
Content

3. Introduction
Epitaxy
Epi (ἐπί)
„upon“ or „above“
Taxis (τάξις)
„arrangement” or “order”
• Deposition of a layer on a substrate which matches
the crystalline order of the substrate

4. • Homoepitaxy - the film and the substrate are the same
material.
• Often used in Si on Si growth.
• Epitaxially grown layers are purer than the substrate and
can be doped independently of it.
Types of Epitaxy
• Heteroepitaxy - film and substrate are different materials.
• GaAs on Si growth
• Allows for optoelectronic structures and band gap
engineered devices.
CHK IMG IN PAGE 14.
GGAS IS MORE
EXPENSIVE
THAN SiSUBSTRATE

5. Epitaxial growth is useful for applications that place
stringent demands on a deposited layer:
• High purity
• Low defect density
• Abrupt interfaces
• Controlled doping profiles
• High repeatability and uniformity
• Safe, efficient operation
Can create clean, fresh surface for device fabrication
Motivation
CHK?
CHK?

6. Surface preparation
• Clean surface needed
• Defects of surface duplicated in epitaxial layer
• Hydrogen passivation of surface with water/HF
Surface mobility
• High temperature required heated substrate
• Epitaxial temperature exists, above which deposition is ordered
• Elements need to be able to move into correct crystallographic
location
• Relatively slow growth rates result
Epitaxial Deposition Requirements
-,
1,5619: --45
(CONTROLLED
BY TEMPERATURE)
CONTROLLED
BY THE
TEMP
. AND CLEAN SURFACES
THICK FILMS TAKE MORE
THAN ONE
DA
Y

7. Epitaxial Growth
Transport of gas (CVD) Adsorption of molecule
Decomposition of molecule Surface diffusion
Crystallization Removing unwanted molecules
TO THE SURFACE
TEMP. CONTROL
· H2REMOVED,
·CI2REMOVED
· HCL Also
REMOVED
CHIL FOR CLEAN
THE SURFACE)
H -
Cl COMBINE AND
-
REMOVE

8. Example of Epitaxial Growth
• Growing Si on Si substrate
same crystallographic properties, but it can
have a different dopant concentration or
another dopant
Si substrate Growing Si

9. Example of Epitaxial Growth (CVD)
)
TO PASSIVATE CHINDER THE
OXIDATION, WHICH
MAY
HAPPENED)
B
Y
THE PRESENCE
OF OZ
e.q
SOME OTHER GASES
e. ge

10. Epitaxial Reactor (CVD)
• Epitaxial reactor
HEATING COIL
m e
CLEANING
GAS

11. • Silicon wafer is placed on a graphite block - susceptor. Plates
are with the susceptor placed into the working chamber of
quartz glass. Around it is a heating coil.
Epitaxial Reactor (CVD)
HEATING
LOiL

12. • During the process, the working chamber with plates is flushed with
nitrogen and then with hydrogen. In an atmosphere of hydr. are plates
heated by induction heating to a temperature of around 1200 °C.
Epitaxial Reactor (CVD)
FOR CLEANING
-
MUCH HIGHER THAN CVD

13. • At high temperature the process begin. The susceptor with cooled
plates is after rinsing with nitrogen pulled from working chamber.
Epitaxial Reactor (CVD)

14. Lattice Strains - Misfit
• Nearly matched lattices are desired to minimize defects and
increase electron mobility
• As the mismatch gets larger, the film material may strain to
accommodate the lattice structure of the substrate
• Si-Ge - rippled surf. and pyramidal tips are typical:
• If strain accommodation is not possible then dislocation
defects at the interface may form
CHK

15. Lattice Strains - Misfit
P epi
P+ substrate
P epi
P+ substrate
Layer
mechanically
strained
Misfit dislocation
relieve stress
CRYSTAL STRUCTURE
OF
THE EPITAXYMATERIAL
IS MORE
PERFECT
THAN
THE
SUBSTRATE.

16. Defects
• Defects reduce electron mobility,
carrier conc. and optical efficiency.
• Defects can propagate from the
substrate as a screw (helical)
dislocations.
• Dopants and impurities can
cause edge and point dislocations.
• Another type of defect is the stacking
faults where the stacking order of
successive layers

17. Application
Engineered wafers
• Clean, flat layer on top of less ideal Si substrate
• On top of SOI structures
• Higher purity layer on lower quality substrate
In (Bi)CMOS structures
• Layers of different doping
• p- layer on top of p+ substrate
note: STI = shallow trench isolation
~m
(SOI:SILICONINSULATOR).

18. Bipolar Transistor
• Needed to produce buried layer
• Create lateral isolation
III-V Devices
• Interface quality key
• Heterojunction Bipolar Transistor
• LED
• Laser
Application
HETROEPITAXY
STRUCTURE
LAYERS
I
LASER

19. • Deposition continues crystal structure
• Creates clean, abrupt interfaces and high quality
surfaces
• High temperature, clean surface required
• Vapor phase epitaxy a major method of deposition
• Epitaxial layers used in highest quality wafers
• Very important in III-V semiconductor production
Summary
AVOID DEFECT AND DISLOCATION

20. References
[1] . Paul H. Holloway and Gary E. McGuire, Preface, In Handbook of Compound Semiconductors,
edited by Paul H. HollowayGary E. McGuire, William Andrew Publishing, Park Ridge, NJ,
1996, Pages vii-viii, ISBN 9780815513742, http://dx.doi.org/10.1016/B978-081551374-
2.50001-6.
[2] Leslie A. Kolodziejski, Dr. Gale S. Petrich. Epitaxial Growth and Processing of Compound. RLE
Progress Report Number 141
[3] ..BORGSTRÖM, Magnus. Epitaxial growth, processing, and characterization of semiconductor
nanostructures. Lund: Univ, 2003. ISBN 91-628-5876-9.
[4]…ON Semiconductor. [prezentace] Od křemene ke křemíkové desce
Piěšťany 2012., VPS s.r.o. [cit. 2015-06-28].
[5] S.J. PEARTON, S.J. Pearton. Topics in growth and device processing of III-V semiconductors.
Singapore: World Scientific, 1996. ISBN 978-981-0218-843.
[6] Daniel Lentz,. Epitaxial Deposition. [prezentace] EE 518 Penn State University., [cit. 2015-06-
28].
[7] EKENSTEDT, Michael. Growth of Strained III-V Semiconductors by Molecular Beam Epitaxy.
Göteborg: vl. n., 1993. ISBN 91-628-1083-9.

21. Silicon on insulator
17. MARCH-2023

22. Technology of SOI preparation
• solve a problem of the parasitic capacitance of the
bulk Si wafer – semiconductor industry – depress the
conductive bulk
• Insulator – SiO2 (SOI) or Sapphire (SOS)
• Heteroepitaxy – direct growth on crystaline insulator
(SOS), limited utility
• SIMOX process – creation burried SiO2 in Si bulk
• Wafer bonding – direct bonding of oxidized silicon
wafer with a second substrate (widespread techlogy)
– Majority of the substrate is removed
• separation techniques to adjust Si thickness (Smart Cut
technique)
you can obtain very thick waterbut
atthe end you will remove the
Major
part of it
(by--I)

23. SIMOX
SIMOX – Separation by IMplantation of Oxygen
• Oxygen is implanded deeply to Si wafer bulk
• High temperature anealing >1000°C
G. K. Celler and S. Cristoloveanu; J. Appl. Phys., Vol. 93, No. 9, 1 May 2003
you
implantation
notice the layer thickness of
the
(SiO2)
②
Smooth ③
=
④ oxidation
a
S
Insulator
layer

24. Wafer Bonding and Smart Cut
Smart Cut - atomic scalpel
• hydrogen implantation to oxidized Si wafer
• bonding at 800-1200°C during 30 s
• exfoliation of top silicon via microcracks created by
H+ ions (Smart Cut)
• polishing
• reuse of wafers
Others separation techniques
• NanoCleave - uses stress (only in case of SiGe alloy)
• ELTRAN – use porous silicon and water cut
BOND BOTH WAFER
TOGETHER
I &
CHY -
↑
-
CHK
6Bishing

25. ADDITIONAL SLIDES
STRAINED SILICON