1. Deutsche Bank held a technology conference in London on September 14, 2007 where Franki Dâ€TMHoore, Director of Investor Relations at ASML, presented on the lithography systems company.
2. ASML is the world's leading provider of lithography systems for the semiconductor industry, serving 17 of the top 20 semiconductor manufacturers. In 2006, ASML had a market share of 63% and net sales of €3.6 billion.
3. ASML's lithography roadmap enables continued shrinkage for logic, DRAM and NAND flash technologies through ongoing innovation and the introduction of new product lines such as the XT:1900 and XT:1700 with improved resolution and throughput.
Semiconductor manufacturing roadmaps are contingent upon the lithography tool supplier product. EUV appears to be a viable alternative to DP/HP immersion. ASML details their EUV roadmap, and offers specifications and a look at upgrades for next node product.
Public Presentation, ASML EUV forecast Jul 2010JVervoort
The document discusses progress on EUV lithography systems for semiconductor manufacturing. It outlines ASML's lithography roadmap to support Moore's Law with EUV technology. It describes the status of their 0.25NA and 0.32NA EUV systems, including resolution improvements achieved and integration progress. It provides outlook on their EUV roadmap and future systems aimed at 16nm nodes and beyond.
This document discusses optical lithography and the challenges of achieving high resolution for integrated circuit fabrication. It covers the lithography process, the role of lithography in IC fabrication, and resolution challenges like diffraction. It then describes several lithography methods used today or under development to improve resolution, including proximity lithography, contact lithography, projection lithography, phase-shifting masks, immersion lithography, and extreme ultraviolet lithography (EUVL). The document focuses on EUVL and the associated challenges of mask design and multilayer optics required for EUV wavelengths. It concludes with a section on simulating an EUV lithography system.
ASML will acquire HMI to enhance its holistic lithography product portfolio. The acquisition will boost ASML and HMI's metrology technologies and support EUV technologies. It will also support ASML's holistic lithography strategy and addressable market opportunities. The acquisition is expected to close in Q4 2016, pending shareholder and regulatory approval.
This document summarizes a presentation given by Lucas van Grinsven of ASML about keeping innovation moving. It discusses:
1) ASML is a cornerstone of the chip industry and its strategy is to be a technology leader in lithographic systems, enabling customers to increase chip functionality while reducing cost and power consumption.
2) Sustainability is a key driver of the chip industry as Moore's Law allows chips to double in power every 1.5-2 years while reducing price, leading to growth in applications like smartphones. ASML enables this through lithography equipment.
3) ASML is taking steps to reduce the energy usage and carbon emissions of its business, focusing on reducing emissions per transistor,
Extreme UV (EUV) lithography uses light with a wavelength of 13.5nm to enable the next generation of smaller computer chips. It relies on specialized curved mirrors coated with molybdenum and silicon instead of lenses, since materials absorb EUV light. The only viable source of 13.5nm light is a hot plasma created by firing a powerful laser at a target. EUV lithography requires operating in a vacuum and developing new resist materials since existing ones strongly absorb the short wavelength light. It holds the potential to further advance computer processing power through smaller transistor sizes.
The document discusses the history and development of micro-optics manufacturing from the 19th century to present day. Key developments include the use of microlenses in color photography in the 1920s, the application of semiconductor manufacturing techniques to micro-optics starting in the 1960s, and the current trend toward wafer-level micro-optics processing and packaging. SUSS MicroOptics is highlighted as a leading supplier of high-quality micro-optics manufactured using 8-inch wafer technology.
Semiconductor manufacturing roadmaps are contingent upon the lithography tool supplier product. EUV appears to be a viable alternative to DP/HP immersion. ASML details their EUV roadmap, and offers specifications and a look at upgrades for next node product.
Public Presentation, ASML EUV forecast Jul 2010JVervoort
The document discusses progress on EUV lithography systems for semiconductor manufacturing. It outlines ASML's lithography roadmap to support Moore's Law with EUV technology. It describes the status of their 0.25NA and 0.32NA EUV systems, including resolution improvements achieved and integration progress. It provides outlook on their EUV roadmap and future systems aimed at 16nm nodes and beyond.
This document discusses optical lithography and the challenges of achieving high resolution for integrated circuit fabrication. It covers the lithography process, the role of lithography in IC fabrication, and resolution challenges like diffraction. It then describes several lithography methods used today or under development to improve resolution, including proximity lithography, contact lithography, projection lithography, phase-shifting masks, immersion lithography, and extreme ultraviolet lithography (EUVL). The document focuses on EUVL and the associated challenges of mask design and multilayer optics required for EUV wavelengths. It concludes with a section on simulating an EUV lithography system.
ASML will acquire HMI to enhance its holistic lithography product portfolio. The acquisition will boost ASML and HMI's metrology technologies and support EUV technologies. It will also support ASML's holistic lithography strategy and addressable market opportunities. The acquisition is expected to close in Q4 2016, pending shareholder and regulatory approval.
This document summarizes a presentation given by Lucas van Grinsven of ASML about keeping innovation moving. It discusses:
1) ASML is a cornerstone of the chip industry and its strategy is to be a technology leader in lithographic systems, enabling customers to increase chip functionality while reducing cost and power consumption.
2) Sustainability is a key driver of the chip industry as Moore's Law allows chips to double in power every 1.5-2 years while reducing price, leading to growth in applications like smartphones. ASML enables this through lithography equipment.
3) ASML is taking steps to reduce the energy usage and carbon emissions of its business, focusing on reducing emissions per transistor,
Extreme UV (EUV) lithography uses light with a wavelength of 13.5nm to enable the next generation of smaller computer chips. It relies on specialized curved mirrors coated with molybdenum and silicon instead of lenses, since materials absorb EUV light. The only viable source of 13.5nm light is a hot plasma created by firing a powerful laser at a target. EUV lithography requires operating in a vacuum and developing new resist materials since existing ones strongly absorb the short wavelength light. It holds the potential to further advance computer processing power through smaller transistor sizes.
The document discusses the history and development of micro-optics manufacturing from the 19th century to present day. Key developments include the use of microlenses in color photography in the 1920s, the application of semiconductor manufacturing techniques to micro-optics starting in the 1960s, and the current trend toward wafer-level micro-optics processing and packaging. SUSS MicroOptics is highlighted as a leading supplier of high-quality micro-optics manufactured using 8-inch wafer technology.
Optical lithography moved to shorter wavelengths like deep ultraviolet (DUV) due to limitations of mercury lamps. Excimer lasers emitting at wavelengths like 248nm and 193nm were adopted as they met the requirements of high photon energy and shorter wavelengths. As feature sizes continued shrinking, even shorter wavelengths like extreme ultraviolet (EUV) at 13.5nm were needed. EUV lithography uses reflective optics since materials absorb at this wavelength, and requires operating in vacuum since all materials absorb EUV radiation. Key challenges for EUV include developing high power radiation sources, improving reflective mirror lifetimes against contamination, and developing suitable photoresists with low line edge roughness.
Status of Advanced Substrates 2019 report by Yole DéveloppementYole Developpement
Demands from the new digital age are waking up the sleeping substrate giants.
More information on https://www.i-micronews.com/products/status-of-advanced-substrates-2019/
The new storage-class memory (SCM) category will be the biggest emerging NVM market, with embedded MCU seeking emerging NVM for strategic differentiation.
PCM leads the race to storage-class memory (SCM), but RRAM will catch up soon
In 2015, the Micron/Intel alliance presented a breakthrough stand-alone memory product called 3D Xpoint, developed in secret for many years, which uses PCM material instead of RRAM as we expected. Thus, after being down and out for a while, PCM made a big comeback in the emerging NVM race. This product has an amazingly high density for an emerging NVM (128 Gb), which is close to the latest NAND thanks to high node (20nm), a 3D crosspoint structure, and a good selector. We expect PCM will have the largest emerging NVM market share by 2021, thanks to its prominent promoters (Micron/Intel), which have sufficient influence to create a new SCM category using 3D Xpoint in the memory hierarchy. Indeed, creating a new memory category is a sea-change that will require numerous hardware and software developments by all memory ecosystem players. And while there is no general agreement, many experts believe DRAM sales will decrease due to SCM’s increased use. For this reason, many incumbent players, especially DRAM ones, have postponed their SCM product introduction in order to extend their DRAM profits, which over the last several years have been very high.
This document discusses ultra thin body SOI FETs. Some key points:
- SOI uses a thin silicon layer on an insulating substrate to reduce parasitic capacitance and improve performance over bulk silicon. Fully depleted SOI is preferred for its thin size and reduced leakage/power consumption.
- Benefits of SOI include lower capacitance, resistance to latch-up, higher performance at lower voltages, reduced temperature effects, better yields, and reduced leakage currents.
- Ultra thin body SOI FETs have even better gate control and mobility due to thin channel thickness, lower parasitic capacitance, and reduced leakage currents, making them useful for applications like memory, microelectronics, RF devices,
Epitaxy Growth Equipment for More Than Moore Devices Technology and Market Tr...Yole Developpement
Driven by microLED displays and power devices, epitaxy equipment shipment volumes will multiply more than threefold over the next five years.
More info on: https://www.i-micronews.com/products/epitaxy-growth-equipment-for-more-than-moore-devices-technology-and-market-trends-2020/
Bonding and Lithography Equipment Market for More than Moore Devices by Yole ...Yole Developpement
More than Moore devices fueled by megatrend applications will strongly drive the growth of the lithography, permanent bonding, and temporary bonding and debonding equipment market.
More information on that report at https://www.i-micronews.com/report/product/bonding-and-lithography-equipment-market-for-more-than-moore-devices.html
MO Exposure Optics (MOEO), is a novel mask aligner illumination system for all SUSS MicroTec Mask Aligners. Self-calibrating light source (no lamp alignment after lamp exchange), improved light uniformity, telecentric illumination and the possibility of freely shaping the angular spectrum are main advantages. Full control of the illumination allows to reduce diffraction effects, enhance resolution, improve CD uniformity and yield. It is now possible to fully simulate the lithography process by using LAB software from GenISys. Well known lithography techniques like customized illumination, optical proximity correction (OPC) and source-mask optimization (SMO) are now available for mask aligner lithography. Mask aligner lithography has entered a new era.
VCSELs – Market and Technology Trends 2019 by Yole DéveloppementYole Developpement
New functionalities in smartphone and automotive are boosting the VCSEL market.
More information on https://www.i-micronews.com/products/vcsels-market-and-technology-trends-2019/
Fan-Out and Embedded Die: Technologies & Market Trends 2015 Report by Yole De...Yole Developpement
Fan-Out and Embedded Die: Two promising Wafer/Panel-Level-Packaging technologies. What are the next steps for the growth?
Fan-Out Wafer Level Packaging is already in high-volume – but it’s about to grow even more strongly
Fan-Out Wafer Level Packaging (FOWLP) started volume commercialization in 2009/2010 and started promisingly, with initial push by Intel Mobile. However, it was limited to a narrow range of applications – essentially single die packages for cell phone baseband chips – reaching its limit in 2011. In 2012 big fab-less wireless/mobile players started slowly volume production after qualifying the technology...
This presentation summarizes silicon-on-insulator (SOI) devices and technologies. It discusses how SOI can achieve high performance and low power usage by placing a buried oxide layer between the silicon device layer and substrate. Key advantages of SOI include reduced junction capacitance, elimination of latchup, lower power consumption, and smaller die size. Various SOI fabrication techniques are presented, including SIMOX, BESOI, and Smart Cut. Current applications of SOI include microprocessors, networking, automotive, and emerging areas like FinFETs, optical waveguides, image sensors, and high voltage switching. SOI is predicted to be an important technology for continued scaling of CMOS to smaller nodes.
Lowering Production Cost of "Big MEMS (and Sensors)" Chip Technologies using ...INVIZA® HEALTH
Since the 1980’s microelectromechanical systems (“MEMS”) based devices have been manufactured primarily on round silicon (“Si”) substrates. This has been accomplished by primarily riding the “coattails” of the semiconductor (“SEMI”) integrated circuit chip industry, where Si substrate diameters have grown from less than 50 mm to 300 mm. As new larger diameter fabrication equipment was needed the previous generation tools (refurbished) were adopted by the MEMS industry at much lower price points.
Today, the SEMI industry has stalled at 300 mm, likewise the MEMS industry is mired at 200 mm diameter. The issue is that many MEMS chip dimensions can be large, greater than 10 x 10 mm^2 in area and can have expensive wafer-level packaging (“WLP”) utilized to protect its moving parts from inexpensive plastic molded packaging. When considering the $1 per mm^2 ‘rule of thumb’ for unyielded chip production cost, these “Big MEMS” chips are very difficult to fabricate cost effectively for their accompanying product market adoption.
Meanwhile over the last two decades of flat panel display (FPD) technology requirements have continued to increase in complexity and manufacturing capabilities. This includes increasing FPD resolution from today’s 4K to 8K and glass substrate size up to 3.1 x 3.1 m^2, a.k.a. ‘Generation 10 (Gen 10 or G10)’ glass. To achieve these challenging levels many manufacturing obstacles have had to be overcome, such as magnetron sputtering over large areas, including deposition thickness uniformity and optical property uniformity, the reduction of yield detractors, such as particles generated due to plasma arcing, and other process challenges.
What if the MEMS/sensor industry wasn’t restricted in substrate size, such as by utilizing G8 (2.1 x 2.4 m^2) or older (smaller area) fabrication equipment? Then, the chip cost could dramatically decrease.
Power GaN 2019: Epitaxy, Devices, Applications and Technology Trends - Yole D...Yole Developpement
First design-win for GaN HEMTs in the high-volume smartphone fast charging market.
More information on: https://www.i-micronews.com/products/power-gan-2019-epitaxy-devices-applications-technology-trends/
2.5D heterogeneous and 3D wafer-level stacking are reshaping the packaging landscape.
More information on that report at https://www.i-micronews.com/advanced-packaging-report/product/p2-5d-3d-tsv-wafer-level-stacking-technology-market-updates-2019.html
The document discusses 3D integrated circuits (3D ICs) and through-silicon vias (TSVs). It provides an overview of Yole Developpement, a research and consulting firm focused on advanced packaging. Yole analyzes trends in the semiconductor packaging industry and markets for 3D ICs. The document outlines several applications of 3D ICs and TSVs, including image sensors, memory, logic, and MEMS. It compares the benefits of 2D and 3D packaging approaches and provides timelines for adoption of technologies like TSVs across different applications.
The document describes the key steps in the semiconductor manufacturing process including silicon manufacturing using the Czochralski method, photolithography using photoresists and photomasks, and ion implantation. Photolithography involves coating wafers with photoresist, exposing it to light through a photomask, and developing the resist to transfer patterns. Ion implantation injects dopants by accelerating ions toward the wafer surface.
SOI Applications -- an overview and some examplesAdele Hars
This document provides an overview of SOI-based applications and examples. It discusses how SOI enables lower power, higher performance, and smaller, faster, cooler chips that can operate in harsh environments. Examples include the IBM Z13 mainframe and Casio G-Shock watches. FD-SOI is gaining traction with companies like STMicroelectronics, GlobalFoundries, and Samsung offering it. Applications discussed include automotive, Internet of Things, mobile, and more.
The document summarizes key steps in the fabrication of integrated circuits: thermal oxidation grows a silicon dioxide layer on the wafer for diffusion barriers and insulation; photolithography patterns the oxide layer using a mask, photoresist, and etching; dopant diffusion introduces impurities into the silicon by heating to allow movement; and metal evaporation deposits a thin aluminum film to connect components. These process steps are precisely controlled to build up the circuit structures layer-by-layer on the silicon wafer.
ASML Investor Day 2021-Technology Strategy - Martin van den Brink.pdfJoeSlow
- Moore's Law scaling of transistor and lithography density is expected to continue into the next decade, driven by innovations in lithography technology.
- While traditional metrics like clock frequency growth have saturated, other metrics like energy efficient performance that measure combined energy and time efficiency are still growing exponentially and expected to do so into the 2030s.
- System-level innovations involving new device architectures, 3D chip stacking, and other approaches will boost energy efficient performance beyond what transistor scaling alone provides, ensuring Moore's Law scaling continues at the system level.
Optical Lithography, Key Enabling Technology for our Modern WorldReinhard Voelkel
In 1959, Richard P. Feynman initiated the Nano-age in his lecture “There’s plenty of room at the bottom”. Feynman also had a clear vision about computers and asked: ”Why can’t we make them very small, make them of little wires, little elements - and by little, I mean little. For instance, the wires should be 10 or 100 atoms in diameter, and the circuits should be a few thousand angstroms across.”
At the same time, Jean Hoerni from Fairchild Semiconductors tried to get his “planar process” to production. Hoerni’s planar process using silicon substrates, so-called “wafers”, revolutionized semiconductor manufacturing and was widely adapted by the industry. The great success of the planar wafer process is also much related with tremendous improvements in optical lithography over all the years. From the early age dominated by mask aligners to highly sophisticated steppers and scanners, lithography was the key enabling technology, allowing now – 50 years after Feynman’s vision – nanostructuring down to the atomic scale on 300mm planar wafers. The evolutionary development of optical lithography is reviewed along with a brief discussion of options for the future.
The document provides technical information about components and schematics for Nokia mobile phone models NHM-5/UB 4 V09-V10. It includes diagrams of the radio frequency schematic, power levels and voltages for GSM 900 and 1800 bands. Tables list component locations on the printed circuit board by coordinates and component codes. The document is marked confidential and intended only for training and service purposes.
The document describes a radiation hardened 8-input NAND gate called the ACS30MS that is qualified for use in military and aerospace applications. It provides details on the device's features such as its radiation tolerance, input/output specifications, and packaging options. Ordering information and documentation references are also provided for procuring the ACS30MS integrated circuit.
Optical lithography moved to shorter wavelengths like deep ultraviolet (DUV) due to limitations of mercury lamps. Excimer lasers emitting at wavelengths like 248nm and 193nm were adopted as they met the requirements of high photon energy and shorter wavelengths. As feature sizes continued shrinking, even shorter wavelengths like extreme ultraviolet (EUV) at 13.5nm were needed. EUV lithography uses reflective optics since materials absorb at this wavelength, and requires operating in vacuum since all materials absorb EUV radiation. Key challenges for EUV include developing high power radiation sources, improving reflective mirror lifetimes against contamination, and developing suitable photoresists with low line edge roughness.
Status of Advanced Substrates 2019 report by Yole DéveloppementYole Developpement
Demands from the new digital age are waking up the sleeping substrate giants.
More information on https://www.i-micronews.com/products/status-of-advanced-substrates-2019/
The new storage-class memory (SCM) category will be the biggest emerging NVM market, with embedded MCU seeking emerging NVM for strategic differentiation.
PCM leads the race to storage-class memory (SCM), but RRAM will catch up soon
In 2015, the Micron/Intel alliance presented a breakthrough stand-alone memory product called 3D Xpoint, developed in secret for many years, which uses PCM material instead of RRAM as we expected. Thus, after being down and out for a while, PCM made a big comeback in the emerging NVM race. This product has an amazingly high density for an emerging NVM (128 Gb), which is close to the latest NAND thanks to high node (20nm), a 3D crosspoint structure, and a good selector. We expect PCM will have the largest emerging NVM market share by 2021, thanks to its prominent promoters (Micron/Intel), which have sufficient influence to create a new SCM category using 3D Xpoint in the memory hierarchy. Indeed, creating a new memory category is a sea-change that will require numerous hardware and software developments by all memory ecosystem players. And while there is no general agreement, many experts believe DRAM sales will decrease due to SCM’s increased use. For this reason, many incumbent players, especially DRAM ones, have postponed their SCM product introduction in order to extend their DRAM profits, which over the last several years have been very high.
This document discusses ultra thin body SOI FETs. Some key points:
- SOI uses a thin silicon layer on an insulating substrate to reduce parasitic capacitance and improve performance over bulk silicon. Fully depleted SOI is preferred for its thin size and reduced leakage/power consumption.
- Benefits of SOI include lower capacitance, resistance to latch-up, higher performance at lower voltages, reduced temperature effects, better yields, and reduced leakage currents.
- Ultra thin body SOI FETs have even better gate control and mobility due to thin channel thickness, lower parasitic capacitance, and reduced leakage currents, making them useful for applications like memory, microelectronics, RF devices,
Epitaxy Growth Equipment for More Than Moore Devices Technology and Market Tr...Yole Developpement
Driven by microLED displays and power devices, epitaxy equipment shipment volumes will multiply more than threefold over the next five years.
More info on: https://www.i-micronews.com/products/epitaxy-growth-equipment-for-more-than-moore-devices-technology-and-market-trends-2020/
Bonding and Lithography Equipment Market for More than Moore Devices by Yole ...Yole Developpement
More than Moore devices fueled by megatrend applications will strongly drive the growth of the lithography, permanent bonding, and temporary bonding and debonding equipment market.
More information on that report at https://www.i-micronews.com/report/product/bonding-and-lithography-equipment-market-for-more-than-moore-devices.html
MO Exposure Optics (MOEO), is a novel mask aligner illumination system for all SUSS MicroTec Mask Aligners. Self-calibrating light source (no lamp alignment after lamp exchange), improved light uniformity, telecentric illumination and the possibility of freely shaping the angular spectrum are main advantages. Full control of the illumination allows to reduce diffraction effects, enhance resolution, improve CD uniformity and yield. It is now possible to fully simulate the lithography process by using LAB software from GenISys. Well known lithography techniques like customized illumination, optical proximity correction (OPC) and source-mask optimization (SMO) are now available for mask aligner lithography. Mask aligner lithography has entered a new era.
VCSELs – Market and Technology Trends 2019 by Yole DéveloppementYole Developpement
New functionalities in smartphone and automotive are boosting the VCSEL market.
More information on https://www.i-micronews.com/products/vcsels-market-and-technology-trends-2019/
Fan-Out and Embedded Die: Technologies & Market Trends 2015 Report by Yole De...Yole Developpement
Fan-Out and Embedded Die: Two promising Wafer/Panel-Level-Packaging technologies. What are the next steps for the growth?
Fan-Out Wafer Level Packaging is already in high-volume – but it’s about to grow even more strongly
Fan-Out Wafer Level Packaging (FOWLP) started volume commercialization in 2009/2010 and started promisingly, with initial push by Intel Mobile. However, it was limited to a narrow range of applications – essentially single die packages for cell phone baseband chips – reaching its limit in 2011. In 2012 big fab-less wireless/mobile players started slowly volume production after qualifying the technology...
This presentation summarizes silicon-on-insulator (SOI) devices and technologies. It discusses how SOI can achieve high performance and low power usage by placing a buried oxide layer between the silicon device layer and substrate. Key advantages of SOI include reduced junction capacitance, elimination of latchup, lower power consumption, and smaller die size. Various SOI fabrication techniques are presented, including SIMOX, BESOI, and Smart Cut. Current applications of SOI include microprocessors, networking, automotive, and emerging areas like FinFETs, optical waveguides, image sensors, and high voltage switching. SOI is predicted to be an important technology for continued scaling of CMOS to smaller nodes.
Lowering Production Cost of "Big MEMS (and Sensors)" Chip Technologies using ...INVIZA® HEALTH
Since the 1980’s microelectromechanical systems (“MEMS”) based devices have been manufactured primarily on round silicon (“Si”) substrates. This has been accomplished by primarily riding the “coattails” of the semiconductor (“SEMI”) integrated circuit chip industry, where Si substrate diameters have grown from less than 50 mm to 300 mm. As new larger diameter fabrication equipment was needed the previous generation tools (refurbished) were adopted by the MEMS industry at much lower price points.
Today, the SEMI industry has stalled at 300 mm, likewise the MEMS industry is mired at 200 mm diameter. The issue is that many MEMS chip dimensions can be large, greater than 10 x 10 mm^2 in area and can have expensive wafer-level packaging (“WLP”) utilized to protect its moving parts from inexpensive plastic molded packaging. When considering the $1 per mm^2 ‘rule of thumb’ for unyielded chip production cost, these “Big MEMS” chips are very difficult to fabricate cost effectively for their accompanying product market adoption.
Meanwhile over the last two decades of flat panel display (FPD) technology requirements have continued to increase in complexity and manufacturing capabilities. This includes increasing FPD resolution from today’s 4K to 8K and glass substrate size up to 3.1 x 3.1 m^2, a.k.a. ‘Generation 10 (Gen 10 or G10)’ glass. To achieve these challenging levels many manufacturing obstacles have had to be overcome, such as magnetron sputtering over large areas, including deposition thickness uniformity and optical property uniformity, the reduction of yield detractors, such as particles generated due to plasma arcing, and other process challenges.
What if the MEMS/sensor industry wasn’t restricted in substrate size, such as by utilizing G8 (2.1 x 2.4 m^2) or older (smaller area) fabrication equipment? Then, the chip cost could dramatically decrease.
Power GaN 2019: Epitaxy, Devices, Applications and Technology Trends - Yole D...Yole Developpement
First design-win for GaN HEMTs in the high-volume smartphone fast charging market.
More information on: https://www.i-micronews.com/products/power-gan-2019-epitaxy-devices-applications-technology-trends/
2.5D heterogeneous and 3D wafer-level stacking are reshaping the packaging landscape.
More information on that report at https://www.i-micronews.com/advanced-packaging-report/product/p2-5d-3d-tsv-wafer-level-stacking-technology-market-updates-2019.html
The document discusses 3D integrated circuits (3D ICs) and through-silicon vias (TSVs). It provides an overview of Yole Developpement, a research and consulting firm focused on advanced packaging. Yole analyzes trends in the semiconductor packaging industry and markets for 3D ICs. The document outlines several applications of 3D ICs and TSVs, including image sensors, memory, logic, and MEMS. It compares the benefits of 2D and 3D packaging approaches and provides timelines for adoption of technologies like TSVs across different applications.
The document describes the key steps in the semiconductor manufacturing process including silicon manufacturing using the Czochralski method, photolithography using photoresists and photomasks, and ion implantation. Photolithography involves coating wafers with photoresist, exposing it to light through a photomask, and developing the resist to transfer patterns. Ion implantation injects dopants by accelerating ions toward the wafer surface.
SOI Applications -- an overview and some examplesAdele Hars
This document provides an overview of SOI-based applications and examples. It discusses how SOI enables lower power, higher performance, and smaller, faster, cooler chips that can operate in harsh environments. Examples include the IBM Z13 mainframe and Casio G-Shock watches. FD-SOI is gaining traction with companies like STMicroelectronics, GlobalFoundries, and Samsung offering it. Applications discussed include automotive, Internet of Things, mobile, and more.
The document summarizes key steps in the fabrication of integrated circuits: thermal oxidation grows a silicon dioxide layer on the wafer for diffusion barriers and insulation; photolithography patterns the oxide layer using a mask, photoresist, and etching; dopant diffusion introduces impurities into the silicon by heating to allow movement; and metal evaporation deposits a thin aluminum film to connect components. These process steps are precisely controlled to build up the circuit structures layer-by-layer on the silicon wafer.
ASML Investor Day 2021-Technology Strategy - Martin van den Brink.pdfJoeSlow
- Moore's Law scaling of transistor and lithography density is expected to continue into the next decade, driven by innovations in lithography technology.
- While traditional metrics like clock frequency growth have saturated, other metrics like energy efficient performance that measure combined energy and time efficiency are still growing exponentially and expected to do so into the 2030s.
- System-level innovations involving new device architectures, 3D chip stacking, and other approaches will boost energy efficient performance beyond what transistor scaling alone provides, ensuring Moore's Law scaling continues at the system level.
Optical Lithography, Key Enabling Technology for our Modern WorldReinhard Voelkel
In 1959, Richard P. Feynman initiated the Nano-age in his lecture “There’s plenty of room at the bottom”. Feynman also had a clear vision about computers and asked: ”Why can’t we make them very small, make them of little wires, little elements - and by little, I mean little. For instance, the wires should be 10 or 100 atoms in diameter, and the circuits should be a few thousand angstroms across.”
At the same time, Jean Hoerni from Fairchild Semiconductors tried to get his “planar process” to production. Hoerni’s planar process using silicon substrates, so-called “wafers”, revolutionized semiconductor manufacturing and was widely adapted by the industry. The great success of the planar wafer process is also much related with tremendous improvements in optical lithography over all the years. From the early age dominated by mask aligners to highly sophisticated steppers and scanners, lithography was the key enabling technology, allowing now – 50 years after Feynman’s vision – nanostructuring down to the atomic scale on 300mm planar wafers. The evolutionary development of optical lithography is reviewed along with a brief discussion of options for the future.
The document provides technical information about components and schematics for Nokia mobile phone models NHM-5/UB 4 V09-V10. It includes diagrams of the radio frequency schematic, power levels and voltages for GSM 900 and 1800 bands. Tables list component locations on the printed circuit board by coordinates and component codes. The document is marked confidential and intended only for training and service purposes.
The document describes a radiation hardened 8-input NAND gate called the ACS30MS that is qualified for use in military and aerospace applications. It provides details on the device's features such as its radiation tolerance, input/output specifications, and packaging options. Ordering information and documentation references are also provided for procuring the ACS30MS integrated circuit.
There is today more than 20 years of experience in automotive CAN applications, and CAN has certainly proven very successful as a robust, cost effective and all-around network technology. But the use of CAN in vehicles is evolving, in particular because of more complex and heterogeneous architectures with FlexRay or Ethernet networks, and because of recent needs like hybrid, electric propulsion or driver assistance that involves more stringent real-time constraints. Besides, there are other new requirements on CAN: more fine-grained ECU mode management for energy savings, multi-ECU splitted functions and huge software downloads. In parallel, safety issues request more and more mechanisms to protect against potential failures and provide end-to-end integrity. The development process is also evolving with the advent of multi-domain cooperation, Autosar, ISO2626-2 and the always shorter time-to-market requirements. In this landscape, CAN has now to be used at much higher bus load level than in the past, and there is less margin for error. What does it imply in terms of verification and validation? What are the characteristics of the communication stacks that should be paid attention to? This article is intended to shed some light and share our views on these issues.
ASML reported strong financial results for the second quarter of 2010, with record gross margin and operating margin. Total sales increased to €1.069 billion, up 43% year-over-year. Backlog also reached a record high of €2.401 billion, reflecting increasing demand for semiconductor manufacturing equipment. Looking forward, ASML expects semiconductor fab spending to continue rising in 2010 and 2011 as the industry transitions to smaller node sizes, requiring significantly more immersion lithography tools.
NEWCON OPTIK - Night Vision, Laser Range Finders, Thermal, Stabilized Imagers, Binoculars, Goggles, Monoculars, Night Vision Scopes by Newcon Optik
Newcon Optik didirikan dengan tujuan untuk memproduksi dan memasok pasar dengan sistem optik state-of-the-art, yang berbasis di Kanada, R & D dan manufaktur dan distribusi di seluruh dunia. Dengan kemampuan manufaktur dan R & D, standar tertinggi dari kualitas dan kepuasan pelanggan menjadi jaminan. Harga kompetitif dan faktor kunci sukses lainnya telah membuat Newcon Optik diterima di pasar internasional.
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1. Deutsche Bank
2007 Technology Conference
London
Franki D’Hoore
Director Investor Relations
14 September, 2007
<file name>
/ Slide 1 <version 00>
<author>
2. Safe Harbor
“Safe Harbor” Statement under the U.S. Private Securities
Litigation Reform Act of 1995: the matters discussed in this
document may include forward-looking statements that are
subject to risks and uncertainties including, but not limited to:
economic conditions, product demand and semiconductor
equipment industry capacity, worldwide demand and
manufacturing capacity utilization for semiconductors (the
principal product of our customer base), competitive products
and pricing, manufacturing efficiencies, new product
development, ability to enforce patents, the outcome of
intellectual property litigation, availability of raw materials and
critical manufacturing equipment, trade environment, and other
risks indicated in the risk factors included in ASML’s Annual
Report on Form 20-F and other filings with the U.S. Securities
and Exchange Commission.
/ Slide 2
3. ASML overview - The world’s leading provider of
lithography systems for the semiconductor industry
Ranked in the top 3 for
Key facts
Established: 1984 customer satisfaction for the
5th consecutive year
Headquarters: Veldhoven, the Netherlands
Market cap ~ €10 B
Employees ~ 6,200
Customers: Serving 17 of the top 20 semi mfg.
Equity Listing: Nasdaq and Euronext
Leaders in Innovation
Key financials ASML TWINSCAN
€ million 2005 2006 H1 2007
Market share (based on revenue) 57% 63% 66%
Net sales 2,529 3,597 1895
Gross profit 974 1,462 777
EBIT 449 871 405
/ Slide 3
4. Industry growth drives Lithography tool
consumption - NAND Flash fastest growing
60
Segment size:
20 Bio. US$
Exposure area 2006 [SI*10^9]
50
LOGIC
40
DRAM
30
MICRO
ANALOG
20
NAND
10
NOR Other
0
0 5 10 15 20 25 30
CAGR Exposure Area 06-09 [%]
Sources: ASML MCC, VLSI Research, iSuppli, SIA
/ Slide 4
7. ASML TWINSCAN™ Product Specifications
λ System Res. 300mm Throughput [WPH) & Overlay Roadmap
Next <40nm >131 <6nm
ArFi XT:1900 40nm G 131 , 6nm
193nm
XT:1700i 45nm F 122 , 7nm
XT:1450 57nm G 145 , 6nm
ArF XT:1400 65nm F 133 , 6nm
193nm
XT:1250 70nm D 120 , 8nm Continuous
Improvement
XT:1000 80nm H 165 , 6nm
KrF XT:875 90nm F 135 , 8nm G 150 , 6nm
248nm XT:870 110nm F 135 , 8nm G 150 , 6nm
XT:760 130nm F 130 , 12nm
XT:450 220nm F 131 ,12nm G 141 ,12nm
i-Line
XT:400 350nm F 135 ,25nm G 149 ,25nm
365nm
2006 2007 2008 2009 2010 2011
Year
/ Slide 7
8. ASML roadmap enables shrink for Logic, DRAM,
and NAND flash at time required
200
Resolution/half pitch “Shrink” [nm]
Logic Litho technology
k1=0.4 DRAM
will allow Logic
to shrink
100 AT:850
NAND
80 AT:1200
k1=0.27
To enable
XT:1400
60 continued
R&D
shrink for
XT:1700i
memory: EUV is
XT:1900i
needed, Double
40 ASML Product Patterning to
XT:1450
Introduction R&D bridge gap until
Double
Patterning EUV mature
00 01 02 03 04 05 06 07 08 09 10 11 12
Year
Source: Various customers, dates determine production start/qualification
/ Slide 8
9. Technology in Time helps grow market share
ASML market share (revenue) – Nearly tripled in 10 years
Immersion
12” & ArF
80%
KrF & Step & Scan
8” & i-line
60%
6” & early i-line
40%
20%
0%
84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06
1984 2006
Perkin Elmer Canon
16%
Canon
GCA ASML
Nikon
63%
Ultratech
21%
Eaton
Nikon
ASET
Hitachi
Total market: €4,800 million
Total market: €463 million
Source: SEMI, Gartner Dataquest
/ Slide 9
10. Immersion - Leadership continues
Over 50 systems shipped to date to all applications and
geographies in the world
25 immersion machines in backlog valued at € 728 M
Received repeat orders from major Japanese customers
including multiple XT:1900i machines
ASML plans to ship about 35 immersion machines in 2007
Backlog in value
ArF Immersion
ArF dry 37 % is 42% of
backlog
KrF 15%
i-line 6%
/ Slide 10
11. First TWINSCAN XT:1900i shipped on schedule early July
First tool in the world capable of printing features below 40 nm
in volume production
/ Slide 11
12. Exposed wafers (x1000)
1000
1500
2000
2500
0
500
Jan-05
Feb-05
/ Slide 12
Mar-05
Apr-05
May-05
Jun-05
cumulative
Jul-05
Aug-05
Sep-05
Oct-05
Nov-05
Dec-05
Jan-06
Feb-06
Mar-06
Apr-06
May-06
Jun-06
Jul-06
Aug-06
Sep-06
Oct-06
Nov-06
Dec-06
Jan-07
Wafers exposed on ASML immersion equipment
Feb-07
Mar-07
Over 2 Million wafers processed on ASML immersion
systems with steep production ramp since April 2007
Apr-07
May-07
Jun-07
13. The layout designers draw, is not quite what gets printed
by scanners
180nm
130nm
90nm
65nm
/ Slide 13
14. Why is this happening? Because the litho
process is not an error-free transfer function
H≠1
Mask-writing Wafer exposure Resist development Etch
/ Slide 14
15. What can we do about it? Software
compensation for the distortion
~1/H H
… … …
/ Slide 15
16. In practice…
Silicon Image w/o correction
Mask
(no correction)
Design Layout
Mask Silicon Image with
(with correction, RET/OPC
or “RET/OPC”)
/ Slide 16
17. What does Brion do?
H≠1
Mask-writing Wafer exposure Resist development Etch
Accurate mathematical model of “H”
Simulated wafer,
Designers drawing before you print anything
/ Slide 17
18. With an accurate mathematical model of H, we
can do two things:
Brion’s Tachyon
OPC+ product line
i.e. Approximate 1/H
Compensate
on design
Scanner tuning
Compensate
i.e. Find H’ so distortion is less
on scanner
and/or easier to compensate for
/ Slide 18
19. Through accurate model, we can fine tune many
system settings for optimum exposure of each device
pattern, reticle & wafer
Illuminator
Illuminator
Laser
Laser
Sigma
Pupicom
Bandwidth
PSEs
DOEs
Dose
Stages
Stages
Unicom
Etc.
Focus
Tilt X
Tilt Y Lens
Lens
Reticle height
Synchronization NA
Manipulators
/ Slide 19
20. Synergies of owning the scanner and the litho
model for scanner-tuning
System setting ranges : Optimum system settings :
NA range
NA
Illumination option/ranges standard & custom
Illumination setting (standard, custom)
DoseMapper correction range
Focus, Dose settings
etc.
etc.
Actual system data
Lens heating characteristics Real time system optimisation :
Aberration data
Lens manipulator settings
Stray light
Exposure dose & DoseMapper offsets
Laser bandwidth
Focus & tilt by shot / wafer
etc.
Laser bandwidth
Wafer metrology & exposure data:
Alignment & wafer grid offsets / field/wafer
Focus & Leveling & focus hot spot data
Dose error, Laser data Other
etc.
/ Slide 20
21. The holy-grail of optimisation: today, only ASML
can do this
Non - Optimized Optimized
Scanner (e.g. Illumination)
Optimize both
the scanner and
the mask,
together, as a
unified
Mask
optimization
problem
Top-down
photoresist
/ Slide 21
22. With Brion, ASML now can… (1/2)
Leverage a whole new dimension of possibilities for
optimizing imaging performance (mask optimization,
RET/OPC) as an integral part of its solution package
Use an accurate model of the lithography process to
tune the dozens of scanner knobs available so to further
optimize imaging performance (scanner tuning)
Through the two points above, enable faster shrink and
higher yield for our customers
/ Slide 22
23. With Brion, ASML now can… (2/2)
Further secure the ArF roadmap until EUV is ready
Prevent value-migration to EDA by capturing software
solutions to printability
Penetrate a new and growing market at the interface
with EDA, capturing new value streams and enabling
growth beyond “hardware”
/ Slide 23
28. ASML Competitive Advantage
2.00
Pixels per Hour per Million Euro
ASML ArF
1.75 Competition ArF
ASML ArFi
1.50
Competition ArFi
1.25
1.00
0.75
0.50
0.25
0.00
2004 2005 2006 2007 2008
/ Slide 28
29. Summary
Shrinking design rules have been the economical driver of the IC
industry. Lithography remains the key enabler
Providing the right product at the right time allows market share
gains for ASML
Shrinking design rules require increasingly more sophisticated
lithography systems resulting in a steady growth in their cost and
resulting ASP’s
ASML insures that the increasing cost of advanced lithography
systems remain acceptable by developing solutions that result in
maximum usable shrink while driving increased productivity to
ensure steady improvement in cost per function
Future lithography technologies will likely ensure that the economics
of shrink will remain attractive for at least several more generations
/ Slide 29