This document summarizes a metal oxide TFT manufacturing process that can be used on existing amorphous silicon (a-Si) TFT lines with minimal equipment upgrades. The process uses the same silicon nitride gate insulator deposition and wet back channel etch steps as a-Si TFT production. It deposits a proprietary metal oxide semiconductor channel layer by sputtering without oxygen, enabling high mobility and uniformity. The metal oxide TFTs exhibit excellent stability, meeting requirements for next-generation LCD and OLED displays. They can be manufactured on a-Si TFT lines at low cost, providing a competitive advantage over incumbent a-Si and poly-Si TFT technologies.
This document provides an overview of using steel slags in cementitious applications. It discusses the diversity of steel slags produced and the importance of sorting. Steel slags can be used as a raw feed material in cement production, providing benefits like reduced CO2 emissions but also challenges like chromium content. Steel slags can also be used as a hydraulic component in cement if processed through methods like granulation or oxidizing treatments to enhance reactivity. Standards for use in cement, concrete and other construction applications are also addressed.
Challenges for Concrete. Presenterat av professor Karen Scrivener, vinnare av Swedish Concrete Award 2015, på Träffpunkt Betong 15 den 7 oktober i Stockholm.
IRJET- Influence of Coal Tar Epoxy Paint on Concrete Exposed to Sulfate E...IRJET Journal
The document discusses a study on the influence of coal tar epoxy paint on concrete exposed to sulfate exposure. Concrete specimens with and without coal tar epoxy paint coating were exposed to 4% Na2SO4 solution for 12 months. The study found that concrete with coal tar epoxy paint coating showed excellent resistance to sulfate attack compared to uncoated concrete. Even concrete made with pozzolanic materials like fly ash and GGBS showed more damage than concrete with a coal tar epoxy paint surface coating. The coal tar epoxy paint effectively protected the concrete from sulfate ingress and attack.
Orthographic projection is a technique where the object is projected onto planes perpendicular to the lines of sight to create 2D views from the front, side, and top. It shows the object as it would look from those directions. The views are typically positioned according to first or third angle projection rules. Orthographic projection uses parallel lines of sight perpendicular to the projection plane to create multi-view drawings of 3D objects.
Nanocrystalline silicon thin film transistor (nc si h tf-ts)-a deviceIAEME Publication
This document discusses nanocrystalline silicon thin film transistors (nc-Si:H TFTs) for use in display panels. It provides an overview of nc-Si:H TFT technology, including the transistor structure, operation, materials used, and performance characteristics. Nc-Si:H TFTs have higher mobility than amorphous silicon TFTs due to the presence of silicon crystallites, but lower off-currents than polycrystalline silicon TFTs. Nc-Si:H TFTs can be deposited at low temperatures similar to amorphous silicon, but have improved stability and uniformity over large areas compared to polycrystalline silicon TFTs. The document
Fabrication and Analysis of Amorphous Silicon TFT IJECEIAES
The display technology and large area electronics got momentum with the introduction of TFT devices. TFTs can be made using different semiconducting materials or organic conducting materials as the active layer. Each one of them differs in their performance depending on the material used for the active layer. In this paper, fabrication of amorphous silicon TFT using PECVD is carried out. Simulation of the a-Si: H TFT is also carried out with the dimensions similar to that of the masks used for the fabrication. The Id -V d plot for both the simulation and fabrication is obtained and studied.
This document provides an overview of using steel slags in cementitious applications. It discusses the diversity of steel slags produced and the importance of sorting. Steel slags can be used as a raw feed material in cement production, providing benefits like reduced CO2 emissions but also challenges like chromium content. Steel slags can also be used as a hydraulic component in cement if processed through methods like granulation or oxidizing treatments to enhance reactivity. Standards for use in cement, concrete and other construction applications are also addressed.
Challenges for Concrete. Presenterat av professor Karen Scrivener, vinnare av Swedish Concrete Award 2015, på Träffpunkt Betong 15 den 7 oktober i Stockholm.
IRJET- Influence of Coal Tar Epoxy Paint on Concrete Exposed to Sulfate E...IRJET Journal
The document discusses a study on the influence of coal tar epoxy paint on concrete exposed to sulfate exposure. Concrete specimens with and without coal tar epoxy paint coating were exposed to 4% Na2SO4 solution for 12 months. The study found that concrete with coal tar epoxy paint coating showed excellent resistance to sulfate attack compared to uncoated concrete. Even concrete made with pozzolanic materials like fly ash and GGBS showed more damage than concrete with a coal tar epoxy paint surface coating. The coal tar epoxy paint effectively protected the concrete from sulfate ingress and attack.
Orthographic projection is a technique where the object is projected onto planes perpendicular to the lines of sight to create 2D views from the front, side, and top. It shows the object as it would look from those directions. The views are typically positioned according to first or third angle projection rules. Orthographic projection uses parallel lines of sight perpendicular to the projection plane to create multi-view drawings of 3D objects.
Nanocrystalline silicon thin film transistor (nc si h tf-ts)-a deviceIAEME Publication
This document discusses nanocrystalline silicon thin film transistors (nc-Si:H TFTs) for use in display panels. It provides an overview of nc-Si:H TFT technology, including the transistor structure, operation, materials used, and performance characteristics. Nc-Si:H TFTs have higher mobility than amorphous silicon TFTs due to the presence of silicon crystallites, but lower off-currents than polycrystalline silicon TFTs. Nc-Si:H TFTs can be deposited at low temperatures similar to amorphous silicon, but have improved stability and uniformity over large areas compared to polycrystalline silicon TFTs. The document
Fabrication and Analysis of Amorphous Silicon TFT IJECEIAES
The display technology and large area electronics got momentum with the introduction of TFT devices. TFTs can be made using different semiconducting materials or organic conducting materials as the active layer. Each one of them differs in their performance depending on the material used for the active layer. In this paper, fabrication of amorphous silicon TFT using PECVD is carried out. Simulation of the a-Si: H TFT is also carried out with the dimensions similar to that of the masks used for the fabrication. The Id -V d plot for both the simulation and fabrication is obtained and studied.
COMPARISON OF DUAL SOURCE TFET USING DIFFERENT DIELECTRIC MATERIALSIRJET Journal
This document compares the performance of a dual source tunnel field-effect transistor (TFET) using different dielectric materials, including hafnium dioxide (HfO2), silicon dioxide (SiO2), and silicon nitride (Si3N4). It analyzes the structure, operation, and simulation results of each TFET design. The key findings are that HfO2, with its higher dielectric constant, provides better performance than SiO2 and Si3N4 by increasing the on current and decreasing the off current, leading to an improved on/off current ratio. Using high-k dielectric materials like HfO2 in TFETs can enable lower power consumption and increased thermal stability.
Dielectric Q-V Measurements using COS techniqueMichael Shifrin
This document discusses thin dielectric layer characterization using a corona-oxide-semiconductor (COS) measurement technique. Specifically, it evaluates using a Quantox measurement system to characterize various thin film dielectric stacks, including single layers and stacks of materials like fluorinated silicon glass (FSG). The goals are to determine properties like dielectric constant and compare COS results to other techniques like ellipsometry and Fourier transform infrared spectroscopy (FTIR). COS has advantages over traditional metal-oxide-semiconductor (MOS) capacitor measurements by not requiring device fabrication and allowing for direct, contactless measurements on dielectric films.
A durable and flexible display with low-power consumption, high-contrast ratio, has been a technical challenge for years. They have to be lightweight, rugged, and in some cases, conformal, wearable, rollable and unbreakable. The recent successful integration of flexible display technologies and the traditional web-based processing and/or inkjet technologies has opened up the possibility of low cost and high throughput roll-to-roll manufacturing and has shown the potential to replace the paper used today.
1. The document describes vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOSFETs) fabricated using a substrate transfer silicon-on-glass technology.
2. Key characteristics of the fabricated VDMOSFETs include a breakdown voltage of nearly 100V, an fT/fmax of 6/10 GHz, high power gain of 14 dB at 2 GHz, and excellent linearity with an IM3 below -50 dBc at 10 dB back-off.
3. The substrate transfer process allows elimination of source lead inductance issues and excellent heat dissipation, ensuring good thermal stability and long-term reliability of the high-performance VDMOSFET
The document provides an overview of an ECE5307 course on VLSI design. It discusses integrated circuits and CMOS technology. It covers the VLSI design process including behavioral, structural, and layout representations. Design approaches like full custom and semi-custom styles are compared. Fabrication process steps like oxidation, lithography, and metallization are outlined. Stick diagrams are introduced as a way to represent circuit layout using different colors or lines for layers like polysilicon and diffusion. Key rules for drawing stick diagrams are provided.
Atomization of reduced graphene oxide ultra thin film for transparent electro...Conference Papers
This document summarizes research on using an atomization process to deposit reduced graphene oxide (rGO) thin films for use as transparent conductive electrodes. Key points:
- Graphene oxide was spray coated onto silicon wafers and glass slides using an ultrasonic atomizer. Thermal reduction processes were then used to make the films electrically conductive while maintaining optical transparency.
- Thinner films with 1-2 spray coats had higher transparency (>90%) but higher resistivity, while thicker 3-4 coat films had lower transparency (77.1%) but lower resistivity (5.3 kΩ/sq).
- Rapid thermal processing was more effective than plasma processing at reducing resistivity. Sheet resistance decreased
Atomization of reduced graphene oxide ultra thin film for transparent electro...Conference Papers
This document summarizes research on using an atomization process to deposit reduced graphene oxide (rGO) thin films for use as transparent conductive electrodes. Key points:
- Graphene oxide was spray coated onto silicon wafers and glass slides using an ultrasonic atomizer. Thermal reduction processes were then used to make the films electrically conductive while maintaining optical transparency.
- Thinner films with 1-2 spray coats had higher transparency (>90%) but higher resistivity, while thicker 3-4 coat films had lower transparency (77.1%) but lower resistivity (5.3 kΩ/sq).
- Rapid thermal processing was more effective than plasma processing at reducing resistivity. Sheet resistance decreased
IRJET - A Review on the Hysteretic Effects on Thin Film TransistorsIRJET Journal
1) The document reviews hysteresis effects on thin film transistors (TFTs), specifically polycrystalline silicon TFTs. Hysteresis refers to a lag between input and output in a system and can cause permanent memory effects.
2) Testing showed that the threshold voltage of poly-Si TFTs varied depending on the direction of the gate voltage sweep (forward or reverse) due to trapped charges in the gate insulator, an example of hysteresis.
3) The hysteresis was less for poly-Si TFTs than amorphous silicon TFTs due to better gate insulator quality in poly-Si TFTs, but still caused a 0.21V difference in threshold
The document discusses a presentation given by Ashish Kumar Singh on his research investigating heterojunction silicon-on-insulator tunnel field effect transistors. The presentation outline includes an introduction discussing challenges with MOSFET scaling, the history and state-of-the-art of TFET research, the basic structure and operation of TFETs, investigations of Ge-source/Si strained SOI TFETs, a proposed Ge-source SOI TFET with oxide overlap, analytical modeling of the proposed device, conclusions and future work.
IRJET- Simulation of High K Dielectric MOS with HFo2 as a Gate DielectricIRJET Journal
This document discusses the simulation of a MOSFET device using HfO2 as the high-k gate dielectric material. It begins with an introduction to the need for high-k dielectrics to replace silicon dioxide as traditional MOSFETs continue to scale down. HfO2 is identified as a promising high-k material due to its high dielectric constant. The document then outlines the process steps to simulate an HfO2-based MOSFET using Silvaco simulation software. Key steps include depositing an HfO2 layer, doping the source and drain, and depositing metal contacts. A comparison is made between traditional MOSFETs and high-k MOSFETs, showing
The document summarizes the key steps in integrated circuit (IC) fabrication and technologies. It discusses the major fabrication processes including wafer preparation, oxidation, photolithography, diffusion, etching, deposition, ion implantation, encapsulation, metallization, and packaging. It also reviews enhancement and depletion MOS transistors and compares NMOS, PMOS, and CMOS technologies. Finally, it provides an overview of the basic MOSFET construction and operation.
This document describes a simple method for creating patterned SiO2/TiO2 films through photo and chemical reactions at room temperature. TiO2 films are patterned using UV light and a photosensitive organic-titanium solution. SiO2 particles are precipitated from silicate solution by adjusting the pH, which are then deposited on the TiO2 films due to attraction between TiO2 and SiO2 surfaces. The films are characterized using SEM and EDS, showing uniform deposition of SiO2 crystals on TiO2. The SiO2 films are further modified with amino groups using aminosilane to enable protein immobilization applications.
What is CAF?
A growth consisting of a conductive copper-containing salt. It is created electrochemically and grows from the anode toward the cathode subsurface along the epoxy/glass interface.
Conductive Anodic Filament (CAF) formation does happen
o When it happens, it can cause a lot of pain
CAF behavior is relatively stable
o Limited change in key PCB technology (pitch, materials,
assembly)
CAF mitigation is well known (execute it!)
o Evaluate your designs
o Qualify your suppliers
This document discusses transparent electronic devices based on zinc oxide (ZnO), including ZnO thin-film transistors (TFTs), Schottky diodes, and metal-semiconductor field-effect transistors (MESFETs). It also describes new applications using these devices, such as for display technology and transparent integrated circuits. Finally, it presents ZnO-based planar nano-devices fabricated using electron beam lithography and wet etching, including self-switching diodes and side-gated transistors that could enable ultra-fast logic circuits.
1. Fully Depleted Silicon On Insulator (FD-SOI) is an innovation that uses an ultra-thin silicon film and buried oxide layer to improve transistor performance and reduce leakage currents.
2. By using a thin buried oxide and silicon film, FD-SOI allows the depletion region to cover the entire film, improving electrostatic characteristics and reducing parasitic capacitance compared to bulk transistors.
3. The improvements allow FD-SOI transistors to operate faster at lower voltages while significantly reducing leakage currents and improving power efficiency through improved body biasing controls.
Flexible electronics is a new technology that uses flexible plastic substrates to assemble electronic circuits. This allows electronics to be lightweight, robust, high density, and conformable. Flexible circuits can be rolled up when not in use. There are several manufacturing techniques for flexible electronics including using polymers like PDMS and conducting adhesives. Applications include displays, solar cells, smart textiles, electronic paper, and healthcare devices. However, challenges remain regarding electrical stability, flexible substrate handling, and flexible conductor properties. The future of flexible electronics is promising with a growing market expected to reach $300 billion by 2028 as the technology enables new applications.
Patented way to create Silicon Controlled Rectifiers in SOI technology Sofics
This paper introduces an SCR based ESD protection design for SOI technologies. It is explained how efficient SCR devices can be constructed in SOI. These devices outperform MOS devices by about 4 times.
Experimental data from 65nm and 130nm SOI is presented to support this.
HIGH-K DEVICES BY ALD FOR SEMICONDUCTOR APPLICATIONSJonas Sundqvist
This document summarizes research on high-k dielectric devices fabricated using atomic layer deposition (ALD) for semiconductor applications presented by researchers from the Fraunhofer Institute for Photonic Microsystems. It discusses the history of ALD deposition of high-k materials like TiO2 and laminates of Ta2O5 and HfO2 for capacitor applications in the 1990s. It also summarizes the development of TiN/ZrO2-based capacitors and research on ALD HfO2 for emerging ferroelectric memory devices. Finally, it discusses the fabrication of 3D capacitor structures using ALD with densities over 250 nF/mm2 and possibilities for 3D integration of ferroelectric HfO2
This term presentation was submitted as a partial requirement for the course: MSE 507: Advanced micro-fabrication with CAD (TSUPREM4). In this presentation, the fabrication process of 3D FINFET transistor has been presented in accordance with US patent (Patent no. US 7,973,389 B2, assignee: Intel Corporation, Santa Clara, CA, US) using Shallow Trench Isolation (STI) method.
COMPARISON OF DUAL SOURCE TFET USING DIFFERENT DIELECTRIC MATERIALSIRJET Journal
This document compares the performance of a dual source tunnel field-effect transistor (TFET) using different dielectric materials, including hafnium dioxide (HfO2), silicon dioxide (SiO2), and silicon nitride (Si3N4). It analyzes the structure, operation, and simulation results of each TFET design. The key findings are that HfO2, with its higher dielectric constant, provides better performance than SiO2 and Si3N4 by increasing the on current and decreasing the off current, leading to an improved on/off current ratio. Using high-k dielectric materials like HfO2 in TFETs can enable lower power consumption and increased thermal stability.
Dielectric Q-V Measurements using COS techniqueMichael Shifrin
This document discusses thin dielectric layer characterization using a corona-oxide-semiconductor (COS) measurement technique. Specifically, it evaluates using a Quantox measurement system to characterize various thin film dielectric stacks, including single layers and stacks of materials like fluorinated silicon glass (FSG). The goals are to determine properties like dielectric constant and compare COS results to other techniques like ellipsometry and Fourier transform infrared spectroscopy (FTIR). COS has advantages over traditional metal-oxide-semiconductor (MOS) capacitor measurements by not requiring device fabrication and allowing for direct, contactless measurements on dielectric films.
A durable and flexible display with low-power consumption, high-contrast ratio, has been a technical challenge for years. They have to be lightweight, rugged, and in some cases, conformal, wearable, rollable and unbreakable. The recent successful integration of flexible display technologies and the traditional web-based processing and/or inkjet technologies has opened up the possibility of low cost and high throughput roll-to-roll manufacturing and has shown the potential to replace the paper used today.
1. The document describes vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOSFETs) fabricated using a substrate transfer silicon-on-glass technology.
2. Key characteristics of the fabricated VDMOSFETs include a breakdown voltage of nearly 100V, an fT/fmax of 6/10 GHz, high power gain of 14 dB at 2 GHz, and excellent linearity with an IM3 below -50 dBc at 10 dB back-off.
3. The substrate transfer process allows elimination of source lead inductance issues and excellent heat dissipation, ensuring good thermal stability and long-term reliability of the high-performance VDMOSFET
The document provides an overview of an ECE5307 course on VLSI design. It discusses integrated circuits and CMOS technology. It covers the VLSI design process including behavioral, structural, and layout representations. Design approaches like full custom and semi-custom styles are compared. Fabrication process steps like oxidation, lithography, and metallization are outlined. Stick diagrams are introduced as a way to represent circuit layout using different colors or lines for layers like polysilicon and diffusion. Key rules for drawing stick diagrams are provided.
Atomization of reduced graphene oxide ultra thin film for transparent electro...Conference Papers
This document summarizes research on using an atomization process to deposit reduced graphene oxide (rGO) thin films for use as transparent conductive electrodes. Key points:
- Graphene oxide was spray coated onto silicon wafers and glass slides using an ultrasonic atomizer. Thermal reduction processes were then used to make the films electrically conductive while maintaining optical transparency.
- Thinner films with 1-2 spray coats had higher transparency (>90%) but higher resistivity, while thicker 3-4 coat films had lower transparency (77.1%) but lower resistivity (5.3 kΩ/sq).
- Rapid thermal processing was more effective than plasma processing at reducing resistivity. Sheet resistance decreased
Atomization of reduced graphene oxide ultra thin film for transparent electro...Conference Papers
This document summarizes research on using an atomization process to deposit reduced graphene oxide (rGO) thin films for use as transparent conductive electrodes. Key points:
- Graphene oxide was spray coated onto silicon wafers and glass slides using an ultrasonic atomizer. Thermal reduction processes were then used to make the films electrically conductive while maintaining optical transparency.
- Thinner films with 1-2 spray coats had higher transparency (>90%) but higher resistivity, while thicker 3-4 coat films had lower transparency (77.1%) but lower resistivity (5.3 kΩ/sq).
- Rapid thermal processing was more effective than plasma processing at reducing resistivity. Sheet resistance decreased
IRJET - A Review on the Hysteretic Effects on Thin Film TransistorsIRJET Journal
1) The document reviews hysteresis effects on thin film transistors (TFTs), specifically polycrystalline silicon TFTs. Hysteresis refers to a lag between input and output in a system and can cause permanent memory effects.
2) Testing showed that the threshold voltage of poly-Si TFTs varied depending on the direction of the gate voltage sweep (forward or reverse) due to trapped charges in the gate insulator, an example of hysteresis.
3) The hysteresis was less for poly-Si TFTs than amorphous silicon TFTs due to better gate insulator quality in poly-Si TFTs, but still caused a 0.21V difference in threshold
The document discusses a presentation given by Ashish Kumar Singh on his research investigating heterojunction silicon-on-insulator tunnel field effect transistors. The presentation outline includes an introduction discussing challenges with MOSFET scaling, the history and state-of-the-art of TFET research, the basic structure and operation of TFETs, investigations of Ge-source/Si strained SOI TFETs, a proposed Ge-source SOI TFET with oxide overlap, analytical modeling of the proposed device, conclusions and future work.
IRJET- Simulation of High K Dielectric MOS with HFo2 as a Gate DielectricIRJET Journal
This document discusses the simulation of a MOSFET device using HfO2 as the high-k gate dielectric material. It begins with an introduction to the need for high-k dielectrics to replace silicon dioxide as traditional MOSFETs continue to scale down. HfO2 is identified as a promising high-k material due to its high dielectric constant. The document then outlines the process steps to simulate an HfO2-based MOSFET using Silvaco simulation software. Key steps include depositing an HfO2 layer, doping the source and drain, and depositing metal contacts. A comparison is made between traditional MOSFETs and high-k MOSFETs, showing
The document summarizes the key steps in integrated circuit (IC) fabrication and technologies. It discusses the major fabrication processes including wafer preparation, oxidation, photolithography, diffusion, etching, deposition, ion implantation, encapsulation, metallization, and packaging. It also reviews enhancement and depletion MOS transistors and compares NMOS, PMOS, and CMOS technologies. Finally, it provides an overview of the basic MOSFET construction and operation.
This document describes a simple method for creating patterned SiO2/TiO2 films through photo and chemical reactions at room temperature. TiO2 films are patterned using UV light and a photosensitive organic-titanium solution. SiO2 particles are precipitated from silicate solution by adjusting the pH, which are then deposited on the TiO2 films due to attraction between TiO2 and SiO2 surfaces. The films are characterized using SEM and EDS, showing uniform deposition of SiO2 crystals on TiO2. The SiO2 films are further modified with amino groups using aminosilane to enable protein immobilization applications.
What is CAF?
A growth consisting of a conductive copper-containing salt. It is created electrochemically and grows from the anode toward the cathode subsurface along the epoxy/glass interface.
Conductive Anodic Filament (CAF) formation does happen
o When it happens, it can cause a lot of pain
CAF behavior is relatively stable
o Limited change in key PCB technology (pitch, materials,
assembly)
CAF mitigation is well known (execute it!)
o Evaluate your designs
o Qualify your suppliers
This document discusses transparent electronic devices based on zinc oxide (ZnO), including ZnO thin-film transistors (TFTs), Schottky diodes, and metal-semiconductor field-effect transistors (MESFETs). It also describes new applications using these devices, such as for display technology and transparent integrated circuits. Finally, it presents ZnO-based planar nano-devices fabricated using electron beam lithography and wet etching, including self-switching diodes and side-gated transistors that could enable ultra-fast logic circuits.
1. Fully Depleted Silicon On Insulator (FD-SOI) is an innovation that uses an ultra-thin silicon film and buried oxide layer to improve transistor performance and reduce leakage currents.
2. By using a thin buried oxide and silicon film, FD-SOI allows the depletion region to cover the entire film, improving electrostatic characteristics and reducing parasitic capacitance compared to bulk transistors.
3. The improvements allow FD-SOI transistors to operate faster at lower voltages while significantly reducing leakage currents and improving power efficiency through improved body biasing controls.
Flexible electronics is a new technology that uses flexible plastic substrates to assemble electronic circuits. This allows electronics to be lightweight, robust, high density, and conformable. Flexible circuits can be rolled up when not in use. There are several manufacturing techniques for flexible electronics including using polymers like PDMS and conducting adhesives. Applications include displays, solar cells, smart textiles, electronic paper, and healthcare devices. However, challenges remain regarding electrical stability, flexible substrate handling, and flexible conductor properties. The future of flexible electronics is promising with a growing market expected to reach $300 billion by 2028 as the technology enables new applications.
Patented way to create Silicon Controlled Rectifiers in SOI technology Sofics
This paper introduces an SCR based ESD protection design for SOI technologies. It is explained how efficient SCR devices can be constructed in SOI. These devices outperform MOS devices by about 4 times.
Experimental data from 65nm and 130nm SOI is presented to support this.
HIGH-K DEVICES BY ALD FOR SEMICONDUCTOR APPLICATIONSJonas Sundqvist
This document summarizes research on high-k dielectric devices fabricated using atomic layer deposition (ALD) for semiconductor applications presented by researchers from the Fraunhofer Institute for Photonic Microsystems. It discusses the history of ALD deposition of high-k materials like TiO2 and laminates of Ta2O5 and HfO2 for capacitor applications in the 1990s. It also summarizes the development of TiN/ZrO2-based capacitors and research on ALD HfO2 for emerging ferroelectric memory devices. Finally, it discusses the fabrication of 3D capacitor structures using ALD with densities over 250 nF/mm2 and possibilities for 3D integration of ferroelectric HfO2
This term presentation was submitted as a partial requirement for the course: MSE 507: Advanced micro-fabrication with CAD (TSUPREM4). In this presentation, the fabrication process of 3D FINFET transistor has been presented in accordance with US patent (Patent no. US 7,973,389 B2, assignee: Intel Corporation, Santa Clara, CA, US) using Shallow Trench Isolation (STI) method.
2. wet etchants such as PAN (mixture of phosphoric, acetic and
nitric acids) or copper etchants during S/D etching. At the same
time, the channel layer also becomes highly tolerant of hydrogen
Table 1. Tools Used to Process CBRITE Metal Oxide TFT
Fig.2. Transfer Curves and Vth during Heating in Pure N2
(BCE oxide TFT on SiNx GI with W=8µm and L=3µm)
diffusion from the hydrogen-rich SiNx GI during annealing.
Examples of element “X” include In, Ga, Zn, Cd etc., and
examples of element “Y” include B, Si, Ge and Al etc. Fig.2
shows the transfer curves of such BCE type metal oxide TFT on
SiNx GI (W=8µm and L=3µm) during heating from room
temperature to 140C in pure N2 (0%O2) environment.
Strong X-O-Y bonds in the channel layer make them highly
tolerant of high concentrations of hydrogen in PECVD SiNx GI
and help inhibit oxygen loss in an oxygen-free environment at
high temperatures, resulting in excellent temperature stability.
Note that 140C is only the heater limit for in-situ testing of
transfer curves on the probe station, and stable and positive Vth
in oxygen-free environment is expected at much higher
temperature judging from the Vth vs. temperature trend in Fig.2.
Also note that the off current is below the detection limit of the
test system up to 140C, with current on/off ratio greater than 109
at Vg=±15V.
In general, robustness of the channel layer material is
proportional to its concentration of covalent bond forming “Y”
elements, as evidenced by the rapidly slowing etching rate (e.g.,
in oxalic acid) with the increase of “Y” concentration. An
example of this is illustrated in Fig.3, where the “Y” element in
this case is aluminum. However, higher concentrations of “Y”
elements also tend to decrease the carrier density and mobility,
therefore a delicate balance needs to be made between the ionic
“X-O” bonds and the covalent “Y-O” bonds when designing a
channel composition with desired mobility and stability.
Fig.3. Etch Rate in Oxalic Acid (40°C) vs. Aluminum Oxide
Concentration in Metal Oxide Semiconductor
Fig.4 shows the mobility curves together with the transfer curves
for a high-mobility BCE type metal oxide TFT on SiNx GI with
W=8µm and L=3µm. With a sharp sub-threshold slope of
0.15V/Dec, current and mobility rises very rapidly with the gate
voltage. Fig.5 shows the 5-point Id-Vg uniformity on the same
sample, where the active layer thickness non-uniformity has
been determined to be larger than 25%. It can be seen that great
Vth uniformity can still be maintained (ΔVth<0.5V) despite of
such large variation in active layer thickness, suggesting great
process latitude in manufacturing environment where film non-
uniformity can usually be controlled to under 10%.
One of the reasons for the high mobility (33 cm2
/Vs at
Vg=Vth+10V) and superb uniformity is the fact that the metal
oxide semiconductor layer is sputtered without flowing oxygen,
contrary to the conventional practice in IGZO sputtering.
Sputtering with oxygen partial pressure could cause negative
oxygen ion bombardment on the film being deposited, causing
non-uniform damage which translates to divergent transfer
Layer Tool Comparison to a-Si TFT
Gate
Sputter
Wet Etch
Same tools, materials and etchants as a-Si
TFT
GI PECVD Same tool and material (SiNx) as a-Si TFT
Channel
Sputter
Wet Etch
Same sputter tools and wet etchants as ITO
process in a-Si TFT lines, but using
proprietary channel materials with XOYO
composition and X-O-Y bonds
S/D
Sputter
Wet Etch
Same sputter tools and wet etchants as a-Si
TFT, but with no need for n+
layer dry etch
Passivation (PV)
PECVD
or Coating
Option of either PECVD PV layer or slit
coated (or spin coated) organic PV layer
Planarization (PLN)
(for High PPI LCD)
Coating
Same tools and materials for PLN process
(slit coating or spin coating)
Pixel Electrode
Sputter
Wet Etch
Same tools, materials and etchants as a-Si
TFT
Invited Paper 26-1 / T. Xiao
SID 2016 DIGEST • 319
3. curves with lower mobility. Sputtering in oxygen environment
also accelerates the change in conductivity and chemical
stoichiometry of target surface, further contributing to non-
uniform device characteristics across the substrate with
prolonged use of target. Sputtering in oxygen can also become a
major maintenance and safety issue if cryopump is used in the
sputtering system. Therefore sputtering with no oxygen not only
enhances TFT performance, but also ensures long-term stability
of active layer sputtering process, while greatly improving the
TFT fab operational efficiency and safety.
Fig.4. Mobility and Transfer Curves for BCE Type Metal
Oxide TFT on SiNx GI with W=8µm and L=3µm
Fig.5. Five-point Id-Vg Uniformity on 3” Substrate with
Active Layer Thickness Non-uniformity > 25% (BCE type
metal oxide TFT on SiNx GI with W=8µm and L=3µm)
Fig.6 shows the transfer curve uniformity of CBRITE BCE type
metal oxide TFT on 400mm x 500mm glass substrate
manufactured from an actual production line using commercial
etchant, which exhibits even tighter Vth spread (ΔVth=0.3V)
compared to Fig.5.
Fig.6. Five-point Id-Vg Uniformity of CBRITE BCE Type
Metal Oxide TFT Manufactured on 400mm x 500mm
Substrate at Production Line
Fig.7 demonstrates the superior BTS stability (especially NBTIS
stability) at 60C for CBRITE BCE type metal oxide TFT on
SiNx GI with W=8µm and L=3µm.
There is usually a trade-off between mobility and NBTIS
stability, and Table 2 summarizes the overall performance of a
“high mobility” version and a “high NBTIS stability” version
BCE process on SiNx GI intended for TFT-LCD display
products.
Fig.7. BTS stability at 60C for BCE Type Metal Oxide TFT
on SiNx GI with W=8µm and L=3µm
26-1 / T. Xiao Invited Paper
320 • SID 2016 DIGEST
4. Table 2. Performance Summary of Two Versions of BCE
Type Metal Oxide TFT on SiNx GI (W=8µm and L=3µm)
The metal oxide TFT summarized in Table 2 is ideal for high
pixel count TFT-LCD retina displays for mobile phones/pad
phones/tablets/2-in-1s/laptops applications. In addition, such
TFT is also suitable for next generation TV products with
4Kx2K and 8Kx4K formats and with high frame rate. It is also
worth noting that the use of much denser SiNx GI (as opposed to
more porous SiO2 GI required by IGZO TFT) also helps to
suppress the copper diffusion from copper gate lines used in
large size high resolution TV products.
With a passivation layer and optional PLN layer following S/D
patterning, and a pixel electrode over, one could achieve high
aperture ratio backplane for LCD or for top emission OLED. For
large size LCD and bottom emission OLED TV, one could
complete entire backplane with 4-5 masks. One of the designs
with metal oxide layer for both channel layer and transparent
pixel electrode has been disclosed[5]
. Backplane for IPS-LCD
can be achieved with a six mask process.
Fig.8 shows the uniformity and transfer/output characteristics of
a BCE type oxide TFT on SiNx GI (W=5µm, L=6µm) tailored
for OLED/LED display applications, exhibiting high mobility of
over 45 cm2
/Vs and excellent transfer and output characteristics.
Fig.8. Uniformity and Transfer/Output Characteristics of
BCE Type Metal Oxide TFT on SiNx GI with W=5µm and
L=6µm Tailored for OLED/LED Display Applications
Fig.9. Constant Current Stress Stability at 60C of BCE
Type Metal Oxide TFT on SiNx GI with W=5µm and
L=6µm Tailored for OLED/LED Display Applications
Fig.9 shows the constant current stress stability at 60C of such
TFT, which is sufficient to meet the lifetime requirements for
portable and TV OLED displays, or LED display products.
3. Conclusion
We developed an oxide TFT manufacturing process which keeps
the high-throughput SiNx GI and wet BCE process used in a-Si
TFT lines, enabling high resolution LCD and OLED/LED
display manufacturing with minimal equipment upgrade capital
expenditures and production costs.
With exceptionally wide processing latitude and superb
consistency enabled by the robust metal oxide semiconductor
material coupled with manufacturing friendly sputtering
deposition process, such metal oxide TFTs not only possess high
mobility and large current switch ratio, but also exhibit
exceptional stability sufficient for next generation LCD and
OLED/LED displays either for portable products or for large
size TVs. They are also promising for many non-display
applications including radiation imagers and
chemical/biochemical sensors.
4. References
[1] Chun Wei Wu et al., “Improvement of Stability on a-IGZO
LCD”, SID 2013 Digest, p.97-99
[2] Jae Kyeong Jeong, “Photo-bias instability of metal oxide
thin film transistors for advanced active matrix displays”,
J. Mater. Res., 28/16, 2013, p.2071-2084
[3] Ken Hoshino, Bao Yeh and John F. Wager, “Impact of
humidity on the electrical performance of amorphous oxide
semiconductor thin-film transistors”, Journal of the SID,
21/7, 2013, p.310-316
[4] Gang Yu, Chan-Long Shieh, Tian Xiao, Karman Lee,
Fatt Foong, Guangming Wang, Juergen Musolf,
Zhao Chen, Frankie Chang, Kristoffer Ottosson,
Jung-Woo Park, Jason Chen and Chen-Yue Li, “High
Throughput MOTFT with Organic Etch-Stopper and SiNx
Gate Insulator”, SID 2015 Digest, p.296-299
[5] Chan-Long Shieh, Fatt Foong and Gang Yu, US Patent
8,187,929
Invited Paper 26-1 / T. Xiao
SID 2016 DIGEST • 321